OV - exec - Loop 199

	Loop Id: 199	Module: exec	Source: ideal_gas.cpp:38-46 [...]	Coverage: 5.42%

0x42f6c0 MOV	%RDI,%RAX

0x42f6c3 CQTO

0x42f6c5 IDIV	%R14

0x42f6c8 ADD	-0x58(%RBP),%RSI    [3]

0x42f6cc ADD	-0x38(%RBP),%EDX    [3]

0x42f6cf MOVSXD	%EDX,%RAX

0x42f6d2 MOVSXD	%ESI,%RDX

0x42f6d5 MOV	%R8,%RCX

0x42f6d8 IMUL	%RDX,%RCX

0x42f6dc ADD	%RAX,%RCX

0x42f6df VMOVSD	(%R9,%RCX,8),%XMM3    [1]

0x42f6e5 VMULSD	%XMM1,%XMM3,%XMM4

0x42f6e9 MOV	%R10,%RSI

0x42f6ec IMUL	%RDX,%RSI

0x42f6f0 ADD	%RAX,%RSI

0x42f6f3 VMULSD	(%R11,%RSI,8),%XMM4,%XMM4    [2]

0x42f6f9 MOV	%R13,%RSI

0x42f6fc IMUL	%RDX,%RSI

0x42f700 ADD	%RAX,%RSI

0x42f703 VMOVSD	%XMM4,(%RBX,%RSI,8)    [5]

0x42f708 VDIVSD	%XMM3,%XMM0,%XMM3

0x42f70c VMULSD	%XMM3,%XMM3,%XMM3

0x42f710 VMULSD	%XMM2,%XMM3,%XMM3

0x42f714 VMULSD	%XMM4,%XMM3,%XMM3

0x42f718 VMULSD	(%R9,%RCX,8),%XMM3,%XMM3    [1]

0x42f71e IMUL	%R12,%RDX

0x42f722 ADD	%RAX,%RDX

0x42f725 VSQRTSD	%XMM3,%XMM3,%XMM3

0x42f729 VMOVSD	%XMM3,(%R15,%RDX,8)    [4]

0x42f72f INC	%RDI

0x42f732 CMP	-0x50(%RBP),%RDI    [3]

0x42f736 JG	42f5ef

0x42f73c MOV	%RDI,%RCX

0x42f73f SHR	$0x20,%RCX

0x42f743 JE	42f780

0x42f745 MOV	%RDI,%RAX

0x42f748 XOR	%EDX,%EDX

0x42f74a DIV	%R14

0x42f74d MOV	%RAX,%RSI

0x42f750 TEST	%RCX,%RCX

0x42f753 JNE	42f6c0

0x42f759 JMP	42f792

0x42f780 MOV	%EDI,%EAX

0x42f782 XOR	%EDX,%EDX

0x42f784 DIV	%R14D

0x42f787 MOV	%EAX,%ESI

0x42f789 TEST	%RCX,%RCX

0x42f78c JNE	42f6c0

0x42f792 MOV	%EDI,%EAX

0x42f794 XOR	%EDX,%EDX

0x42f796 DIV	%R14D

0x42f799 JMP	42f6c8

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 38 - 46

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

46:     }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.88
CQA speedup if FP arith vectorized	1.21
CQA speedup if fully vectorized	2.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.01
Bottlenecks
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	20.25
CQA cycles if fully vectorized	10.75
Front-end cycles	8.38
P0 cycles	8.00
P1 cycles	12.17
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.60
P6 cycles	4.90
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.50
P11 cycles	2.00
DIV/SQRT cycles	24.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.75
Nb uops	48.25
Nb loads	6.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.48
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.48
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	10.94
Vector-efficiency ratio other	9.61

Metric	Value
CQA speedup if no scalar integer	2.41
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P0,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	7.25
Front-end cycles	8.33
P0 cycles	8.00
P1 cycles	12.27
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.60
P6 cycles	4.80
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.60
P11 cycles	2.00
DIV/SQRT cycles	20.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	48.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.39
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.93
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.76
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	7.81

Metric	Value
CQA speedup if no scalar integer	2.88
CQA speedup if FP arith vectorized	1.21
CQA speedup if fully vectorized	2.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.03
Bottlenecks	P0,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	20.25
CQA cycles if fully vectorized	10.75
Front-end cycles	8.17
P0 cycles	8.00
P1 cycles	12.07
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.60
P6 cycles	5.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.40
P11 cycles	2.00
DIV/SQRT cycles	24.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	47.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.45
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.51
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	10.94
Vector-efficiency ratio other	10.00

Metric	Value
CQA speedup if no scalar integer	2.88
CQA speedup if FP arith vectorized	1.21
CQA speedup if fully vectorized	2.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	20.25
CQA cycles if fully vectorized	10.75
Front-end cycles	8.67
P0 cycles	8.00
P1 cycles	12.27
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.60
P6 cycles	4.80
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.60
P11 cycles	2.00
DIV/SQRT cycles	24.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	50.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.45
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	10.94
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	3.35
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.36
Bottlenecks	P0,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	24.25
CQA cycles if fully vectorized	14.25
Front-end cycles	8.33
P0 cycles	8.00
P1 cycles	12.07
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.60
P6 cycles	5.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	4.40
P11 cycles	2.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	48.00
Nb loads	6.00
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.28
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.11
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.17
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 24.50 to 10.75 cycles (2.28x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 7.21 cycles (3.40x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: multiply
1: divide
1: square root

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	41.75
nb uops	48.25
loop length	154.50
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	10.00	2.00	2.00	1.00	4.60	4.90	1.00	1.00	1.00	4.50	2.00
cycles	8.00	12.17	2.00	2.00	1.00	4.60	4.90	1.00	1.00	1.00	4.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	24.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.38
Dispatch	12.17
DIV/SQRT	24.50
Data deps.	0.00
Overall L1	24.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	10%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

0% of peak load performance is reached (1.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 8.50 cycles (2.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 20.50 to 7.25 cycles (2.83x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.50 to 12.27 cycles (1.67x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.50 to 7.33 cycles (2.80x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: multiply
1: divide
1: square root

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	42
nb uops	48
loop length	155
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	10.00	2.00	2.00	1.00	4.60	4.80	1.00	1.00	1.00	4.60	2.00
cycles	8.00	12.27	2.00	2.00	1.00	4.60	4.80	1.00	1.00	1.00	4.60	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.33
Dispatch	12.27
DIV/SQRT	20.50
Data deps.	0.00
Overall L1	20.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.50 cycles. At this rate:

1% of peak load performance is reached (2.15 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f73c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD -0x58(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x38(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%RBX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VDIVSD %XMM3,%XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R9,%RCX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSQRTSD %XMM3,%XMM3,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0x50(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 42f5ef <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 42f780 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x230>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 42f6c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
JMP 42f6c8 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x178>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 8.50 cycles (2.88x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 7.00 cycles (3.50x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: multiply
1: divide
1: square root

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	41
nb uops	47
loop length	151
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	10.00	2.00	2.00	1.00	4.60	5.00	1.00	1.00	1.00	4.40	2.00
cycles	8.00	12.07	2.00	2.00	1.00	4.60	5.00	1.00	1.00	1.00	4.40	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	24.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.17
Dispatch	12.07
DIV/SQRT	24.50
Data deps.	0.00
Overall L1	24.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	10%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

0% of peak load performance is reached (1.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f73c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
ADD -0x58(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x38(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%RBX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VDIVSD %XMM3,%XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R9,%RCX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSQRTSD %XMM3,%XMM3,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0x50(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 42f5ef <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 42f780 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x230>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 42f6c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 8.50 cycles (2.88x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.50 to 7.50 cycles (3.27x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: multiply
1: divide
1: square root

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	50
loop length	159
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	10.00	2.00	2.00	1.00	4.60	4.80	1.00	1.00	1.00	4.60	2.00
cycles	8.00	12.27	2.00	2.00	1.00	4.60	4.80	1.00	1.00	1.00	4.60	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	24.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.67
Dispatch	12.27
DIV/SQRT	24.50
Data deps.	0.00
Overall L1	24.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	10%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

0% of peak load performance is reached (1.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f73c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD -0x58(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x38(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%RBX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VDIVSD %XMM3,%XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R9,%RCX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSQRTSD %XMM3,%XMM3,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0x50(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 42f5ef <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 42f780 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x230>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 42f6c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 42f792 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x242>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
JMP 42f6c8 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x178>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.50 to 8.50 cycles (3.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 28.50 to 14.25 cycles (2.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 7.00 cycles (4.07x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: multiply
1: divide
1: square root

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	41
nb uops	48
loop length	153
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	10.00	2.00	2.00	1.00	4.60	5.00	1.00	1.00	1.00	4.40	2.00
cycles	8.00	12.07	2.00	2.00	1.00	4.60	5.00	1.00	1.00	1.00	4.40	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.33
Dispatch	12.07
DIV/SQRT	28.50
Data deps.	0.00
Overall L1	28.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

0% of peak load performance is reached (1.54 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f73c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
ADD -0x58(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x38(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%RBX,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VDIVSD %XMM3,%XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD (%R9,%RCX,8),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
IMUL %R12,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSQRTSD %XMM3,%XMM3,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0x50(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 42f5ef <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 42f780 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x230>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 42f6c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

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Vectorization

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Expensive FP math instructions/calls

Complex instructions

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

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Vectorization

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

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Slow data structures access

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Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround