OV - exec - Loop 178

	Loop Id: 178	Module: exec	Source: calc_dt.cpp:50-76 [...]	Coverage: 3.24%

0x42c180 VFMADD213SD	%XMM10,%XMM9,%XMM9

0x42c185 VSQRTSD	%XMM9,%XMM9,%XMM9

0x42c18a VMAXSD	%XMM5,%XMM9,%XMM9

0x42c18e VMINSD	%XMM18,%XMM13,%XMM10

0x42c194 VCMPSD	$0x3,%XMM18,%XMM18,%K1

0x42c19b VMOVSD	%XMM13,%XMM10,%XMM10{%K1}

0x42c1a1 VMULSD	%XMM0,%XMM10,%XMM10

0x42c1a5 VDIVSD	%XMM9,%XMM10,%XMM9

0x42c1aa VMULSD	%XMM2,%XMM15,%XMM10

0x42c1ae VANDPD	%XMM6,%XMM11,%XMM11

0x42c1b2 VANDPD	%XMM6,%XMM12,%XMM12

0x42c1b6 VMAXSD	%XMM11,%XMM12,%XMM13

0x42c1bb VCMPSD	$0x3,%XMM11,%XMM11,%K1

0x42c1c2 VMOVSD	%XMM12,%XMM13,%XMM13{%K1}

0x42c1c8 VMULSD	%XMM5,%XMM15,%XMM11

0x42c1cc VCMPSD	$0x3,%XMM13,%XMM13,%K1

0x42c1d3 VMAXSD	%XMM13,%XMM11,%XMM12

0x42c1d8 VMOVSD	%XMM11,%XMM12,%XMM12{%K1}

0x42c1de VDIVSD	%XMM12,%XMM10,%XMM10

0x42c1e3 VMULSD	%XMM4,%XMM15,%XMM12

0x42c1e7 VANDPD	%XMM6,%XMM14,%XMM13

0x42c1eb VANDPD	%XMM6,%XMM17,%XMM14

0x42c1f1 VMAXSD	%XMM13,%XMM14,%XMM15

0x42c1f6 VCMPSD	$0x3,%XMM13,%XMM13,%K1

0x42c1fd VMOVSD	%XMM14,%XMM15,%XMM15{%K1}

0x42c203 VCMPSD	$0x3,%XMM15,%XMM15,%K1

0x42c20a VMAXSD	%XMM15,%XMM11,%XMM13

0x42c20f VMOVSD	%XMM11,%XMM13,%XMM13{%K1}

0x42c215 VDIVSD	%XMM13,%XMM12,%XMM11

0x42c21a VMINSD	%XMM7,%XMM16,%XMM12

0x42c220 VMINSD	%XMM12,%XMM11,%XMM11

0x42c225 VMINSD	%XMM11,%XMM10,%XMM10

0x42c22a VMINSD	%XMM10,%XMM9,%XMM9

0x42c22f VMINSD	%XMM9,%XMM3,%XMM3

0x42c234 INC	%R14

0x42c237 CMP	-0xc0(%RBP),%R14    [10]

0x42c23e MOV	-0xb8(%RBP),%R8    [10]

0x42c245 JG	42bf96

0x42c24b MOV	%R14,%RCX

0x42c24e SHR	$0x20,%RCX

0x42c252 JE	42c280

0x42c254 MOV	%R14,%RAX

0x42c257 XOR	%EDX,%EDX

0x42c259 DIV	%R8

0x42c25c MOV	%RAX,%RSI

0x42c25f TEST	%RCX,%RCX

0x42c262 JE	42c28f

0x42c264 MOV	%R14,%RAX

0x42c267 CQTO

0x42c269 IDIV	%R8

0x42c26c JMP	42c297

0x42c280 MOV	%R14D,%EAX

0x42c283 XOR	%EDX,%EDX

0x42c285 DIV	%R8D

0x42c288 MOV	%EAX,%ESI

0x42c28a TEST	%RCX,%RCX

0x42c28d JNE	42c264

0x42c28f MOV	%R14D,%EAX

0x42c292 XOR	%EDX,%EDX

0x42c294 DIV	%R8D

0x42c297 ADD	0x60(%RBP),%ESI    [10]

0x42c29a MOV	0x68(%RBP),%RAX    [10]

0x42c29e ADD	%EAX,%EDX

0x42c2a0 MOVSXD	%EDX,%RAX

0x42c2a3 MOVSXD	%ESI,%RDX

0x42c2a6 MOV	-0xa0(%RBP),%RCX    [10]

0x42c2ad IMUL	%RDX,%RCX

0x42c2b1 ADD	%RAX,%RCX

0x42c2b4 MOV	-0x98(%RBP),%RSI    [10]

0x42c2bb VMOVSD	(%RSI,%RCX,8),%XMM9    [9]

0x42c2c0 MOV	-0x90(%RBP),%RCX    [10]

0x42c2c7 IMUL	%RDX,%RCX

0x42c2cb ADD	%RAX,%RCX

0x42c2ce MOV	-0x88(%RBP),%RSI    [10]

0x42c2d5 VMOVSD	(%RSI,%RCX,8),%XMM10    [8]

0x42c2da VADDSD	%XMM10,%XMM10,%XMM10

0x42c2df MOV	-0x80(%RBP),%RCX    [10]

0x42c2e3 IMUL	%RDX,%RCX

0x42c2e7 ADD	%RAX,%RCX

0x42c2ea MOV	-0x78(%RBP),%RSI    [10]

0x42c2ee VDIVSD	(%RSI,%RCX,8),%XMM10,%XMM10    [3]

0x42c2f3 MOV	-0x70(%RBP),%RDI    [10]

0x42c2f7 MOV	%RDI,%RCX

0x42c2fa IMUL	%RDX,%RCX

0x42c2fe LEA	(%RCX,%RAX,1),%R15

0x42c302 LEA	0x1(%RDX),%ESI

0x42c305 MOVSXD	%ESI,%RSI

0x42c308 IMUL	%RSI,%RDI

0x42c30c LEA	(%RDI,%RAX,1),%R8

0x42c310 VMOVSD	(%R10,%R8,8),%XMM11    [4]

0x42c316 VADDSD	(%R10,%R15,8),%XMM11,%XMM11    [4]

0x42c31c MOV	-0x68(%RBP),%R8    [10]

0x42c320 IMUL	%RDX,%R8

0x42c324 LEA	(%R8,%RAX,1),%R15

0x42c328 VMULSD	(%R12,%R15,8),%XMM11,%XMM11    [11]

0x42c32e LEA	0x1(%RDI,%RAX,1),%RDI

0x42c333 VMOVSD	(%R10,%RDI,8),%XMM12    [4]

0x42c339 MOV	-0xa8(%RBP),%RDI    [10]

0x42c340 VMOVSD	(%RDI,%RDX,8),%XMM13    [2]

0x42c345 LEA	0x1(%RCX,%RAX,1),%RCX

0x42c34a VADDSD	(%R10,%RCX,8),%XMM12,%XMM12    [4]

0x42c350 LEA	0x1(%R8,%RAX,1),%RCX

0x42c355 VMULSD	(%R12,%RCX,8),%XMM12,%XMM12    [11]

0x42c35b MOV	%R13,%RCX

0x42c35e IMUL	%RDX,%RCX

0x42c362 LEA	0x1(%RCX,%RAX,1),%RDI

0x42c367 VMOVSD	(%R9,%RDI,8),%XMM14    [1]

0x42c36d MOV	-0x60(%RBP),%RDI    [10]

0x42c371 ADD	%RAX,%RCX

0x42c374 VADDSD	(%R9,%RCX,8),%XMM14,%XMM14    [1]

0x42c37a IMUL	%RDX,%RDI

0x42c37e IMUL	%RBX,%RDX

0x42c382 ADD	%RAX,%RDX

0x42c385 VMULSD	(%R11,%RDX,8),%XMM14,%XMM14    [7]

0x42c38b MOV	%R13,%RCX

0x42c38e IMUL	%RSI,%RCX

0x42c392 LEA	0x1(%RCX,%RAX,1),%RDX

0x42c397 VMOVSD	(%R9,%RDX,8),%XMM15    [1]

0x42c39d ADD	%RAX,%RCX

0x42c3a0 VADDSD	(%R9,%RCX,8),%XMM15,%XMM16    [1]

0x42c3a7 ADD	%RAX,%RDI

0x42c3aa MOV	-0x58(%RBP),%RCX    [10]

0x42c3ae VMOVSD	(%RCX,%RDI,8),%XMM15    [6]

0x42c3b3 MOV	-0xb0(%RBP),%RCX    [10]

0x42c3ba VMOVSD	(%RCX,%RAX,8),%XMM18    [5]

0x42c3c1 IMUL	%RBX,%RSI

0x42c3c5 ADD	%RAX,%RSI

0x42c3c8 VMULSD	(%R11,%RSI,8),%XMM16,%XMM17    [7]

0x42c3cf VADDSD	%XMM14,%XMM11,%XMM16

0x42c3d5 VSUBSD	%XMM16,%XMM12,%XMM16

0x42c3db VADDSD	%XMM17,%XMM16,%XMM16

0x42c3e1 VADDSD	%XMM15,%XMM15,%XMM19

0x42c3e7 VDIVSD	%XMM19,%XMM16,%XMM19

0x42c3ed VUCOMISD	%XMM19,%XMM8

0x42c3f3 VMOVAPD	%XMM7,%XMM16

0x42c3f9 JBE	42c180

0x42c3ff VDIVSD	%XMM19,%XMM1,%XMM16

0x42c405 JMP	42c180

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 50 - 76

--------------------------------------------------------------------------------

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

76:     }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.12
CQA speedup if FP arith vectorized	1.31
CQA speedup if fully vectorized	2.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks	P0,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .extracted]
Source	calc_dt.cpp:50-76,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	60.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	46.25
CQA cycles if fully vectorized	27.25
Front-end cycles	26.83
P0 cycles	28.00
P1 cycles	31.80
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	0.00
P5 cycles	23.00
P6 cycles	12.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	11.33
DIV/SQRT cycles	60.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	138.00
Nb uops	152.00
Nb loads	34.00
Nb stores	0.00
Nb stack references	16.00
FLOP/cycle	0.43
Nb FLOP add-sub	9.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.43
Bytes prefetched	0.00
Bytes loaded	268.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.14
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	16.13
Vector-efficiency ratio all	13.21
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	11.36
Vector-efficiency ratio other	14.52

Metric	Value
CQA speedup if no scalar integer	2.12
CQA speedup if FP arith vectorized	1.31
CQA speedup if fully vectorized	2.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks	P0,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .extracted]
Source	calc_dt.cpp:50-76,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	60.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	46.25
CQA cycles if fully vectorized	27.25
Front-end cycles	26.83
P0 cycles	28.00
P1 cycles	31.80
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	0.00
P5 cycles	23.00
P6 cycles	12.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	11.33
DIV/SQRT cycles	60.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	138.00
Nb uops	152.00
Nb loads	34.00
Nb stores	0.00
Nb stack references	16.00
FLOP/cycle	0.43
Nb FLOP add-sub	9.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.43
Bytes prefetched	0.00
Bytes loaded	268.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.14
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	16.13
Vector-efficiency ratio all	13.21
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	11.36
Vector-efficiency ratio other	14.52

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .extracted]
Source file and lines	calc_dt.cpp:50-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-76
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 60.50 to 28.50 cycles (2.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 60.50 to 27.25 cycles (2.22x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 60.50 to 31.80 cycles (1.90x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.50 to 24.33 cycles (2.49x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 268 bytes (33 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	138
nb uops	152
loop length	632
used x86 registers	15
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.83 cycles
front end	26.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	28.00	28.00	11.33	11.33	0.00	23.00	12.00	0.00	0.00	0.00	12.00	11.33
cycles	28.00	31.80	11.33	11.33	0.00	23.00	12.00	0.00	0.00	0.00	12.00	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

60.50

Cycles summary

Front-end	26.83
Dispatch	31.80
DIV/SQRT	60.50
Overall L1	60.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	18%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	14%

INT+FP

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	11%
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.50 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c24b

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VFMADD213SD %XMM10,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM9,%XMM9,%XMM9	1	1	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMAXSD %XMM5,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM18,%XMM13,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM18,%XMM18,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM13,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM10,%XMM9	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM2,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM6,%XMM11,%XMM11	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM6,%XMM12,%XMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM11,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM11,%XMM11,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM13,%XMM13{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM5,%XMM15,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM13,%XMM13,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMAXSD %XMM13,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM12,%XMM12{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VDIVSD %XMM12,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM6,%XMM14,%XMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM6,%XMM17,%XMM14	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM13,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM13,%XMM13,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM14,%XMM15,%XMM15{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x3,%XMM15,%XMM15,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMAXSD %XMM15,%XMM11,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM13,%XMM13{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VDIVSD %XMM13,%XMM12,%XMM11	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMINSD %XMM7,%XMM16,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM12,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM10,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM9,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0xc0(%RBP),%R14	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JG 42bf96 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0xa6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
JE 42c280 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x390>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8	5	0	3	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JE 42c28f <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x39f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0.50	0	0	1	0.50	scal (12.5%)
IDIV %R8	5	0	3	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 42c297 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x3a7>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JNE 42c264 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x374>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	11-16	6	scal (6.3%)
ADD 0x60(%RBP),%ESI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x98(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM10,%XMM10,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VDIVSD (%RSI,%RCX,8),%XMM10,%XMM10	1	1	0	0.33	0.33	0	0	0	0.33	13-15	4	scal (12.5%)
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RDX),%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
IMUL %RSI,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RAX,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R10,%R8,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R10,%R15,8),%XMM11,%XMM11	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD (%R12,%R15,8),%XMM11,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
LEA 0x1(%RDI,%RAX,1),%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R10,%RDI,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDI,%RDX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX,%RAX,1),%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VADDSD (%R10,%RCX,8),%XMM12,%XMM12	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
LEA 0x1(%R8,%RAX,1),%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMULSD (%R12,%RCX,8),%XMM12,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RCX,%RAX,1),%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R9,%RDI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD (%R9,%RCX,8),%XMM14,%XMM14	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD (%R11,%RDX,8),%XMM14,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RCX,%RAX,1),%RDX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R9,%RDX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD (%R9,%RCX,8),%XMM15,%XMM16	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RDI,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM18	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RBX,%RSI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM16,%XMM17	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM14,%XMM11,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM16,%XMM12,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM16,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM15,%XMM19	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM19,%XMM16,%XMM19	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VUCOMISD %XMM19,%XMM8	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM7,%XMM16	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JBE 42c180 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x290>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VDIVSD %XMM19,%XMM1,%XMM16	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
JMP 42c180 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x290>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .extracted]
Source file and lines	calc_dt.cpp:50-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-76
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.50 to 24.33 cycles (2.49x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 268 bytes (33 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	138
nb uops	152
loop length	632
used x86 registers	15
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.83 cycles
front end	26.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	28.00	28.00	11.33	11.33	0.00	23.00	12.00	0.00	0.00	0.00	12.00	11.33
cycles	28.00	31.80	11.33	11.33	0.00	23.00	12.00	0.00	0.00	0.00	12.00	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

60.50

Cycles summary

Front-end	26.83
Dispatch	31.80
DIV/SQRT	60.50
Overall L1	60.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	18%

INT+FP

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	14%

INT+FP

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	11%
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.50 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c24b

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VFMADD213SD %XMM10,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM9,%XMM9,%XMM9	1	1	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMAXSD %XMM5,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM18,%XMM13,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM18,%XMM18,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM13,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM10,%XMM9	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM2,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM6,%XMM11,%XMM11	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM6,%XMM12,%XMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM11,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM11,%XMM11,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM13,%XMM13{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM5,%XMM15,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM13,%XMM13,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMAXSD %XMM13,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM12,%XMM12{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VDIVSD %XMM12,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %XMM6,%XMM14,%XMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM6,%XMM17,%XMM14	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM13,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM13,%XMM13,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM14,%XMM15,%XMM15{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VCMPSD $0x3,%XMM15,%XMM15,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMAXSD %XMM15,%XMM11,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM13,%XMM13{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
VDIVSD %XMM13,%XMM12,%XMM11	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMINSD %XMM7,%XMM16,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM12,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM10,%XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM9,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP -0xc0(%RBP),%R14	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JG 42bf96 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0xa6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
JE 42c280 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x390>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8	5	0	3	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JE 42c28f <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x39f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0.50	0	0	1	0.50	scal (12.5%)
IDIV %R8	5	0	3	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 42c297 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x3a7>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JNE 42c264 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x374>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	11-16	6	scal (6.3%)
ADD 0x60(%RBP),%ESI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %EAX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
MOVSXD %ESI,%RDX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x98(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM10,%XMM10,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VDIVSD (%RSI,%RCX,8),%XMM10,%XMM10	1	1	0	0.33	0.33	0	0	0	0.33	13-15	4	scal (12.5%)
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RDX),%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
IMUL %RSI,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RAX,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R10,%R8,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R10,%R15,8),%XMM11,%XMM11	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%R8	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD (%R12,%R15,8),%XMM11,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
LEA 0x1(%RDI,%RAX,1),%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R10,%RDI,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDI,%RDX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX,%RAX,1),%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VADDSD (%R10,%RCX,8),%XMM12,%XMM12	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
LEA 0x1(%R8,%RAX,1),%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMULSD (%R12,%RCX,8),%XMM12,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RCX,%RAX,1),%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R9,%RDI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD (%R9,%RCX,8),%XMM14,%XMM14	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
IMUL %RDX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD (%R11,%RDX,8),%XMM14,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RCX,%RAX,1),%RDX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMOVSD (%R9,%RDX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD (%R9,%RCX,8),%XMM15,%XMM16	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RDI,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM18	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RBX,%RSI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD (%R11,%RSI,8),%XMM16,%XMM17	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM14,%XMM11,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM16,%XMM12,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM16,%XMM16	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM15,%XMM19	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM19,%XMM16,%XMM19	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VUCOMISD %XMM19,%XMM8	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM7,%XMM16	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JBE 42c180 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x290>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VDIVSD %XMM19,%XMM1,%XMM16	1	1	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
JMP 42c180 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.extracted+0x290>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code