OV - exec - Loop 175

	Loop Id: 175	Module: exec	Source: build_field.cpp:119-129 [...]	Coverage: 0.07%

0x42aa80 MOV	%RCX,%RAX

0x42aa83 CQTO

0x42aa85 IDIV	%RBX

0x42aa88 CLTQ

0x42aa8a MOV	-0x80(%RBP),%R15    [3]

0x42aa8e IMUL	%RAX,%R15

0x42aa92 ADD	%RDX,%R15

0x42aa95 MOV	-0x78(%RBP),%R14    [3]

0x42aa99 MOVQ	$0,(%R14,%R15,8)    [9]

0x42aaa1 MOV	-0x68(%RBP),%R15    [3]

0x42aaa5 IMUL	%RAX,%R15

0x42aaa9 ADD	%RDX,%R15

0x42aaac MOV	-0x70(%RBP),%R14    [3]

0x42aab0 MOVQ	$0,(%R14,%R15,8)    [8]

0x42aab8 MOV	-0x58(%RBP),%R15    [3]

0x42aabc IMUL	%RAX,%R15

0x42aac0 ADD	%RDX,%R15

0x42aac3 MOV	-0x60(%RBP),%R14    [3]

0x42aac7 MOVQ	$0,(%R14,%R15,8)    [7]

0x42aacf MOV	%R13,%R15

0x42aad2 IMUL	%RAX,%R15

0x42aad6 ADD	%RDX,%R15

0x42aad9 MOV	-0x50(%RBP),%R14    [3]

0x42aadd MOVQ	$0,(%R14,%R15,8)    [6]

0x42aae5 MOV	%R8,%R15

0x42aae8 IMUL	%RAX,%R15

0x42aaec ADD	%RDX,%R15

0x42aaef MOV	-0x48(%RBP),%R14    [3]

0x42aaf3 MOVQ	$0,(%R14,%R15,8)    [5]

0x42aafb MOV	%R9,%R15

0x42aafe IMUL	%RAX,%R15

0x42ab02 ADD	%RDX,%R15

0x42ab05 MOVQ	$0,(%RDI,%R15,8)    [1]

0x42ab0d MOV	%R10,%R15

0x42ab10 IMUL	%RAX,%R15

0x42ab14 ADD	%RDX,%R15

0x42ab17 MOVQ	$0,(%R11,%R15,8)    [2]

0x42ab1f IMUL	%R12,%RAX

0x42ab23 ADD	%RDX,%RAX

0x42ab26 MOVQ	$0,(%RSI,%RAX,8)    [4]

0x42ab2e INC	%RCX

0x42ab31 CMP	-0x88(%RBP),%RCX    [3]

0x42ab38 JG	42a96a

0x42ab3e MOV	%RCX,%RAX

0x42ab41 OR	%RBX,%RAX

0x42ab44 SHR	$0x20,%RAX

0x42ab48 JNE	42aa80

0x42ab4e MOV	%ECX,%EAX

0x42ab50 XOR	%EDX,%EDX

0x42ab52 DIV	%EBX

0x42ab54 JMP	42aa88

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 119 - 129

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

129:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks
Function	build_field(global_variables&) [clone .extracted.27]
Source	build_field.cpp:119-129,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	13.50
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	3.25
Front-end cycles	8.50
P0 cycles	3.65
P1 cycles	13.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.00
P5 cycles	3.70
P6 cycles	3.55
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	3.60
P11 cycles	3.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.50
Nb uops	51.00
Nb loads	9.00
Nb stores	8.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.07
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.39
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	9.38
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	P1,
Function	build_field(global_variables&) [clone .extracted.27]
Source	build_field.cpp:119-129,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	13.50
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	1.50
Front-end cycles	8.50
P0 cycles	3.50
P1 cycles	13.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.00
P5 cycles	3.60
P6 cycles	3.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	3.40
P11 cycles	3.00
DIV/SQRT cycles	6.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	51.00
Nb loads	9.00
Nb stores	8.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.07
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.82
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P1,
Function	build_field(global_variables&) [clone .extracted.27]
Source	build_field.cpp:119-129,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	13.50
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	5.00
Front-end cycles	8.50
P0 cycles	3.80
P1 cycles	13.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.00
P5 cycles	3.80
P6 cycles	3.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	3.80
P11 cycles	3.00
DIV/SQRT cycles	10.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	51.00
Nb loads	9.00
Nb stores	8.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.07
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.95
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .extracted.27]
Source file and lines	build_field.cpp:119-129
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-129
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.50 to 3.25 cycles (4.15x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.50 to 10.50 cycles (1.29x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	47.50
nb uops	51
loop length	207.50
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.65	11.00	3.00	3.00	4.00	3.70	3.55	4.00	4.00	4.00	3.60	3.00
cycles	3.65	13.50	3.00	3.00	4.00	3.70	3.55	4.00	4.00	4.00	3.60	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.50
Dispatch	13.50
DIV/SQRT	8.00
Data deps.	1.00
Overall L1	13.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	build_field(global_variables&) [clone .extracted.27]
Source file and lines	build_field.cpp:119-129
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-129
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.50 to 1.50 cycles (9.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.50 to 10.50 cycles (1.29x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:121

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	48
nb uops	51
loop length	209
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	11.00	3.00	3.00	4.00	3.60	3.50	4.00	4.00	4.00	3.40	3.00
cycles	3.50	13.50	3.00	3.00	4.00	3.60	3.50	4.00	4.00	4.00	3.40	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	6.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.50
Dispatch	13.50
DIV/SQRT	6.00
Data deps.	1.00
Overall L1	13.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ab3e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x68(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x58(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%RDI,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
IMUL %R12,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x88(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 42a96a <_Z11build_fieldR16global_variables.extracted.27+0x8a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 42aa80 <_Z11build_fieldR16global_variables.extracted.27+0x1a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
JMP 42aa88 <_Z11build_fieldR16global_variables.extracted.27+0x1a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	build_field(global_variables&) [clone .extracted.27]
Source file and lines	build_field.cpp:119-129
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-129
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.50 to 10.50 cycles (1.29x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:121
CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	47
nb uops	51
loop length	206
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.80	11.00	3.00	3.00	4.00	3.80	3.60	4.00	4.00	4.00	3.80	3.00
cycles	3.80	13.50	3.00	3.00	4.00	3.80	3.60	4.00	4.00	4.00	3.80	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.50
Dispatch	13.50
DIV/SQRT	10.00
Data deps.	1.00
Overall L1	13.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ab3e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x68(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x58(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%R14,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%RDI,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%R11,%R15,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
IMUL %R12,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%RSI,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x88(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 42a96a <_Z11build_fieldR16global_variables.extracted.27+0x8a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 42aa80 <_Z11build_fieldR16global_variables.extracted.27+0x1a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code