OV - exec - Loop 154

	Loop Id: 154	Module: exec	Source: advec_mom.cpp:181-211 [...]	Coverage: 4.00%

0x428300 VSUBSD	%XMM7,%XMM3,%XMM7

0x428304 VFMADD213SD	%XMM8,%XMM10,%XMM7

0x428309 VMULSD	%XMM6,%XMM7,%XMM6

0x42830d IMUL	-0x60(%RBP),%R11    [2]

0x428312 ADD	%RAX,%R11

0x428315 VMOVSD	%XMM6,(%R15,%R11,8)    [5]

0x42831b INC	%RCX

0x42831e CMP	%RDI,%RCX

0x428321 JG	428207

0x428327 MOV	%RCX,%R8

0x42832a SHR	$0x20,%R8

0x42832e JE	428380

0x428330 MOV	%RCX,%RAX

0x428333 XOR	%EDX,%EDX

0x428335 DIV	%R14

0x428338 MOV	%RAX,%RSI

0x42833b TEST	%R8,%R8

0x42833e JE	42838e

0x428340 MOV	%RCX,%RAX

0x428343 CQTO

0x428345 IDIV	%R14

0x428348 JMP	428395

0x428380 MOV	%ECX,%EAX

0x428382 XOR	%EDX,%EDX

0x428384 DIV	%R14D

0x428387 MOV	%EAX,%ESI

0x428389 TEST	%R8,%R8

0x42838c JNE	428340

0x42838e MOV	%ECX,%EAX

0x428390 XOR	%EDX,%EDX

0x428392 DIV	%R14D

0x428395 ADD	-0x30(%RBP),%ESI    [2]

0x428398 ADD	-0x40(%RBP),%EDX    [2]

0x42839b MOVSXD	%EDX,%RAX

0x42839e MOVSXD	%ESI,%R11

0x4283a1 MOV	-0x80(%RBP),%RDX    [2]

0x4283a5 IMUL	%R11,%RDX

0x4283a9 ADD	%RAX,%RDX

0x4283ac MOV	-0x78(%RBP),%R8    [2]

0x4283b0 VMOVSD	(%R8,%RDX,8),%XMM6    [1]

0x4283b6 LEA	0x1(%R11),%R9D

0x4283ba VUCOMISD	%XMM6,%XMM0

0x4283be MOVSXD	%R9D,%R8

0x4283c1 JBE	428400

0x4283c3 ADD	$0x2,%ESI

0x4283c6 MOV	%R11,%RDX

0x4283c9 JMP	42840b

0x428400 DEC	%ESI

0x428402 MOV	%R8,%RDX

0x428405 MOV	%R11,%R8

0x428408 MOV	%ESI,%R9D

0x42840b VANDPD	%XMM1,%XMM6,%XMM7

0x42840f MOV	-0x70(%RBP),%R10    [2]

0x428413 IMUL	%R8,%R10

0x428417 ADD	%RAX,%R10

0x42841a VDIVSD	(%R13,%R10,8),%XMM7,%XMM7    [4]

0x428421 IMUL	%RBX,%R8

0x428425 ADD	%RAX,%R8

0x428428 VMOVSD	(%R12,%R8,8),%XMM8    [3]

0x42842e MOVSXD	%ESI,%RSI

0x428431 IMUL	%RBX,%RSI

0x428435 ADD	%RAX,%RSI

0x428438 IMUL	%RBX,%RDX

0x42843c ADD	%RAX,%RDX

0x42843f VMOVHPD	(%R12,%RDX,8),%XMM8,%XMM9    [3]

0x428445 VMOVSD	(%R12,%RSI,8),%XMM10    [3]

0x42844b VPUNPCKLQDQ	%XMM8,%XMM10,%XMM10

0x428450 VSUBPD	%XMM10,%XMM9,%XMM11

0x428455 VSHUFPD	$0x1,%XMM11,%XMM11,%XMM9

0x42845b VMULSD	%XMM11,%XMM9,%XMM12

0x428460 VXORPD	%XMM10,%XMM10,%XMM10

0x428465 VUCOMISD	%XMM10,%XMM12

0x42846a JBE	428300

0x428470 MOV	-0x58(%RBP),%RDX    [2]

0x428474 MOV	0x8(%RDX),%RDX    [7]

0x428478 VMOVSD	(%RDX,%R11,8),%XMM10    [6]

0x42847e VANDPD	%XMM1,%XMM11,%XMM11

0x428482 VSUBSD	%XMM7,%XMM2,%XMM12

0x428486 VADDSD	%XMM3,%XMM7,%XMM13

0x42848a VPUNPCKLQDQ	%XMM12,%XMM13,%XMM12

0x42848f MOVSXD	%R9D,%RSI

0x428492 VMULPD	%XMM12,%XMM11,%XMM12

0x428497 VMOVSD	(%RDX,%RSI,8),%XMM13    [6]

0x42849c VPUNPCKLQDQ	%XMM10,%XMM13,%XMM13

0x4284a1 VDIVPD	%XMM13,%XMM12,%XMM12

0x4284a6 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

0x4284ac VADDSD	%XMM13,%XMM12,%XMM12

0x4284b1 VMULSD	%XMM4,%XMM10,%XMM10

0x4284b5 VMULSD	%XMM12,%XMM10,%XMM10

0x4284ba VCMPSD	$0x3,%XMM10,%XMM10,%K1

0x4284c1 VMINSD	%XMM10,%XMM11,%XMM10

0x4284c6 VMOVSD	%XMM11,%XMM10,%XMM10{%K1}

0x4284cc VSHUFPS	$0x4e,%XMM11,%XMM11,%XMM11

0x4284d2 VCMPSD	$0x3,%XMM10,%XMM10,%K1

0x4284d9 VMINSD	%XMM10,%XMM11,%XMM12

0x4284de VMOVSD	%XMM11,%XMM12,%XMM12{%K1}

0x4284e4 VXORPD	%XMM5,%XMM12,%XMM10

0x4284e8 VCMPSD	$0x6,%XMM0,%XMM9,%K1

0x4284ef VMOVSD	%XMM12,%XMM10,%XMM10{%K1}

0x4284f5 JMP	428300

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 181 - 211

--------------------------------------------------------------------------------

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	2.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P0,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.7]
Source	advec_mom.cpp:181-211,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	38.00
CQA cycles if fully vectorized	19.00
Front-end cycles	19.33
P0 cycles	16.83
P1 cycles	22.47
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.50
P5 cycles	16.67
P6 cycles	13.30
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	13.20
P11 cycles	5.00
DIV/SQRT cycles	40.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	114.00
Nb loads	15.00
Nb stores	1.00
Nb stack references	7.00
FLOP/cycle	0.42
Nb FLOP add-sub	6.00
Nb FLOP mul	6.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	20.00
Vectorization ratio add_sub	16.67
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	16.67
Vectorization ratio other	28.00
Vector-efficiency ratio all	14.63
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	15.00
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.75

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	2.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P0,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.7]
Source	advec_mom.cpp:181-211,context.h:46-46,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	38.00
CQA cycles if fully vectorized	19.00
Front-end cycles	19.33
P0 cycles	16.83
P1 cycles	22.47
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.50
P5 cycles	16.67
P6 cycles	13.30
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	13.20
P11 cycles	5.00
DIV/SQRT cycles	40.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	114.00
Nb loads	15.00
Nb stores	1.00
Nb stack references	7.00
FLOP/cycle	0.42
Nb FLOP add-sub	6.00
Nb FLOP mul	6.00
Nb FLOP fma	1.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	20.00
Vectorization ratio add_sub	16.67
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	16.67
Vectorization ratio other	28.00
Vector-efficiency ratio all	14.63
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	15.00
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.7]
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 12.00 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 40.00 to 19.00 cycles (2.11x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
16% of SSE/AVX divide and square root instructions are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 40.00 to 22.47 cycles (1.78x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 16.83 cycles (2.38x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
7: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 112 bytes (14 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	114
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.33 cycles
front end	19.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.83	18.00	5.00	5.00	0.50	16.67	13.30	0.50	0.50	0.50	13.20	5.00
cycles	16.83	22.47	5.00	5.00	0.50	16.67	13.30	0.50	0.50	0.50	13.20	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

40.00

Cycles summary

Front-end	19.33
Dispatch	22.47
DIV/SQRT	40.00
Overall L1	40.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	0%
store	0%
mul	20%
add-sub	20%
fma	0%
div/sqrt	50%
other	41%

INT+FP

all	20%
load	0%
store	0%
mul	20%
add-sub	16%
fma	0%
div/sqrt	16%
other	28%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	12%
store	12%
mul	15%
add-sub	15%
fma	12%
div/sqrt	18%
other	17%

INT+FP

all	14%
load	12%
store	12%
mul	15%
add-sub	14%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (2.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428327

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM8,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL -0x60(%RBP),%R11	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM6,(%R15,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 428207 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xa7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 428380 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 42838e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x22e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 428395 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x235>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 428340 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
ADD -0x30(%RBP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x40(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %ESI,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R11,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R8,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R11),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VUCOMISD %XMM6,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVSXD %R9D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
JBE 428400 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 42840b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x2ab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VANDPD %XMM1,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOV -0x70(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R13,%R10,8),%XMM7,%XMM7	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12,%R8,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RBX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVHPD (%R12,%RDX,8),%XMM8,%XMM9	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM8,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD %XMM10,%XMM9,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM11,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM10,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 428300 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VANDPD %XMM1,%XMM11,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VSUBSD %XMM7,%XMM2,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM7,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM12,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R9D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMULPD %XMM12,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSD (%RDX,%RSI,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM10,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %XMM13,%XMM12,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VSHUFPD $0x1,%XMM12,%XMM12,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM13,%XMM12,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINSD %XMM10,%XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VSHUFPS $0x4e,%XMM11,%XMM11,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINSD %XMM10,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM12,%XMM12{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VXORPD %XMM5,%XMM12,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x6,%XMM0,%XMM9,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
JMP 428300 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.7]
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
20% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
16% of SSE/AVX divide and square root instructions are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 16.83 cycles (2.38x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
7: multiply (1 inside FMA instructions)
3: divide

The binary loop is loading 112 bytes (14 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	114
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.33 cycles
front end	19.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.83	18.00	5.00	5.00	0.50	16.67	13.30	0.50	0.50	0.50	13.20	5.00
cycles	16.83	22.47	5.00	5.00	0.50	16.67	13.30	0.50	0.50	0.50	13.20	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

40.00

Cycles summary

Front-end	19.33
Dispatch	22.47
DIV/SQRT	40.00
Overall L1	40.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	0%
store	0%
mul	20%
add-sub	20%
fma	0%
div/sqrt	50%
other	41%

INT+FP

all	20%
load	0%
store	0%
mul	20%
add-sub	16%
fma	0%
div/sqrt	16%
other	28%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	12%
store	12%
mul	15%
add-sub	15%
fma	12%
div/sqrt	18%
other	17%

INT+FP

all	14%
load	12%
store	12%
mul	15%
add-sub	14%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

1% of peak load performance is reached (2.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428327

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM8,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL -0x60(%RBP),%R11	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM6,(%R15,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 428207 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xa7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 428380 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 42838e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x22e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R14	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 428395 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x235>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 428340 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
ADD -0x30(%RBP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x40(%RBP),%EDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOVSXD %EDX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %ESI,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R11,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R8,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R11),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VUCOMISD %XMM6,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVSXD %R9D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
JBE 428400 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 42840b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x2ab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VANDPD %XMM1,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOV -0x70(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD (%R13,%R10,8),%XMM7,%XMM7	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12,%R8,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %RBX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RBX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVHPD (%R12,%RDX,8),%XMM8,%XMM9	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM8,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD %XMM10,%XMM9,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM11,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM10,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 428300 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VANDPD %XMM1,%XMM11,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VSUBSD %XMM7,%XMM2,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM7,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM12,%XMM13,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R9D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
VMULPD %XMM12,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSD (%RDX,%RSI,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM10,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %XMM13,%XMM12,%XMM12	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VSHUFPD $0x1,%XMM12,%XMM12,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM13,%XMM12,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINSD %XMM10,%XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VSHUFPS $0x4e,%XMM11,%XMM11,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINSD %XMM10,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM11,%XMM12,%XMM12{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VXORPD %XMM5,%XMM12,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x6,%XMM0,%XMM9,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM10,%XMM10{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
JMP 428300 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x1a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code