| Loop Id: 149 | Module: exec | Source: advec_cell.cpp:118-126 [...] | Coverage: 3.25% |
|---|
| Loop Id: 149 | Module: exec | Source: advec_cell.cpp:118-126 [...] | Coverage: 3.25% |
|---|
0x426d80 MOV %R13,%RAX |
0x426d83 CQTO |
0x426d85 IDIV %R14 |
0x426d88 ADD -0x98(%RBP),%RSI [5] |
0x426d8f ADD -0x40(%RBP),%EDX [5] |
0x426d92 MOVSXD %EDX,%RAX |
0x426d95 MOVSXD %ESI,%RSI |
0x426d98 MOV -0x88(%RBP),%RDX [5] |
0x426d9f IMUL %RSI,%RDX |
0x426da3 ADD %RAX,%RDX |
0x426da6 MOV -0x80(%RBP),%RCX [5] |
0x426daa IMUL %RSI,%RCX |
0x426dae ADD %RAX,%RCX |
0x426db1 MOV -0x78(%RBP),%R8 [5] |
0x426db5 VMOVSD (%R8,%RCX,8),%XMM0 [1] |
0x426dbb VMULSD (%R9,%RDX,8),%XMM0,%XMM1 [2] |
0x426dc1 MOV -0x70(%RBP),%RCX [5] |
0x426dc5 IMUL %RSI,%RCX |
0x426dc9 LEA (%RCX,%RAX,1),%R12 |
0x426dcd VADDSD (%RBX,%R12,8),%XMM1,%XMM2 [7] |
0x426dd3 LEA 0x1(%RCX,%RAX,1),%RCX |
0x426dd8 VSUBSD (%RBX,%RCX,8),%XMM2,%XMM2 [7] |
0x426ddd MOV -0x68(%RBP),%RCX [5] |
0x426de1 IMUL %RSI,%RCX |
0x426de5 ADD %RAX,%RCX |
0x426de8 VMOVSD (%R15,%RCX,8),%XMM3 [6] |
0x426dee MOV -0x30(%RBP),%R12 [5] |
0x426df2 IMUL %RSI,%R12 |
0x426df6 LEA (%R12,%RAX,1),%R8 |
0x426dfa VFMADD213SD (%RDI,%R8,8),%XMM1,%XMM3 [3] |
0x426e00 LEA 0x1(%R12,%RAX,1),%R8 |
0x426e05 VSUBSD (%RDI,%R8,8),%XMM3,%XMM1 [3] |
0x426e0b IMUL %R11,%RSI |
0x426e0f LEA (%RSI,%RAX,1),%R8 |
0x426e13 VADDSD (%R10,%R8,8),%XMM0,%XMM0 [4] |
0x426e19 LEA 0x1(%RSI,%RAX,1),%RAX |
0x426e1e VSUBSD (%R10,%RAX,8),%XMM0,%XMM0 [4] |
0x426e24 VDIVSD %XMM0,%XMM2,%XMM0 |
0x426e28 VMOVSD %XMM0,(%R9,%RDX,8) [2] |
0x426e2e VDIVSD %XMM2,%XMM1,%XMM0 |
0x426e32 VMOVSD %XMM0,(%R15,%RCX,8) [6] |
0x426e38 INC %R13 |
0x426e3b CMP -0x90(%RBP),%R13 [5] |
0x426e42 JG 426c95 |
0x426e48 MOV %R13,%RCX |
0x426e4b SHR $0x20,%RCX |
0x426e4f JE 426e80 |
0x426e51 MOV %R13,%RAX |
0x426e54 XOR %EDX,%EDX |
0x426e56 DIV %R14 |
0x426e59 MOV %RAX,%RSI |
0x426e5c TEST %RCX,%RCX |
0x426e5f JNE 426d80 |
0x426e65 JMP 426e93 |
0x426e80 MOV %R13D,%EAX |
0x426e83 XOR %EDX,%EDX |
0x426e85 DIV %R14D |
0x426e88 MOV %EAX,%ESI |
0x426e8a TEST %RCX,%RCX |
0x426e8d JNE 426d80 |
0x426e93 MOV %R13D,%EAX |
0x426e96 XOR %EDX,%EDX |
0x426e98 DIV %R14D |
0x426e9b JMP 426d88 |
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 118 - 126 |
-------------------------------------------------------------------------------- |
118: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
119: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
120: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
121: double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0); |
122: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s; |
123: double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0); |
124: density1(i, j) = post_mass_s / advec_vol_s; |
125: energy1(i, j) = post_ener_s; |
126: } |
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.00 |
| CQA speedup if FP arith vectorized | 1.20 |
| CQA speedup if fully vectorized | 2.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.41 |
| Bottlenecks | |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:118-126,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 20.00 |
| CQA cycles if fully vectorized | 10.50 |
| Front-end cycles | 11.21 |
| P0 cycles | 5.55 |
| P1 cycles | 16.97 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 1.00 |
| P5 cycles | 5.60 |
| P6 cycles | 5.45 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.40 |
| P11 cycles | 6.00 |
| DIV/SQRT cycles | 24.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 53.75 |
| Nb uops | 60.25 |
| Nb loads | 18.00 |
| Nb stores | 2.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.42 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 2.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.59 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 140.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.14 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 10.94 |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.50 |
| CQA speedup if FP arith vectorized | 1.25 |
| CQA speedup if fully vectorized | 2.86 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.17 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:118-126,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 20.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 7.00 |
| Front-end cycles | 11.17 |
| P0 cycles | 5.60 |
| P1 cycles | 17.07 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 1.00 |
| P5 cycles | 5.60 |
| P6 cycles | 5.40 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.40 |
| P11 cycles | 6.00 |
| DIV/SQRT cycles | 20.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 54.00 |
| Nb uops | 60.00 |
| Nb loads | 18.00 |
| Nb stores | 2.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 2.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 7.80 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 140.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 11.76 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 9.38 |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.00 |
| CQA speedup if FP arith vectorized | 1.20 |
| CQA speedup if fully vectorized | 2.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.42 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:118-126,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 20.00 |
| CQA cycles if fully vectorized | 10.50 |
| Front-end cycles | 11.00 |
| P0 cycles | 5.50 |
| P1 cycles | 16.87 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 1.00 |
| P5 cycles | 5.60 |
| P6 cycles | 5.50 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.40 |
| P11 cycles | 6.00 |
| DIV/SQRT cycles | 24.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 53.00 |
| Nb uops | 59.00 |
| Nb loads | 18.00 |
| Nb stores | 2.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.42 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 2.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.50 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 140.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.15 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 10.94 |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.00 |
| CQA speedup if FP arith vectorized | 1.20 |
| CQA speedup if fully vectorized | 2.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.41 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:118-126,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 20.00 |
| CQA cycles if fully vectorized | 10.50 |
| Front-end cycles | 11.50 |
| P0 cycles | 5.60 |
| P1 cycles | 17.07 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 1.00 |
| P5 cycles | 5.60 |
| P6 cycles | 5.40 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.40 |
| P11 cycles | 6.00 |
| DIV/SQRT cycles | 24.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 55.00 |
| Nb uops | 62.00 |
| Nb loads | 18.00 |
| Nb stores | 2.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.42 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 2.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.50 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 140.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.13 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 10.94 |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.50 |
| CQA speedup if FP arith vectorized | 1.17 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.66 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:118-126,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 28.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 24.00 |
| CQA cycles if fully vectorized | 14.00 |
| Front-end cycles | 11.17 |
| P0 cycles | 5.50 |
| P1 cycles | 16.87 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 1.00 |
| P5 cycles | 5.60 |
| P6 cycles | 5.50 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.40 |
| P11 cycles | 6.00 |
| DIV/SQRT cycles | 28.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 53.00 |
| Nb uops | 60.00 |
| Nb loads | 18.00 |
| Nb stores | 2.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.36 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 2.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.57 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 140.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 12.50 |
| Path / |
 |
| nb instructions | 53.75 |
| nb uops | 60.25 |
| loop length | 231.50 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 9 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 11.21 cycles |
| front end | 11.21 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.55 | 15.00 | 6.00 | 6.00 | 1.00 | 5.60 | 5.45 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| cycles | 5.55 | 16.97 | 6.00 | 6.00 | 1.00 | 5.60 | 5.45 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| Cycles executing div or sqrt instructions | 24.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.21 |
| Dispatch | 16.97 |
| DIV/SQRT | 24.00 |
| Data deps. | 0.00 |
| Overall L1 | 24.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 10% |
| other | 12% |
|
| nb instructions | 54 |
| nb uops | 60 |
| loop length | 233 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 9 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 11.17 cycles |
| front end | 11.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.60 | 15.00 | 6.00 | 6.00 | 1.00 | 5.60 | 5.40 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| cycles | 5.60 | 17.07 | 6.00 | 6.00 | 1.00 | 5.60 | 5.40 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| Cycles executing div or sqrt instructions | 20.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.17 |
| Dispatch | 17.07 |
| DIV/SQRT | 20.00 |
| Data deps. | 0.00 |
| Overall L1 | 20.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 9% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 11% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 9% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD -0x98(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| ADD -0x40(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %ESI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD (%R8,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMULSD (%R9,%RDX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RCX,%RAX,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%RBX,%R12,8),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX,%RAX,1),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RBX,%RCX,8),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| MOV -0x68(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| VMOVSD (%R15,%RCX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV -0x30(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%R12,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VFMADD213SD (%RDI,%R8,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| LEA 0x1(%R12,%RAX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RDI,%R8,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RSI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%R10,%R8,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RSI,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%R10,%RAX,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R9,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R15,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| INC %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP -0x90(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JG 426c95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0xb5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x20,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| JE 426e80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x2a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 | scal (6.3%) |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JNE 426d80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 | scal (6.3%) |
| JMP 426d88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
|
| nb instructions | 53 |
| nb uops | 59 |
| loop length | 228 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 9 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 11.00 cycles |
| front end | 11.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.50 | 15.00 | 6.00 | 6.00 | 1.00 | 5.60 | 5.50 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| cycles | 5.50 | 16.87 | 6.00 | 6.00 | 1.00 | 5.60 | 5.50 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| Cycles executing div or sqrt instructions | 24.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.00 |
| Dispatch | 16.87 |
| DIV/SQRT | 24.00 |
| Data deps. | 0.00 |
| Overall L1 | 24.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 10% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R13,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| IDIV %R14 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
| ADD -0x98(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| ADD -0x40(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %ESI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD (%R8,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMULSD (%R9,%RDX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RCX,%RAX,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%RBX,%R12,8),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX,%RAX,1),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RBX,%RCX,8),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| MOV -0x68(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| VMOVSD (%R15,%RCX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV -0x30(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%R12,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VFMADD213SD (%RDI,%R8,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| LEA 0x1(%R12,%RAX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RDI,%R8,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RSI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%R10,%R8,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RSI,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%R10,%RAX,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R9,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R15,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| INC %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP -0x90(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JG 426c95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0xb5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x20,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| JE 426e80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x2a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 | scal (6.3%) |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JNE 426d80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
|
| nb instructions | 55 |
| nb uops | 62 |
| loop length | 236 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 9 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 11.50 cycles |
| front end | 11.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.60 | 15.00 | 6.00 | 6.00 | 1.00 | 5.60 | 5.40 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| cycles | 5.60 | 17.07 | 6.00 | 6.00 | 1.00 | 5.60 | 5.40 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| Cycles executing div or sqrt instructions | 24.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.50 |
| Dispatch | 17.07 |
| DIV/SQRT | 24.00 |
| Data deps. | 0.00 |
| Overall L1 | 24.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 10% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 10% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD -0x98(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| ADD -0x40(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %ESI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD (%R8,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMULSD (%R9,%RDX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RCX,%RAX,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%RBX,%R12,8),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX,%RAX,1),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RBX,%RCX,8),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| MOV -0x68(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| VMOVSD (%R15,%RCX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV -0x30(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%R12,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VFMADD213SD (%RDI,%R8,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| LEA 0x1(%R12,%RAX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RDI,%R8,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RSI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%R10,%R8,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RSI,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%R10,%RAX,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R9,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R15,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| INC %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP -0x90(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JG 426c95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0xb5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x20,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| JE 426e80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x2a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
| MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JNE 426d80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| JMP 426e93 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x2b3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 | N/A |
| MOV %R13D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 | scal (6.3%) |
| JMP 426d88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
 |
|
| nb instructions | 53 |
| nb uops | 60 |
| loop length | 229 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 9 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 11.17 cycles |
| front end | 11.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 5.50 | 15.00 | 6.00 | 6.00 | 1.00 | 5.60 | 5.50 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| cycles | 5.50 | 16.87 | 6.00 | 6.00 | 1.00 | 5.60 | 5.50 | 1.00 | 1.00 | 1.00 | 5.40 | 6.00 |
| Cycles executing div or sqrt instructions | 28.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.17 |
| Dispatch | 16.87 |
| DIV/SQRT | 28.00 |
| Data deps. | 0.00 |
| Overall L1 | 28.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R13,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| IDIV %R14 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
| ADD -0x98(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| ADD -0x40(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOVSXD %ESI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
| MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSD (%R8,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMULSD (%R9,%RDX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| MOV -0x70(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RCX,%RAX,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%RBX,%R12,8),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RCX,%RAX,1),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RBX,%RCX,8),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| MOV -0x68(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| VMOVSD (%R15,%RCX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV -0x30(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| IMUL %RSI,%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%R12,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VFMADD213SD (%RDI,%R8,8),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (12.5%) |
| LEA 0x1(%R12,%RAX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%RDI,%R8,8),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| LEA (%RSI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VADDSD (%R10,%R8,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| LEA 0x1(%RSI,%RAX,1),%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VSUBSD (%R10,%RAX,8),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R9,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM2,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 | scal (12.5%) |
| VMOVSD %XMM0,(%R15,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| INC %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| CMP -0x90(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JG 426c95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0xb5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x20,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| JE 426e80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x2a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R13,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| DIV %R14 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
| MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JNE 426d80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x1a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |