OV - exec - Function initialise_chunk(int, global_variables&) [clone .extracted.7]

	Function: initialise_chunk(int, global_variables&) [clone .extracted.7]	Module: exec	Source: initialise_chunk.cpp:77-83 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 83

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

83:     }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42fc10 PUSH	%RBP

0x42fc11 MOV	%RSP,%RBP

0x42fc14 PUSH	%R15

0x42fc16 PUSH	%R14

0x42fc18 PUSH	%R13

0x42fc1a PUSH	%R12

0x42fc1c PUSH	%RBX

0x42fc1d SUB	$0x18,%RSP

0x42fc21 MOVL	$0,-0x30(%RBP)

0x42fc28 MOV	%R9,%RBX

0x42fc2b MOV	%R8,%R15

0x42fc2e MOV	%RCX,%R12

0x42fc31 MOV	%RDX,%R13

0x42fc34 MOV	(%RDI),%ESI

0x42fc36 MOVQ	$0,-0x38(%RBP)

0x42fc3e MOVQ	$0x1,-0x40(%RBP)

0x42fc46 SUB	$0x8,%RSP

0x42fc4a LEA	-0x40(%RBP),%RAX

0x42fc4e LEA	-0x30(%RBP),%RCX

0x42fc52 LEA	-0x38(%RBP),%R8

0x42fc56 LEA	0x18(%RBP),%R9

0x42fc5a MOV	$0x47a270,%EDI

0x42fc5f MOV	%ESI,-0x2c(%RBP)

0x42fc62 MOV	$0x22,%EDX

0x42fc67 PUSH	$0x1

0x42fc69 PUSH	$0x1

0x42fc6b PUSH	%RAX

0x42fc6c CALL	403200 <__kmpc_for_static_init_8@plt>

0x42fc71 ADD	$0x20,%RSP

0x42fc75 MOV	-0x38(%RBP),%RCX

0x42fc79 MOV	0x18(%RBP),%RSI

0x42fc7d CMP	%RSI,%RCX

0x42fc80 JBE	42fcc0

0x42fc82 MOV	$0x47a290,%EDI

0x42fc87 MOV	-0x2c(%RBP),%ESI

0x42fc8a ADD	$0x18,%RSP

0x42fc8e POP	%RBX

0x42fc8f POP	%R12

0x42fc91 POP	%R13

0x42fc93 POP	%R14

0x42fc95 POP	%R15

0x42fc97 POP	%RBP

0x42fc98 JMP	403050

0x42fc9d NOPW	%CS:(%RAX,%RAX,1)

0x42fcac NOPW	%CS:(%RAX,%RAX,1)

0x42fcbb NOPL	(%RAX,%RAX,1)

0x42fcc0 VMOVQ	%R13,%XMM0

0x42fcc5 VMOVQ	%R12,%XMM1

0x42fcca VMULSD	%XMM0,%XMM1,%XMM0

0x42fcce MOV	0x2a0(%R15),%RDI

0x42fcd5 MOV	0x290(%R15),%R14

0x42fcdc MOV	0x228(%R15),%R9

0x42fce3 MOV	0x248(%R15),%R10

0x42fcea MOV	0x2b8(%R15),%R11

0x42fcf1 MOV	0x2a8(%R15),%R12

0x42fcf8 MOV	0x2d0(%R15),%R13

0x42fcff MOV	0x2c0(%R15),%R15

0x42fd06 JMP	42fd90

0x42fd0b NOPW	%CS:(%RAX,%RAX,1)

0x42fd1a NOPW	%CS:(%RAX,%RAX,1)

0x42fd29 NOPW	%CS:(%RAX,%RAX,1)

0x42fd38 NOPL	(%RAX,%RAX,1)

(202) 0x42fd40 MOV	%RCX,%RAX

(202) 0x42fd43 CQTO

(202) 0x42fd45 IDIV	%RBX

(202) 0x42fd48 CLTQ

(202) 0x42fd4a MOV	%R14,%R8

(202) 0x42fd4d IMUL	%RAX,%R8

(202) 0x42fd51 ADD	%RDX,%R8

(202) 0x42fd54 VMOVSD	%XMM0,(%RDI,%R8,8)

(202) 0x42fd5a VMOVSD	(%R10,%RAX,8),%XMM1

(202) 0x42fd60 MOV	%R12,%R8

(202) 0x42fd63 IMUL	%RAX,%R8

(202) 0x42fd67 ADD	%RDX,%R8

(202) 0x42fd6a VMOVSD	%XMM1,(%R11,%R8,8)

(202) 0x42fd70 VMOVSD	(%R9,%RDX,8),%XMM1

(202) 0x42fd76 IMUL	%R15,%RAX

(202) 0x42fd7a ADD	%RDX,%RAX

(202) 0x42fd7d VMOVSD	%XMM1,(%R13,%RAX,8)

(202) 0x42fd84 INC	%RCX

(202) 0x42fd87 CMP	%RSI,%RCX

(202) 0x42fd8a JG	42fc82

(202) 0x42fd90 MOV	%RCX,%RAX

(202) 0x42fd93 OR	%RBX,%RAX

(202) 0x42fd96 SHR	$0x20,%RAX

(202) 0x42fd9a JNE	42fd40

(202) 0x42fd9c MOV	%ECX,%EAX

(202) 0x42fd9e XOR	%EDX,%EDX

(202) 0x42fda0 DIV	%EBX

(202) 0x42fda2 JMP	42fd48

0x42fda4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	initialise_chunk.cpp:77-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-83
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 2.00 cycles (5.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.67 to 0.77 cycles (13.81x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 88 bytes (11 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	64
loop length	316
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.60	1.50	6.00	6.00	7.00	2.00	1.50	7.00	7.00	7.00	1.40	6.00
cycles	1.60	1.50	6.00	6.00	7.00	2.00	1.50	7.00	7.00	7.00	1.40	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	7.00
Overall L1	10.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.67 cycles. At this rate:

4% of peak load performance is reached (8.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 7.00 cycles (1.52x speedup).

ASM code

In the binary file, the address of the function is: 42fc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x47a270,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403200 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 42fcc0 <_Z16initialise_chunkiR16global_variables.extracted.7+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x47a290,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R12,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x2a0(%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x290(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x228(%R15),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x248(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2b8(%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2a8(%R15),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2d0(%R15),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2c0(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 42fd90 <_Z16initialise_chunkiR16global_variables.extracted.7+0x180>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	initialise_chunk.cpp:77-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-83
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 2.00 cycles (5.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 88 bytes (11 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	64
loop length	316
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.60	1.50	6.00	6.00	7.00	2.00	1.50	7.00	7.00	7.00	1.40	6.00
cycles	1.60	1.50	6.00	6.00	7.00	2.00	1.50	7.00	7.00	7.00	1.40	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	7.00
Overall L1	10.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.67 cycles. At this rate:

4% of peak load performance is reached (8.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42fc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x47a270,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403200 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 42fcc0 <_Z16initialise_chunkiR16global_variables.extracted.7+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x47a290,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R12,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x2a0(%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x290(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x228(%R15),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x248(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2b8(%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2a8(%R15),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2d0(%R15),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x2c0(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 42fd90 <_Z16initialise_chunkiR16global_variables.extracted.7+0x180>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone .extracted.7]–	0.03	0.01
○Loop 202 - initialise_chunk.cpp:78-83 - exec	0.03	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code