OV - exec - Function generate_chunk(int, global

	Function: generate_chunk(int, global_variables&) [clone .extracted]	Module: exec	Source: generate_chunk.cpp:85-128 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 128

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

124:               }

125:             }

126:           }

127:         }

128:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42e6f0 PUSH	%RBP

0x42e6f1 MOV	%RSP,%RBP

0x42e6f4 PUSH	%R15

0x42e6f6 PUSH	%R14

0x42e6f8 PUSH	%R13

0x42e6fa PUSH	%R12

0x42e6fc PUSH	%RBX

0x42e6fd SUB	$0xb8,%RSP

0x42e704 MOV	%R9,-0xa0(%RBP)

0x42e70b MOV	%R8,-0x98(%RBP)

0x42e712 MOV	%RCX,-0x90(%RBP)

0x42e719 MOV	%RDX,-0x88(%RBP)

0x42e720 MOV	0x60(%RBP),%RAX

0x42e724 MOV	0x50(%RBP),%R13

0x42e728 MOV	0x48(%RBP),%RBX

0x42e72c MOV	0x40(%RBP),%RDX

0x42e730 MOV	0x38(%RBP),%R14

0x42e734 MOV	0x30(%RBP),%RCX

0x42e738 MOV	%RCX,-0xd0(%RBP)

0x42e73f MOV	0x28(%RBP),%RCX

0x42e743 MOV	0x20(%RBP),%R15

0x42e747 MOV	0x18(%RBP),%RSI

0x42e74b MOV	%RSI,-0xc8(%RBP)

0x42e752 MOV	0x10(%RBP),%R12

0x42e756 MOVL	$0,-0xa8(%RBP)

0x42e760 TEST	%RAX,%RAX

0x42e763 JS	42e840

0x42e769 MOV	%RCX,-0xc0(%RBP)

0x42e770 MOV	(%RDI),%ESI

0x42e772 MOVQ	$0,-0xb8(%RBP)

0x42e77d MOV	%RAX,-0xb0(%RBP)

0x42e784 MOVQ	$0x1,-0xd8(%RBP)

0x42e78f SUB	$0x8,%RSP

0x42e793 LEA	-0xd8(%RBP),%RAX

0x42e79a LEA	-0xa8(%RBP),%RCX

0x42e7a1 LEA	-0xb8(%RBP),%R8

0x42e7a8 MOV	%RDX,-0x68(%RBP)

0x42e7ac LEA	-0xb0(%RBP),%R9

0x42e7b3 MOV	$0x47a0f0,%EDI

0x42e7b8 MOV	%ESI,-0xa4(%RBP)

0x42e7be MOV	$0x22,%EDX

0x42e7c3 PUSH	$0x1

0x42e7c5 PUSH	$0x1

0x42e7c7 PUSH	%RAX

0x42e7c8 CALL	403200 <__kmpc_for_static_init_8@plt>

0x42e7cd MOV	-0x68(%RBP),%RDI

0x42e7d1 ADD	$0x20,%RSP

0x42e7d5 MOV	-0xb8(%RBP),%R9

0x42e7dc MOV	-0xb0(%RBP),%R11

0x42e7e3 CMP	%R11,%R9

0x42e7e6 JBE	42e880

0x42e7ec MOV	$0x47a110,%EDI

0x42e7f1 MOV	-0xa4(%RBP),%ESI

0x42e7f7 ADD	$0xb8,%RSP

0x42e7fe POP	%RBX

0x42e7ff POP	%R12

0x42e801 POP	%R13

0x42e803 POP	%R14

0x42e805 POP	%R15

0x42e807 POP	%RBP

0x42e808 JMP	403050

0x42e80d NOPW	%CS:(%RAX,%RAX,1)

0x42e81c NOPW	%CS:(%RAX,%RAX,1)

0x42e82b NOPW	%CS:(%RAX,%RAX,1)

0x42e83a NOPW	(%RAX,%RAX,1)

0x42e840 ADD	$0xb8,%RSP

0x42e847 POP	%RBX

0x42e848 POP	%R12

0x42e84a POP	%R13

0x42e84c POP	%R14

0x42e84e POP	%R15

0x42e850 POP	%RBP

0x42e851 RET

0x42e852 NOPW	%CS:(%RAX,%RAX,1)

0x42e861 NOPW	%CS:(%RAX,%RAX,1)

0x42e870 NOPW	%CS:(%RAX,%RAX,1)

0x42e87f NOP

0x42e880 MOVSXD	%EBX,%R8

0x42e883 MOV	(%R14,%R8,4),%EBX

0x42e887 VMOVSD	(%R12,%R8,8),%XMM0

0x42e88d VMOVSD	(%R15,%R8,8),%XMM1

0x42e893 LEA	0x1(%R9),%RAX

0x42e897 INC	%R11

0x42e89a CMP	%R11,%RAX

0x42e89d CMOVG	%RAX,%R11

0x42e8a1 SUB	%R9,%R11

0x42e8a4 XOR	%R10D,%R10D

0x42e8a7 MOV	%R13,-0x80(%RBP)

0x42e8ab MOV	%R9,-0x78(%RBP)

0x42e8af MOV	%R11,-0x70(%RBP)

0x42e8b3 MOV	%EBX,-0x5c(%RBP)

0x42e8b6 JMP	42e8fc

0x42e8b8 NOPL	(%RAX,%RAX,1)

(194) 0x42e8c0 MOV	-0x50(%RBP),%RSI

(194) 0x42e8c4 LEA	(%RSI,%RAX,8),%RDX

(194) 0x42e8c8 VMOVSD	(%R15,%R8,8),%XMM2

(194) 0x42e8ce VMOVSD	%XMM2,(%RDX)

(194) 0x42e8d2 MOV	-0x30(%RBP),%RCX

(194) 0x42e8d6 VMOVSD	(%RCX),%XMM2

(194) 0x42e8da VMOVSD	%XMM2,0x8(%R12,%R14,8)

(194) 0x42e8e1 VMOVSD	(%R15,%R8,8),%XMM2

(194) 0x42e8e7 VMOVSD	%XMM2,0x8(%RSI,%RAX,8)

(194) 0x42e8ed NOPL	(%RAX)

(194) 0x42e8f0 INC	%R10

(194) 0x42e8f3 CMP	%R11,%R10

(194) 0x42e8f6 JE	42e7ec

(194) 0x42e8fc LEA	(%R9,%R10,1),%RAX

(194) 0x42e900 MOV	%RAX,%RCX

(194) 0x42e903 OR	%R13,%RCX

(194) 0x42e906 SHR	$0x20,%RCX

(194) 0x42e90a JE	42ebc0

(194) 0x42e910 CQTO

(194) 0x42e912 IDIV	%R13

(194) 0x42e915 MOV	%RDX,%R14

(194) 0x42e918 MOV	%RAX,%RSI

(194) 0x42e91b CMP	$0x3,%EBX

(194) 0x42e91e JE	42ebd3

(194) 0x42e924 CMP	$0x2,%EBX

(194) 0x42e927 JE	42edc0

(194) 0x42e92d CMP	$0x1,%EBX

(194) 0x42e930 JNE	42e8f0

(194) 0x42e932 MOV	0x258(%RDI),%RAX

(194) 0x42e939 MOVSXD	%R14D,%RCX

(194) 0x42e93c VMOVSD	0x8(%RAX,%RCX,8),%XMM2

(194) 0x42e942 VUCOMISD	%XMM0,%XMM2

(194) 0x42e946 JB	42e8f0

(194) 0x42e948 MOV	-0xc8(%RBP),%RCX

(194) 0x42e94f VMOVSD	(%RCX,%R8,8),%XMM2

(194) 0x42e955 VUCOMISD	(%RAX,%R14,8),%XMM2

(194) 0x42e95b JBE	42e8f0

(194) 0x42e95d MOV	0x278(%RDI),%RAX

(194) 0x42e964 SAL	$0x20,%RSI

(194) 0x42e968 MOV	$0x100000000,%RCX

(194) 0x42e972 LEA	(%RSI,%RCX,1),%R15

(194) 0x42e976 MOV	%R15,%RCX

(194) 0x42e979 SAR	$0x1d,%RCX

(194) 0x42e97d VMOVSD	(%RAX,%RCX,1),%XMM2

(194) 0x42e982 VUCOMISD	%XMM1,%XMM2

(194) 0x42e986 JB	42e8f0

(194) 0x42e98c MOV	%RSI,%RCX

(194) 0x42e98f SAR	$0x1d,%RCX

(194) 0x42e993 MOV	-0xc0(%RBP),%RDX

(194) 0x42e99a VMOVSD	(%RDX,%R8,8),%XMM2

(194) 0x42e9a0 VUCOMISD	(%RAX,%RCX,1),%XMM2

(194) 0x42e9a5 JBE	42e8f0

(194) 0x42e9ab SAR	$0x20,%RSI

(194) 0x42e9af MOV	-0x90(%RBP),%RAX

(194) 0x42e9b6 MOV	0x8(%RAX),%RAX

(194) 0x42e9ba MOV	0x40(%RDI),%RCX

(194) 0x42e9be MOV	0x30(%RDI),%RDX

(194) 0x42e9c2 IMUL	%RSI,%RDX

(194) 0x42e9c6 ADD	%R14,%RDX

(194) 0x42e9c9 VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42e9cf VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42e9d4 MOV	-0x88(%RBP),%RAX

(194) 0x42e9db MOV	0x8(%RAX),%RAX

(194) 0x42e9df MOV	0x10(%RDI),%RCX

(194) 0x42e9e3 MOV	(%RDI),%RDX

(194) 0x42e9e6 IMUL	%RSI,%RDX

(194) 0x42e9ea MOV	%R14,-0x40(%RBP)

(194) 0x42e9ee ADD	%R14,%RDX

(194) 0x42e9f1 VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42e9f7 VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42e9fc SAR	$0x20,%R15

(194) 0x42ea00 MOV	-0x98(%RBP),%RAX

(194) 0x42ea07 MOV	0x8(%RAX),%R12

(194) 0x42ea0b MOV	0xa8(%RDI),%RAX

(194) 0x42ea12 MOV	%RAX,-0x30(%RBP)

(194) 0x42ea16 MOV	0xb8(%RDI),%RAX

(194) 0x42ea1d MOV	%RAX,-0x58(%RBP)

(194) 0x42ea21 MOV	-0xa0(%RBP),%RAX

(194) 0x42ea28 MOV	%R15,%RCX

(194) 0x42ea2b MOV	0x8(%RAX),%R15

(194) 0x42ea2f MOV	0xe8(%RDI),%RAX

(194) 0x42ea36 MOV	%RAX,-0x50(%RBP)

(194) 0x42ea3a MOV	0xd8(%RDI),%RAX

(194) 0x42ea41 MOV	%RAX,-0x48(%RBP)

(194) 0x42ea45 INC	%RCX

(194) 0x42ea48 LEA	0x1(%RSI),%RAX

(194) 0x42ea4c CMP	%RAX,%RCX

(194) 0x42ea4f CMOVLE	%RAX,%RCX

(194) 0x42ea53 SUB	%RSI,%RCX

(194) 0x42ea56 MOV	%RCX,-0x38(%RBP)

(194) 0x42ea5a CMP	$0x2,%RCX

(194) 0x42ea5e JB	42eb3d

(194) 0x42ea64 MOV	-0x38(%RBP),%RCX

(194) 0x42ea68 SHR	$0x1,%RCX

(194) 0x42ea6b NEG	%RCX

(194) 0x42ea6e MOV	-0x48(%RBP),%R9

(194) 0x42ea72 LEA	(,%R9,8),%RDI

(194) 0x42ea7a MOV	%RDI,%R14

(194) 0x42ea7d IMUL	%RAX,%R14

(194) 0x42ea81 MOV	-0x50(%RBP),%R11

(194) 0x42ea85 ADD	%R11,%R14

(194) 0x42ea88 MOV	-0x40(%RBP),%RDX

(194) 0x42ea8c LEA	0x8(,%RDX,8),%R13

(194) 0x42ea94 SAL	$0x4,%R9

(194) 0x42ea98 IMUL	%RSI,%RDI

(194) 0x42ea9c ADD	%R11,%RDI

(194) 0x42ea9f MOV	-0x30(%RBP),%RBX

(194) 0x42eaa3 LEA	(,%RBX,8),%R11

(194) 0x42eaab IMUL	%R11,%RAX

(194) 0x42eaaf MOV	-0x58(%RBP),%RDX

(194) 0x42eab3 ADD	%RDX,%RAX

(194) 0x42eab6 SAL	$0x4,%RBX

(194) 0x42eaba IMUL	%RSI,%R11

(194) 0x42eabe ADD	%RDX,%R11

(194) 0x42eac1 MOV	%R13,%RDX

(194) 0x42eac4 NOPW	%CS:(%RAX,%RAX,1)

  (196) 0x42ead0 VMOVSD	(%R12,%R8,8),%XMM2

  (196) 0x42ead6 VMOVSD	%XMM2,-0x8(%R11,%R13,1)

  (196) 0x42eadd VMOVSD	(%R15,%R8,8),%XMM2

  (196) 0x42eae3 VMOVSD	%XMM2,-0x8(%RDI,%RDX,1)

  (196) 0x42eae9 VMOVSD	(%R12,%R8,8),%XMM2

  (196) 0x42eaef VMOVSD	%XMM2,(%R11,%R13,1)

  (196) 0x42eaf5 VMOVSD	(%R15,%R8,8),%XMM2

  (196) 0x42eafb VMOVSD	%XMM2,(%RDI,%RDX,1)

  (196) 0x42eb00 VMOVSD	(%R12,%R8,8),%XMM2

  (196) 0x42eb06 VMOVSD	%XMM2,-0x8(%RAX,%R13,1)

  (196) 0x42eb0d VMOVSD	(%R15,%R8,8),%XMM2

  (196) 0x42eb13 VMOVSD	%XMM2,-0x8(%R14,%RDX,1)

  (196) 0x42eb1a VMOVSD	(%R12,%R8,8),%XMM2

  (196) 0x42eb20 VMOVSD	%XMM2,(%RAX,%R13,1)

  (196) 0x42eb26 VMOVSD	(%R15,%R8,8),%XMM2

  (196) 0x42eb2c VMOVSD	%XMM2,(%R14,%RDX,1)

  (196) 0x42eb32 ADD	%R9,%RDX

  (196) 0x42eb35 ADD	%RBX,%R13

  (196) 0x42eb38 INC	%RCX

  (196) 0x42eb3b JNE	42ead0

(194) 0x42eb3d MOV	-0x38(%RBP),%RCX

(194) 0x42eb41 MOV	%RCX,%RAX

(194) 0x42eb44 AND	$-0x2,%RAX

(194) 0x42eb48 CMP	%RCX,%RAX

(194) 0x42eb4b MOV	-0x80(%RBP),%R13

(194) 0x42eb4f MOV	-0x68(%RBP),%RDI

(194) 0x42eb53 MOV	-0x78(%RBP),%R9

(194) 0x42eb57 MOV	-0x70(%RBP),%R11

(194) 0x42eb5b MOV	-0x5c(%RBP),%EBX

(194) 0x42eb5e MOV	-0x40(%RBP),%RDX

(194) 0x42eb62 JE	42e8f0

(194) 0x42eb68 MOV	%RAX,%RCX

(194) 0x42eb6b MOV	-0x30(%RBP),%R14

(194) 0x42eb6f IMUL	%R14,%RCX

(194) 0x42eb73 IMUL	%RSI,%R14

(194) 0x42eb77 ADD	%RDX,%R14

(194) 0x42eb7a ADD	%RCX,%R14

(194) 0x42eb7d VMOVSD	(%R12,%R8,8),%XMM2

(194) 0x42eb83 MOV	-0x58(%RBP),%RDX

(194) 0x42eb87 VMOVSD	%XMM2,(%RDX,%R14,8)

(194) 0x42eb8d LEA	(%R12,%R8,8),%RCX

(194) 0x42eb91 MOV	%RCX,-0x30(%RBP)

(194) 0x42eb95 MOV	%RDX,%R12

(194) 0x42eb98 MOV	-0x48(%RBP),%RCX

(194) 0x42eb9c IMUL	%RCX,%RSI

(194) 0x42eba0 ADD	-0x40(%RBP),%RSI

(194) 0x42eba4 IMUL	%RCX,%RAX

(194) 0x42eba8 ADD	%RSI,%RAX

(194) 0x42ebab JMP	42e8c0

0x42ebb0 NOPW	%CS:(%RAX,%RAX,1)

0x42ebbf NOP

(194) 0x42ebc0 XOR	%EDX,%EDX

(194) 0x42ebc2 DIV	%R13D

(194) 0x42ebc5 MOV	%EDX,%R14D

(194) 0x42ebc8 MOV	%EAX,%ESI

(194) 0x42ebca CMP	$0x3,%EBX

(194) 0x42ebcd JNE	42e924

(194) 0x42ebd3 MOV	0x258(%RDI),%RAX

(194) 0x42ebda VMOVSD	(%RAX,%R14,8),%XMM2

(194) 0x42ebe0 VUCOMISD	%XMM0,%XMM2

(194) 0x42ebe4 JNE	42e8f0

(194) 0x42ebea JP	42e8f0

(194) 0x42ebf0 MOV	0x278(%RDI),%RAX

(194) 0x42ebf7 MOVSXD	%ESI,%R12

(194) 0x42ebfa VMOVSD	(%RAX,%R12,8),%XMM2

(194) 0x42ec00 VUCOMISD	%XMM1,%XMM2

(194) 0x42ec04 JNE	42e8f0

(194) 0x42ec0a JP	42e8f0

(194) 0x42ec10 SAL	$0x20,%RSI

(194) 0x42ec14 MOV	-0x90(%RBP),%RAX

(194) 0x42ec1b MOV	0x8(%RAX),%RAX

(194) 0x42ec1f MOV	0x40(%RDI),%RCX

(194) 0x42ec23 MOV	0x30(%RDI),%RDX

(194) 0x42ec27 IMUL	%R12,%RDX

(194) 0x42ec2b ADD	%R14,%RDX

(194) 0x42ec2e VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42ec34 VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42ec39 MOV	-0x88(%RBP),%RAX

(194) 0x42ec40 MOV	0x8(%RAX),%RAX

(194) 0x42ec44 MOV	0x10(%RDI),%RCX

(194) 0x42ec48 MOV	(%RDI),%RDX

(194) 0x42ec4b IMUL	%R12,%RDX

(194) 0x42ec4f MOV	%R14,-0x40(%RBP)

(194) 0x42ec53 ADD	%R14,%RDX

(194) 0x42ec56 VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42ec5c VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42ec61 MOV	-0x98(%RBP),%RAX

(194) 0x42ec68 MOV	0x8(%RAX),%RCX

(194) 0x42ec6c MOV	0xa8(%RDI),%RAX

(194) 0x42ec73 MOV	%RAX,-0x30(%RBP)

(194) 0x42ec77 MOV	0xb8(%RDI),%RAX

(194) 0x42ec7e MOV	%RAX,-0x58(%RBP)

(194) 0x42ec82 MOV	-0xa0(%RBP),%RAX

(194) 0x42ec89 MOV	0x8(%RAX),%R15

(194) 0x42ec8d MOV	0xe8(%RDI),%RAX

(194) 0x42ec94 MOV	%RAX,-0x50(%RBP)

(194) 0x42ec98 MOV	0xd8(%RDI),%RAX

(194) 0x42ec9f MOV	%RAX,-0x48(%RBP)

(194) 0x42eca3 MOV	$0x100000000,%RAX

(194) 0x42ecad ADD	%RAX,%RSI

(194) 0x42ecb0 SAR	$0x20,%RSI

(194) 0x42ecb4 INC	%RSI

(194) 0x42ecb7 LEA	0x1(%R12),%RAX

(194) 0x42ecbc CMP	%RAX,%RSI

(194) 0x42ecbf CMOVLE	%RAX,%RSI

(194) 0x42ecc3 MOV	%R12,-0x38(%RBP)

(194) 0x42ecc7 SUB	%R12,%RSI

(194) 0x42ecca CMP	$0x2,%RSI

(194) 0x42ecce JB	42ef9c

(194) 0x42ecd4 MOV	%RSI,%RDI

(194) 0x42ecd7 SHR	$0x1,%RDI

(194) 0x42ecda NEG	%RDI

(194) 0x42ecdd MOV	-0x48(%RBP),%R11

(194) 0x42ece1 LEA	(,%R11,8),%R12

(194) 0x42ece9 MOV	%R12,%R13

(194) 0x42ecec IMUL	%RAX,%R13

(194) 0x42ecf0 MOV	-0x50(%RBP),%R9

(194) 0x42ecf4 ADD	%R9,%R13

(194) 0x42ecf7 MOV	-0x40(%RBP),%RDX

(194) 0x42ecfb LEA	0x8(,%RDX,8),%R14

(194) 0x42ed03 SAL	$0x4,%R11

(194) 0x42ed07 IMUL	-0x38(%RBP),%R12

(194) 0x42ed0c ADD	%R9,%R12

(194) 0x42ed0f MOV	-0x30(%RBP),%RDX

(194) 0x42ed13 LEA	(,%RDX,8),%RBX

(194) 0x42ed1b IMUL	%RBX,%RAX

(194) 0x42ed1f MOV	-0x58(%RBP),%R9

(194) 0x42ed23 ADD	%R9,%RAX

(194) 0x42ed26 SAL	$0x4,%RDX

(194) 0x42ed2a IMUL	-0x38(%RBP),%RBX

(194) 0x42ed2f ADD	%R9,%RBX

(194) 0x42ed32 MOV	%R14,%R9

(194) 0x42ed35 NOPW	%CS:(%RAX,%RAX,1)

  (197) 0x42ed40 VMOVSD	(%RCX,%R8,8),%XMM2

  (197) 0x42ed46 VMOVSD	%XMM2,-0x8(%RBX,%R14,1)

  (197) 0x42ed4d VMOVSD	(%R15,%R8,8),%XMM2

  (197) 0x42ed53 VMOVSD	%XMM2,-0x8(%R12,%R9,1)

  (197) 0x42ed5a VMOVSD	(%RCX,%R8,8),%XMM2

  (197) 0x42ed60 VMOVSD	%XMM2,(%RBX,%R14,1)

  (197) 0x42ed66 VMOVSD	(%R15,%R8,8),%XMM2

  (197) 0x42ed6c VMOVSD	%XMM2,(%R12,%R9,1)

  (197) 0x42ed72 VMOVSD	(%RCX,%R8,8),%XMM2

  (197) 0x42ed78 VMOVSD	%XMM2,-0x8(%RAX,%R14,1)

  (197) 0x42ed7f VMOVSD	(%R15,%R8,8),%XMM2

  (197) 0x42ed85 VMOVSD	%XMM2,-0x8(%R13,%R9,1)

  (197) 0x42ed8c VMOVSD	(%RCX,%R8,8),%XMM2

  (197) 0x42ed92 VMOVSD	%XMM2,(%RAX,%R14,1)

  (197) 0x42ed98 VMOVSD	(%R15,%R8,8),%XMM2

  (197) 0x42ed9e VMOVSD	%XMM2,(%R13,%R9,1)

  (197) 0x42eda5 ADD	%R11,%R9

  (197) 0x42eda8 ADD	%RDX,%R14

  (197) 0x42edab INC	%RDI

  (197) 0x42edae JNE	42ed40

(194) 0x42edb0 JMP	42ef9c

0x42edb5 NOPW	%CS:(%RAX,%RAX,1)

(194) 0x42edc0 MOV	0x218(%RDI),%RAX

(194) 0x42edc7 MOV	0x238(%RDI),%RCX

(194) 0x42edce VMOVSD	(%RAX,%R14,8),%XMM2

(194) 0x42edd4 VSUBSD	%XMM0,%XMM2,%XMM2

(194) 0x42edd8 VMULSD	%XMM2,%XMM2,%XMM2

(194) 0x42eddc MOVSXD	%ESI,%R12

(194) 0x42eddf VMOVSD	(%RCX,%R12,8),%XMM3

(194) 0x42ede5 VSUBSD	%XMM1,%XMM3,%XMM3

(194) 0x42ede9 VFMADD213SD	%XMM2,%XMM3,%XMM3

(194) 0x42edee VSQRTSD	%XMM3,%XMM3,%XMM2

(194) 0x42edf2 MOV	-0xd0(%RBP),%RAX

(194) 0x42edf9 VMOVSD	(%RAX,%R8,8),%XMM3

(194) 0x42edff VUCOMISD	%XMM2,%XMM3

(194) 0x42ee03 JB	42e8f0

(194) 0x42ee09 SAL	$0x20,%RSI

(194) 0x42ee0d MOV	-0x90(%RBP),%RAX

(194) 0x42ee14 MOV	0x8(%RAX),%RAX

(194) 0x42ee18 MOV	0x40(%RDI),%RCX

(194) 0x42ee1c MOV	0x30(%RDI),%RDX

(194) 0x42ee20 IMUL	%R12,%RDX

(194) 0x42ee24 ADD	%R14,%RDX

(194) 0x42ee27 VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42ee2d VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42ee32 MOV	-0x88(%RBP),%RAX

(194) 0x42ee39 MOV	0x8(%RAX),%RAX

(194) 0x42ee3d MOV	0x10(%RDI),%RCX

(194) 0x42ee41 MOV	(%RDI),%RDX

(194) 0x42ee44 IMUL	%R12,%RDX

(194) 0x42ee48 MOV	%R14,-0x40(%RBP)

(194) 0x42ee4c ADD	%R14,%RDX

(194) 0x42ee4f VMOVSD	(%RAX,%R8,8),%XMM2

(194) 0x42ee55 VMOVSD	%XMM2,(%RCX,%RDX,8)

(194) 0x42ee5a MOV	-0x98(%RBP),%RAX

(194) 0x42ee61 MOV	0x8(%RAX),%RCX

(194) 0x42ee65 MOV	0xa8(%RDI),%RAX

(194) 0x42ee6c MOV	%RAX,-0x30(%RBP)

(194) 0x42ee70 MOV	0xb8(%RDI),%RAX

(194) 0x42ee77 MOV	%RAX,-0x58(%RBP)

(194) 0x42ee7b MOV	-0xa0(%RBP),%RAX

(194) 0x42ee82 MOV	0x8(%RAX),%R15

(194) 0x42ee86 MOV	0xe8(%RDI),%RAX

(194) 0x42ee8d MOV	%RAX,-0x50(%RBP)

(194) 0x42ee91 MOV	0xd8(%RDI),%RAX

(194) 0x42ee98 MOV	%RAX,-0x48(%RBP)

(194) 0x42ee9c MOV	$0x100000000,%RAX

(194) 0x42eea6 ADD	%RAX,%RSI

(194) 0x42eea9 SAR	$0x20,%RSI

(194) 0x42eead INC	%RSI

(194) 0x42eeb0 LEA	0x1(%R12),%RAX

(194) 0x42eeb5 CMP	%RAX,%RSI

(194) 0x42eeb8 CMOVLE	%RAX,%RSI

(194) 0x42eebc MOV	%R12,-0x38(%RBP)

(194) 0x42eec0 SUB	%R12,%RSI

(194) 0x42eec3 CMP	$0x2,%RSI

(194) 0x42eec7 JB	42ef9c

(194) 0x42eecd MOV	%RSI,%RDI

(194) 0x42eed0 SHR	$0x1,%RDI

(194) 0x42eed3 NEG	%RDI

(194) 0x42eed6 MOV	-0x48(%RBP),%R11

(194) 0x42eeda LEA	(,%R11,8),%R12

(194) 0x42eee2 MOV	%R12,%R13

(194) 0x42eee5 IMUL	%RAX,%R13

(194) 0x42eee9 MOV	-0x50(%RBP),%R9

(194) 0x42eeed ADD	%R9,%R13

(194) 0x42eef0 MOV	-0x40(%RBP),%RDX

(194) 0x42eef4 LEA	0x8(,%RDX,8),%RDX

(194) 0x42eefc SAL	$0x4,%R11

(194) 0x42ef00 IMUL	-0x38(%RBP),%R12

(194) 0x42ef05 ADD	%R9,%R12

(194) 0x42ef08 MOV	-0x30(%RBP),%R14

(194) 0x42ef0c LEA	(,%R14,8),%RBX

(194) 0x42ef14 IMUL	%RBX,%RAX

(194) 0x42ef18 MOV	-0x58(%RBP),%R9

(194) 0x42ef1c ADD	%R9,%RAX

(194) 0x42ef1f SAL	$0x4,%R14

(194) 0x42ef23 IMUL	-0x38(%RBP),%RBX

(194) 0x42ef28 ADD	%R9,%RBX

(194) 0x42ef2b MOV	%RDX,%R9

(194) 0x42ef2e XCHG	%AX,%AX

  (195) 0x42ef30 VMOVSD	(%RCX,%R8,8),%XMM2

  (195) 0x42ef36 VMOVSD	%XMM2,-0x8(%RBX,%RDX,1)

  (195) 0x42ef3c VMOVSD	(%R15,%R8,8),%XMM2

  (195) 0x42ef42 VMOVSD	%XMM2,-0x8(%R12,%R9,1)

  (195) 0x42ef49 VMOVSD	(%RCX,%R8,8),%XMM2

  (195) 0x42ef4f VMOVSD	%XMM2,(%RBX,%RDX,1)

  (195) 0x42ef54 VMOVSD	(%R15,%R8,8),%XMM2

  (195) 0x42ef5a VMOVSD	%XMM2,(%R12,%R9,1)

  (195) 0x42ef60 VMOVSD	(%RCX,%R8,8),%XMM2

  (195) 0x42ef66 VMOVSD	%XMM2,-0x8(%RAX,%RDX,1)

  (195) 0x42ef6c VMOVSD	(%R15,%R8,8),%XMM2

  (195) 0x42ef72 VMOVSD	%XMM2,-0x8(%R13,%R9,1)

  (195) 0x42ef79 VMOVSD	(%RCX,%R8,8),%XMM2

  (195) 0x42ef7f VMOVSD	%XMM2,(%RAX,%RDX,1)

  (195) 0x42ef84 VMOVSD	(%R15,%R8,8),%XMM2

  (195) 0x42ef8a VMOVSD	%XMM2,(%R13,%R9,1)

  (195) 0x42ef91 ADD	%R11,%R9

  (195) 0x42ef94 ADD	%R14,%RDX

  (195) 0x42ef97 INC	%RDI

  (195) 0x42ef9a JNE	42ef30

(194) 0x42ef9c MOV	%RSI,%RAX

(194) 0x42ef9f AND	$-0x2,%RAX

(194) 0x42efa3 CMP	%RSI,%RAX

(194) 0x42efa6 MOV	-0x80(%RBP),%R13

(194) 0x42efaa MOV	-0x68(%RBP),%RDI

(194) 0x42efae MOV	-0x78(%RBP),%R9

(194) 0x42efb2 MOV	-0x70(%RBP),%R11

(194) 0x42efb6 MOV	-0x5c(%RBP),%EBX

(194) 0x42efb9 MOV	-0x40(%RBP),%RSI

(194) 0x42efbd MOV	-0x38(%RBP),%R12

(194) 0x42efc1 JE	42e8f0

(194) 0x42efc7 MOV	%RAX,%RDX

(194) 0x42efca MOV	-0x30(%RBP),%R14

(194) 0x42efce IMUL	%R14,%RDX

(194) 0x42efd2 IMUL	%R12,%R14

(194) 0x42efd6 ADD	%RSI,%R14

(194) 0x42efd9 ADD	%RDX,%R14

(194) 0x42efdc VMOVSD	(%RCX,%R8,8),%XMM2

(194) 0x42efe2 MOV	%R12,%RDX

(194) 0x42efe5 MOV	-0x58(%RBP),%R12

(194) 0x42efe9 VMOVSD	%XMM2,(%R12,%R14,8)

(194) 0x42efef LEA	(%RCX,%R8,8),%RCX

(194) 0x42eff3 MOV	%RCX,-0x30(%RBP)

(194) 0x42eff7 MOV	-0x48(%RBP),%RCX

(194) 0x42effb IMUL	%RCX,%RDX

(194) 0x42efff ADD	%RSI,%RDX

(194) 0x42f002 IMUL	%RCX,%RAX

(194) 0x42f006 ADD	%RDX,%RAX

(194) 0x42f009 JMP	42e8c0

0x42f00e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	generate_chunk.cpp:85-128
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-128
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 1.83 cycles (8.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.33 to 1.32 cycles (12.42x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	97
nb uops	98
loop length	493
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	3.13	10.33	10.33	13.50	2.93	3.00	13.50	13.50	13.50	2.93	10.33
cycles	3.00	3.13	10.33	10.33	13.50	2.93	3.00	13.50	13.50	13.50	2.93	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	13.50
Overall L1	16.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

4% of peak load performance is reached (8.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.33 to 13.50 cycles (1.21x speedup).

ASM code

In the binary file, the address of the function is: 42e6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 42e840 <_Z14generate_chunkiR16global_variables.extracted+0x150>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xb8(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0xb0(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x47a0f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0xa4(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403200 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xb8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 42e880 <_Z14generate_chunkiR16global_variables.extracted+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x47a110,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa4(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EBX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%R14,%R8,4),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSD (%R12,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R15,%R8,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
SUB %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EBX,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42e8fc <_Z14generate_chunkiR16global_variables.extracted+0x20c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	generate_chunk.cpp:85-128
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-128
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 1.83 cycles (8.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	97
nb uops	98
loop length	493
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	3.13	10.33	10.33	13.50	2.93	3.00	13.50	13.50	13.50	2.93	10.33
cycles	3.00	3.13	10.33	10.33	13.50	2.93	3.00	13.50	13.50	13.50	2.93	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	13.50
Overall L1	16.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

4% of peak load performance is reached (8.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42e6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 42e840 <_Z14generate_chunkiR16global_variables.extracted+0x150>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xb8(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0xb0(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x47a0f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0xa4(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403200 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xb8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 42e880 <_Z14generate_chunkiR16global_variables.extracted+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x47a110,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa4(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xb8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EBX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%R14,%R8,4),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSD (%R12,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R15,%R8,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
SUB %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EBX,-0x5c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 42e8fc <_Z14generate_chunkiR16global_variables.extracted+0x20c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone .extracted]–	0.01	0.00
▼Loop 194 - generate_chunk.cpp:85-128 - exec–	0.01	0.01
○Loop 196 - generate_chunk.cpp:95-98 - exec	0.00	0.00
○Loop 195 - generate_chunk.cpp:109-112 - exec	0.00	0.00
○Loop 197 - generate_chunk.cpp:120-123 - exec	0.00	0.00

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code