OV - exec - Loop 729

	Loop Id: 729	Module: exec	Source: viscosity.cpp:39-64 [...]	Coverage: 2.61%

0x46d7b8 VCOMISD	%XMM13,%XMM7

0x46d7bd VANDPD	%XMM9,%XMM13,%XMM15

0x46d7c2 VMAXSD	%XMM8,%XMM15,%XMM4

0x46d7c7 VMOVAPD	%XMM10,%XMM0

0x46d7cb JA	46d998

0x46d7d1 VANDPD	%XMM9,%XMM1,%XMM1

0x46d7d6 VMAXSD	%XMM8,%XMM1,%XMM2

0x46d7db MOV	-0x50(%RBP),%R14    [10]

0x46d7df MOV	0x10(%R11),%RBX    [9]

0x46d7e3 VMULSD	%XMM0,%XMM2,%XMM15

0x46d7e7 IMUL	(%R11),%R14    [9]

0x46d7eb ADD	%RAX,%R14

0x46d7ee VMULSD	%XMM15,%XMM15,%XMM13

0x46d7f3 VFMADD231SD	%XMM4,%XMM4,%XMM13

0x46d7f8 VSQRTSD	%XMM13,%XMM13,%XMM13

0x46d7fd VMULSD	%XMM5,%XMM13,%XMM5

0x46d801 VMULSD	%XMM14,%XMM13,%XMM14

0x46d806 VMOVSD	(%RBX,%R14,8),%XMM13    [6]

0x46d80c VDIVSD	%XMM15,%XMM5,%XMM0

0x46d811 VADDSD	%XMM13,%XMM13,%XMM5

0x46d816 VDIVSD	%XMM4,%XMM14,%XMM4

0x46d81a VANDPD	%XMM9,%XMM0,%XMM1

0x46d81f VANDPD	%XMM9,%XMM4,%XMM2

0x46d824 VMINSD	%XMM2,%XMM1,%XMM15

0x46d828 VMULSD	%XMM3,%XMM15,%XMM3

0x46d82c VMULSD	%XMM3,%XMM3,%XMM0

0x46d830 VMULSD	%XMM0,%XMM5,%XMM1

0x46d834 MOV	-0x40(%RBP),%R14    [10]

0x46d838 VMOVSD	%XMM1,(%R13,%RAX,8)    [12]

0x46d83f MOV	%RDX,%RAX

0x46d842 CMP	%R14,%RDX

0x46d845 JE	46d9c0

0x46d84b INC	%RDX

0x46d84e VMOVSD	0x8(%R8,%RAX,8),%XMM0    [1]

0x46d855 VMOVSD	(%R9,%RAX,8),%XMM3    [2]

0x46d85b VMOVSD	(%R8,%RAX,8),%XMM2    [1]

0x46d861 VMOVSD	0x8(%R9,%RAX,8),%XMM15    [2]

0x46d868 VADDSD	%XMM3,%XMM2,%XMM4

0x46d86c VADDSD	%XMM15,%XMM0,%XMM1

0x46d871 VMOVSD	0x8(%RDI,%RAX,8),%XMM14    [4]

0x46d877 VMOVSD	0x8(%RSI,%RAX,8),%XMM5    [5]

0x46d87d VMOVSD	(%RDI,%RAX,8),%XMM17    [4]

0x46d884 VMOVSD	(%RSI,%RAX,8),%XMM13    [5]

0x46d889 VADDSD	%XMM0,%XMM2,%XMM16

0x46d88f VADDSD	%XMM15,%XMM3,%XMM15

0x46d894 VSUBSD	%XMM4,%XMM1,%XMM0

0x46d898 VADDSD	%XMM14,%XMM5,%XMM2

0x46d89d VADDSD	%XMM13,%XMM5,%XMM4

0x46d8a2 VADDSD	%XMM17,%XMM13,%XMM13

0x46d8a8 VADDSD	%XMM17,%XMM14,%XMM1

0x46d8ae VSUBSD	%XMM15,%XMM16,%XMM19

0x46d8b4 VSUBSD	%XMM13,%XMM2,%XMM2

0x46d8b9 VSUBSD	%XMM4,%XMM1,%XMM4

0x46d8bd VMULSD	%XMM6,%XMM19,%XMM20

0x46d8c3 VMULSD	%XMM6,%XMM2,%XMM1

0x46d8c7 MOV	-0x38(%RBP),%R14    [10]

0x46d8cb VMOVSD	(%R10,%RAX,8),%XMM14    [8]

0x46d8d1 VMOVSD	(%R14),%XMM5    [13]

0x46d8d6 VMOVSD	0x8(%RCX,%RAX,8),%XMM2    [3]

0x46d8dc VDIVSD	%XMM14,%XMM1,%XMM13

0x46d8e1 VADDSD	0x8(%R10,%RAX,8),%XMM14,%XMM1    [8]

0x46d8e8 VMOVSD	(%R12,%RAX,8),%XMM15    [11]

0x46d8ee MOV	-0x48(%RBP),%RBX    [10]

0x46d8f2 VMULSD	%XMM4,%XMM5,%XMM18

0x46d8f8 VMULSD	%XMM6,%XMM4,%XMM4

0x46d8fc VFMADD231SD	%XMM0,%XMM14,%XMM18

0x46d902 VMULSD	%XMM6,%XMM0,%XMM0

0x46d906 VCOMISD	%XMM7,%XMM18

0x46d90c VDIVSD	%XMM5,%XMM20,%XMM21

0x46d912 VDIVSD	%XMM14,%XMM0,%XMM0

0x46d917 VADDSD	%XMM21,%XMM13,%XMM3

0x46d91d VSUBSD	-0x8(%RCX,%RAX,8),%XMM2,%XMM13    [3]

0x46d923 VADDSD	(%R15),%XMM5,%XMM2    [15]

0x46d928 VDIVSD	%XMM1,%XMM13,%XMM13

0x46d92c VSUBSD	(%RBX,%RAX,8),%XMM15,%XMM1    [7]

0x46d931 VDIVSD	%XMM2,%XMM1,%XMM1

0x46d935 VMULSD	%XMM13,%XMM13,%XMM15

0x46d93a VDIVSD	%XMM5,%XMM4,%XMM2

0x46d93e VMULSD	%XMM1,%XMM1,%XMM22

0x46d944 VADDSD	%XMM15,%XMM22,%XMM23

0x46d94a VMAXSD	%XMM8,%XMM23,%XMM24

0x46d950 VMULSD	%XMM22,%XMM2,%XMM4

0x46d956 VMULSD	%XMM13,%XMM1,%XMM2

0x46d95b VFMADD132SD	%XMM15,%XMM4,%XMM0

0x46d960 VFMADD132SD	%XMM3,%XMM0,%XMM2

0x46d965 VDIVSD	%XMM24,%XMM2,%XMM3

0x46d96b JAE	46d977

0x46d96d VCOMISD	%XMM7,%XMM3

0x46d971 JBE	46d7b8

0x46d977 VXORPD	%XMM1,%XMM1,%XMM1

0x46d97b JMP	46d834

0x46d998 VCOMISD	%XMM7,%XMM4

0x46d99c VXORPD	%XMM12,%XMM4,%XMM13

0x46d9a1 VMOVAPD	%XMM13,%XMM4

0x46d9a5 JBE	46d9ea

0x46d9a7 VMOVAPD	%XMM11,%XMM0

0x46d9ab JMP	46d7d1

0x46d9ea VMOVSD	0x1ae6(%RIP),%XMM0    [14]

0x46d9f2 JMP	46d7d1

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 39 - 64

--------------------------------------------------------------------------------

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○97.68	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.32	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.91
Bottlenecks	P0,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	viscosity.cpp:39-64,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.50
CQA cycles if no scalar integer	40.50
CQA cycles if FP arith vectorized	20.25
CQA cycles if fully vectorized	20.25
Front-end cycles	17.00
P0 cycles	20.83
P1 cycles	21.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	21.17
P6 cycles	5.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	8.00
DIV/SQRT cycles	40.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	99.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	1.31
Nb FLOP add-sub	19.00
Nb FLOP mul	16.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.94
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.98
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.87
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.91
Bottlenecks	P0,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	viscosity.cpp:39-64,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.50
CQA cycles if no scalar integer	40.50
CQA cycles if FP arith vectorized	20.25
CQA cycles if fully vectorized	20.25
Front-end cycles	17.00
P0 cycles	20.83
P1 cycles	21.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	21.17
P6 cycles	5.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	8.00
DIV/SQRT cycles	40.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	99.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	1.31
Nb FLOP add-sub	19.00
Nb FLOP mul	16.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.94
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.98
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.87
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	viscosity.cpp:39-64
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39-64
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 40.50 to 20.25 cycles (2.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 40.50 to 21.17 cycles (1.91x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.50 to 24.50 cycles (1.65x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

57 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 53 FP arithmetical operations:

23: addition or subtraction (4 inside FMA instructions)
20: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	99
loop length	493
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	20.83	21.00	8.00	8.00	0.50	21.17	5.00	0.50	0.50	0.50	2.00	8.00
cycles	20.83	21.00	8.00	8.00	0.50	21.17	5.00	0.50	0.50	0.50	2.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

40.50

Cycles summary

Front-end	17.00
Dispatch	21.17
DIV/SQRT	40.50
Overall L1	40.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	52%

INT+FP

all	10%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.50 cycles. At this rate:

2% of peak load performance is reached (4.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46d84e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCOMISD %XMM13,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VANDPD %XMM9,%XMM13,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM8,%XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JA 46d998 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x428>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM9,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM8,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R11),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM0,%XMM2,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL (%R11),%R14	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM15,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM13,%XMM13,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM5,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM13,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%RBX,%R14,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM15,%XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM4,%XMM14,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM9,%XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM9,%XMM4,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM1,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM15,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM5,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM1,(%R13,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46d9c0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x450>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%R8,%RAX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%R9,%RAX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM3,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x8(%RDI,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM0,%XMM2,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM3,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM14,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM5,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM14,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM16,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM19,%XMM20	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R10,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R14),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM14,%XMM1,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD 0x8(%R10,%RAX,8),%XMM14,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM4,%XMM5,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM0,%XMM14,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM7,%XMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVSD %XMM5,%XMM20,%XMM21	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VDIVSD %XMM14,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM21,%XMM13,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD -0x8(%RCX,%RAX,8),%XMM2,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD (%R15),%XMM5,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VDIVSD %XMM1,%XMM13,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSUBSD (%RBX,%RAX,8),%XMM15,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM1,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM5,%XMM4,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM22	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM22,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM8,%XMM23,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM22,%XMM2,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM13,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM15,%XMM4,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM3,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM24,%XMM2,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
JAE 46d977 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x407>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM7,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46d7b8 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 46d834 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VCOMISD %XMM7,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VXORPD %XMM12,%XMM4,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVAPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JBE 46d9ea <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x47a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 46d7d1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x261>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x1ae6(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46d7d1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x261>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	viscosity.cpp:39-64
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39-64
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.50 to 24.50 cycles (1.65x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

57 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 53 FP arithmetical operations:

23: addition or subtraction (4 inside FMA instructions)
20: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	99
loop length	493
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	20.83	21.00	8.00	8.00	0.50	21.17	5.00	0.50	0.50	0.50	2.00	8.00
cycles	20.83	21.00	8.00	8.00	0.50	21.17	5.00	0.50	0.50	0.50	2.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

40.50

Cycles summary

Front-end	17.00
Dispatch	21.17
DIV/SQRT	40.50
Overall L1	40.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	52%

INT+FP

all	10%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.50 cycles. At this rate:

2% of peak load performance is reached (4.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46d84e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCOMISD %XMM13,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VANDPD %XMM9,%XMM13,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM8,%XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JA 46d998 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x428>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM9,%XMM1,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM8,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R11),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM0,%XMM2,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL (%R11),%R14	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM15,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM13,%XMM13,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM5,%XMM13,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM13,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%RBX,%R14,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM15,%XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM4,%XMM14,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM9,%XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VANDPD %XMM9,%XMM4,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM2,%XMM1,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM15,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM5,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM1,(%R13,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46d9c0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x450>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%R8,%RAX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%R9,%RAX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM3,%XMM2,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x8(%RDI,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM0,%XMM2,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM3,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM14,%XMM5,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM5,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM17,%XMM14,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM16,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM19,%XMM20	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R10,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R14),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD %XMM14,%XMM1,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD 0x8(%R10,%RAX,8),%XMM14,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM4,%XMM5,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM4,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM0,%XMM14,%XMM18	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM7,%XMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VDIVSD %XMM5,%XMM20,%XMM21	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VDIVSD %XMM14,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VADDSD %XMM21,%XMM13,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD -0x8(%RCX,%RAX,8),%XMM2,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD (%R15),%XMM5,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VDIVSD %XMM1,%XMM13,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSUBSD (%RBX,%RAX,8),%XMM15,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM1,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM5,%XMM4,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM22	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM22,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM8,%XMM23,%XMM24	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM22,%XMM2,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM13,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM15,%XMM4,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM3,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM24,%XMM2,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
JAE 46d977 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x407>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM7,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46d7b8 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 46d834 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VCOMISD %XMM7,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VXORPD %XMM12,%XMM4,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVAPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JBE 46d9ea <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x47a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPD %XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 46d7d1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x261>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x1ae6(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46d7d1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x261>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code