OV - exec - Loop 338

	Loop Id: 338	Module: exec	Source: PdV.cpp:51-63	Coverage: 5.12%

0x447ff0 VMOVUPD	(%R14,%RAX,1),%ZMM8    [3]

0x447ff7 MOV	0x188(%RSP),%RCX    [18]

0x447fff VMOVUPD	(%R11,%RAX,1),%ZMM3    [15]

0x448006 VADDPD	(%RCX,%RAX,1),%ZMM8,%ZMM10    [12]

0x44800d MOV	0x198(%RSP),%RCX    [18]

0x448015 VMOVUPD	(%RBX,%RAX,1),%ZMM0    [20]

0x44801c VADDPD	(%RCX,%RAX,1),%ZMM3,%ZMM9    [11]

0x448023 VMOVUPD	(%R12,%RAX,1),%ZMM14    [1]

0x44802a MOV	0x190(%RSP),%RCX    [18]

0x448032 VADDPD	%ZMM0,%ZMM0,%ZMM11

0x448038 VADDPD	(%RCX,%RAX,1),%ZMM14,%ZMM8    [10]

0x44803f VMOVUPD	(%R9,%RAX,1),%ZMM3    [17]

0x448046 VMOVUPD	(%R10,%RAX,1),%ZMM0    [14]

0x44804d MOV	0x1a0(%RSP),%RCX    [18]

0x448055 VMULPD	%ZMM11,%ZMM9,%ZMM13

0x44805b VADDPD	(%RCX,%RAX,1),%ZMM3,%ZMM9    [9]

0x448062 VADDPD	%ZMM0,%ZMM0,%ZMM11

0x448068 VMOVUPD	(%R13,%RAX,1),%ZMM12    [2]

0x448070 VMOVUPD	(%R15,%RAX,1),%ZMM14    [4]

0x448077 VADDPD	%ZMM12,%ZMM12,%ZMM15

0x44807d VMULPD	%ZMM11,%ZMM9,%ZMM12

0x448083 VMOVUPD	(%RDI,%RAX,1),%ZMM0    [13]

0x44808a MOV	0x1a8(%RSP),%RCX    [18]

0x448092 VMOVUPD	(%R8,%RAX,1),%ZMM3    [16]

0x448099 VADDPD	(%RCX,%RAX,1),%ZMM0,%ZMM11    [8]

0x4480a0 VFMADD132PD	%ZMM8,%ZMM12,%ZMM15

0x4480a6 VADDPD	%ZMM14,%ZMM14,%ZMM8

0x4480ac VDIVPD	(%RDX,%RAX,1),%ZMM11,%ZMM12    [5]

0x4480b3 VDIVPD	%ZMM3,%ZMM4,%ZMM14

0x4480b9 VFMADD132PD	%ZMM10,%ZMM13,%ZMM8

0x4480bf MOV	0x1b0(%RSP),%RCX    [18]

0x4480c7 VSUBPD	%ZMM8,%ZMM15,%ZMM10

0x4480cd VMULPD	%ZMM14,%ZMM12,%ZMM8

0x4480d3 VMULPD	%ZMM5,%ZMM10,%ZMM9

0x4480d9 VADDPD	%ZMM9,%ZMM3,%ZMM13

0x4480df VFNMADD213PD	(%RCX,%RAX,1),%ZMM8,%ZMM9    [7]

0x4480e6 MOV	0x1b8(%RSP),%RCX    [18]

0x4480ee VDIVPD	%ZMM13,%ZMM3,%ZMM15

0x4480f4 VMOVUPD	%ZMM9,(%RCX,%RAX,1)    [6]

0x4480fb VMULPD	(%RDX,%RAX,1),%ZMM15,%ZMM10    [5]

0x448102 MOV	0x180(%RSP),%RCX    [18]

0x44810a VMOVUPD	%ZMM10,(%RSI,%RAX,1)    [19]

0x448111 ADD	$0x40,%RAX

0x448115 CMP	%RCX,%RAX

0x448118 JNE	447ff0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 51 - 63

--------------------------------------------------------------------------------

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

Coverage (%)	Name	Source Location	Module
○97.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P0,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	PdV.cpp:51-63
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	48.00
Front-end cycles	9.67
P0 cycles	14.00
P1 cycles	9.50
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	1.00
P5 cycles	14.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	51.00
Nb loads	26.00
Nb stores	2.00
Nb stack references	8.00
FLOP/cycle	4.17
Nb FLOP add-sub	88.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	1216.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	19.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.43
Bottlenecks	P0,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	PdV.cpp:51-63
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	48.00
CQA cycles if no scalar integer	48.00
CQA cycles if FP arith vectorized	48.00
CQA cycles if fully vectorized	48.00
Front-end cycles	9.67
P0 cycles	14.00
P1 cycles	9.50
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	1.00
P5 cycles	14.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	51.00
Nb loads	26.00
Nb stores	2.00
Nb stack references	8.00
FLOP/cycle	4.17
Nb FLOP add-sub	88.00
Nb FLOP mul	40.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	1216.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	19.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	PdV.cpp:51-63
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:51-63.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 14.00 cycles (3.43x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 11.00 cycles (4.36x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:61
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:59

Type of elements and instruction set

22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1216 bytes (152 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	51
loop length	302
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	8
ADD-SUB / MUL ratio	2.20

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	0.00	8.67	8.67	1.00	14.00	1.00	1.00	1.00	1.00	0.00	8.67
cycles	14.00	9.50	8.67	8.67	1.00	14.00	1.00	1.00	1.00	1.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	14.00
DIV/SQRT	48.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

13% of peak load performance is reached (25.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 447ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R14,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x188(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R11,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x198(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM3,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x190(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM0,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM14,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD %ZMM11,%ZMM9,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM3,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R15,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x1a8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM0,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD %ZMM8,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD (%RDX,%RAX,1),%ZMM11,%ZMM12	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VDIVPD %ZMM3,%ZMM4,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD132PD %ZMM10,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x1b0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD %ZMM8,%ZMM15,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM12,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM10,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM3,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RCX,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x1b8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVPD %ZMM13,%ZMM3,%ZMM15	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM9,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM15,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x180(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM10,(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 447ff0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	PdV.cpp:51-63
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 11.00 cycles (4.36x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:61
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:59

Type of elements and instruction set

22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
64: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1216 bytes (152 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	51
loop length	302
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	8
ADD-SUB / MUL ratio	2.20

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	0.00	8.67	8.67	1.00	14.00	1.00	1.00	1.00	1.00	0.00	8.67
cycles	14.00	9.50	8.67	8.67	1.00	14.00	1.00	1.00	1.00	1.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.67
Dispatch	14.00
DIV/SQRT	48.00
Data deps.	1.00
Overall L1	48.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

13% of peak load performance is reached (25.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 447ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R14,%RAX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x188(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R11,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
MOV 0x198(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%RBX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM3,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x190(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDPD %ZMM0,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM14,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPD %ZMM11,%ZMM9,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM3,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R15,%RAX,1),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM9,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x1a8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPD (%RCX,%RAX,1),%ZMM0,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VFMADD132PD %ZMM8,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD (%RDX,%RAX,1),%ZMM11,%ZMM12	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VDIVPD %ZMM3,%ZMM4,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD132PD %ZMM10,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x1b0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBPD %ZMM8,%ZMM15,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM12,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM10,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM3,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RCX,%RAX,1),%ZMM8,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x1b8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVPD %ZMM13,%ZMM3,%ZMM15	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVUPD %ZMM9,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD (%RDX,%RAX,1),%ZMM15,%ZMM10	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
MOV 0x180(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD %ZMM10,(%RSI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 447ff0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code