OV - exec - Loop 317

	Loop Id: 317	Module: exec	Source: pack_kernel.cpp:121-124 [...]	Coverage: 0.02%

0x44419e MOV	0x28(%RSP),%R9

0x4441a3 LEA	(,%R8,8),%RSI

0x4441ab IMUL	%R11,%R9

0x4441af CMPL	$0x2,0x3c(%RSP)

0x4441b4 JBE	444460

0x4441ba MOV	0x1c(%RSP),%EDI

0x4441be LEA	(%RDI,%R8,1),%ECX

  (318) 0x4441c2 MOV	0x10(%RSP),%R15

  (318) 0x4441c7 MOV	0x8(%RSP),%RAX

  (318) 0x4441cc LEA	0x2(%R9,%R15,1),%RDI

  (318) 0x4441d1 MOV	0x30(%RSP),%R15

  (318) 0x4441d6 LEA	(,%R8,8),%RSI

  (318) 0x4441de SAL	$0x3,%RDI

  (318) 0x4441e2 LEA	-0x8(%RDI,%RAX,1),%RDX

  (318) 0x4441e7 ADD	%RSI,%R15

  (318) 0x4441ea ADD	%R10,%RDX

  (318) 0x4441ed ADD	%R12,%R15

  (318) 0x4441f0 LEA	(%R12,%RSI,1),%R13

  (318) 0x4441f4 CMP	%R15,%RDX

  (318) 0x4441f7 JAE	444206

  (318) 0x4441f9 LEA	(%R10,%RDI,1),%RAX

  (318) 0x4441fd CMP	%RAX,%R13

  (318) 0x444200 JB	444460

  (318) 0x444206 CMPL	$0x6,0x3c(%RSP)

  (318) 0x44420b JBE	4445db

  (318) 0x444211 LEA	-0x40(%R14),%RSI

  (318) 0x444215 LEA	-0x40(%R10,%RDI,1),%RAX

  (318) 0x44421a SHR	$0x6,%RSI

  (318) 0x44421e MOV	%RAX,%R15

  (318) 0x444221 INC	%RSI

  (318) 0x444224 MOV	%R13,%RDX

  (318) 0x444227 SUB	%R14,%R15

  (318) 0x44422a AND	$0x7,%ESI

  (318) 0x44422d JE	4442fa

  (318) 0x444233 CMP	$0x1,%RSI

  (318) 0x444237 JE	4442dd

  (318) 0x44423d CMP	$0x2,%RSI

  (318) 0x444241 JE	4442c8

  (318) 0x444247 CMP	$0x3,%RSI

  (318) 0x44424b JE	4442b3

  (318) 0x44424d CMP	$0x4,%RSI

  (318) 0x444251 JE	44429e

  (318) 0x444253 CMP	$0x5,%RSI

  (318) 0x444257 JE	444289

  (318) 0x444259 CMP	$0x6,%RSI

  (318) 0x44425d JE	444274

  (318) 0x44425f VPERMPD	(%RAX),%ZMM0,%ZMM1

  (318) 0x444265 ADD	$0x40,%RDX

  (318) 0x444269 VMOVUPD	%ZMM1,(%R13)

  (318) 0x444270 SUB	$0x40,%RAX

  (318) 0x444274 VPERMPD	(%RAX),%ZMM0,%ZMM2

  (318) 0x44427a ADD	$0x40,%RDX

  (318) 0x44427e VMOVUPD	%ZMM2,-0x40(%RDX)

  (318) 0x444285 SUB	$0x40,%RAX

  (318) 0x444289 VPERMPD	(%RAX),%ZMM0,%ZMM3

  (318) 0x44428f ADD	$0x40,%RDX

  (318) 0x444293 VMOVUPD	%ZMM3,-0x40(%RDX)

  (318) 0x44429a SUB	$0x40,%RAX

  (318) 0x44429e VPERMPD	(%RAX),%ZMM0,%ZMM4

  (318) 0x4442a4 ADD	$0x40,%RDX

  (318) 0x4442a8 VMOVUPD	%ZMM4,-0x40(%RDX)

  (318) 0x4442af SUB	$0x40,%RAX

  (318) 0x4442b3 VPERMPD	(%RAX),%ZMM0,%ZMM5

  (318) 0x4442b9 ADD	$0x40,%RDX

  (318) 0x4442bd VMOVUPD	%ZMM5,-0x40(%RDX)

  (318) 0x4442c4 SUB	$0x40,%RAX

  (318) 0x4442c8 VPERMPD	(%RAX),%ZMM0,%ZMM6

  (318) 0x4442ce ADD	$0x40,%RDX

  (318) 0x4442d2 VMOVUPD	%ZMM6,-0x40(%RDX)

  (318) 0x4442d9 SUB	$0x40,%RAX

  (318) 0x4442dd VPERMPD	(%RAX),%ZMM0,%ZMM7

  (318) 0x4442e3 SUB	$0x40,%RAX

  (318) 0x4442e7 VMOVUPD	%ZMM7,(%RDX)

  (318) 0x4442ed ADD	$0x40,%RDX

  (318) 0x4442f1 CMP	%RAX,%R15

  (318) 0x4442f4 JE	44437a

    (319) 0x4442fa VPERMPD	(%RAX),%ZMM0,%ZMM8

    (319) 0x444300 SUB	$0x200,%RAX

    (319) 0x444306 VMOVUPD	%ZMM8,(%RDX)

    (319) 0x44430c VPERMPD	0x1c0(%RAX),%ZMM0,%ZMM9

    (319) 0x444313 ADD	$0x200,%RDX

    (319) 0x44431a VMOVUPD	%ZMM9,-0x1c0(%RDX)

    (319) 0x444321 VPERMPD	0x180(%RAX),%ZMM0,%ZMM10

    (319) 0x444328 VMOVUPD	%ZMM10,-0x180(%RDX)

    (319) 0x44432f VPERMPD	0x140(%RAX),%ZMM0,%ZMM11

    (319) 0x444336 VMOVUPD	%ZMM11,-0x140(%RDX)

    (319) 0x44433d VPERMPD	0x100(%RAX),%ZMM0,%ZMM12

    (319) 0x444344 VMOVUPD	%ZMM12,-0x100(%RDX)

    (319) 0x44434b VPERMPD	0xc0(%RAX),%ZMM0,%ZMM13

    (319) 0x444352 VMOVUPD	%ZMM13,-0xc0(%RDX)

    (319) 0x444359 VPERMPD	0x80(%RAX),%ZMM0,%ZMM14

    (319) 0x444360 VMOVUPD	%ZMM14,-0x80(%RDX)

    (319) 0x444367 VPERMPD	0x40(%RAX),%ZMM0,%ZMM15

    (319) 0x44436e VMOVUPD	%ZMM15,-0x40(%RDX)

    (319) 0x444375 CMP	%RAX,%R15

    (319) 0x444378 JNE	4442fa

  (318) 0x44437a MOV	%EBX,%EAX

  (318) 0x44437c AND	$-0x8,%EAX

  (318) 0x44437f MOV	%EAX,%EDX

  (318) 0x444381 CMP	%EAX,%EBX

  (318) 0x444383 JE	444430

  (318) 0x444389 MOV	%EBX,%ESI

  (318) 0x44438b SUB	%EAX,%ESI

  (318) 0x44438d LEA	-0x1(%RSI),%R13D

  (318) 0x444391 CMP	$0x2,%R13D

  (318) 0x444395 JBE	4443bd

  (318) 0x444397 MOV	%RDX,%R15

  (318) 0x44439a ADD	%R10,%RDI

  (318) 0x44439d NEG	%R15

  (318) 0x4443a0 VPERMPD	$0x1b,-0x20(%RDI,%R15,8),%YMM1

  (318) 0x4443a8 MOV	%ESI,%EDI

  (318) 0x4443aa AND	$-0x4,%EDI

  (318) 0x4443ad ADD	%R8,%RDX

  (318) 0x4443b0 ADD	%EDI,%EAX

  (318) 0x4443b2 AND	$0x3,%ESI

  (318) 0x4443b5 VMOVUPD	%YMM1,(%R12,%RDX,8)

  (318) 0x4443bb JE	444430

  (318) 0x4443bd MOV	0x18(%RSP),%R13D

  (318) 0x4443c2 MOV	0x4(%RSP),%R15D

  (318) 0x4443c7 MOV	%R13D,%EDX

  (318) 0x4443ca SUB	%EAX,%EDX

  (318) 0x4443cc MOVSXD	%EDX,%RSI

  (318) 0x4443cf ADD	%R9,%RSI

  (318) 0x4443d2 LEA	(%R15,%RAX,1),%EDI

  (318) 0x4443d6 ADD	%ECX,%EDI

  (318) 0x4443d8 VMOVSD	(%R10,%RSI,8),%XMM2

  (318) 0x4443de MOVSXD	%EDI,%RDX

  (318) 0x4443e1 LEA	0x1(%RAX),%EDI

  (318) 0x4443e4 VMOVSD	%XMM2,(%R12,%RDX,8)

  (318) 0x4443ea CMP	%EDI,%EBX

  (318) 0x4443ec JLE	444430

  (318) 0x4443ee MOV	(%RSP),%ESI

  (318) 0x4443f1 ADD	%R15D,%EDI

  (318) 0x4443f4 SUB	%EAX,%ESI

  (318) 0x4443f6 MOVSXD	%ESI,%RDX

  (318) 0x4443f9 ADD	%R9,%RDX

  (318) 0x4443fc VMOVSD	(%R10,%RDX,8),%XMM3

  (318) 0x444402 ADD	%ECX,%EDI

  (318) 0x444404 MOVSXD	%EDI,%RDI

  (318) 0x444407 ADD	$0x2,%EAX

  (318) 0x44440a VMOVSD	%XMM3,(%R12,%RDI,8)

  (318) 0x444410 CMP	%EAX,%EBX

  (318) 0x444412 JLE	444430

  (318) 0x444414 SUB	%EAX,%R13D

  (318) 0x444417 MOVSXD	%R13D,%R13

  (318) 0x44441a ADD	%R9,%R13

  (318) 0x44441d ADD	%R15D,%EAX

  (318) 0x444420 VMOVSD	(%R10,%R13,8),%XMM4

  (318) 0x444426 ADD	%ECX,%EAX

  (318) 0x444428 CLTQ

  (318) 0x44442a VMOVSD	%XMM4,(%R12,%RAX,8)

  (318) 0x444430 MOV	0x20(%RSP),%R9

  (318) 0x444435 INC	%R11

  (318) 0x444438 ADD	%R9,%R8

  (318) 0x44443b CMP	%R11D,0x38(%RSP)

  (318) 0x444440 JLE	4445c0

  (318) 0x444446 MOV	0x1c(%RSP),%ECX

  (318) 0x44444a MOV	0x28(%RSP),%R9

  (318) 0x44444f LEA	(%RCX,%R8,1),%ECX

  (318) 0x444453 IMUL	%R11,%R9

  (318) 0x444457 JMP	4441c2

0x444460 MOV	0x30(%RSP),%RDI

0x444465 LEA	(%R12,%RSI,1),%R15

0x444469 ADD	%R12,%RDI

0x44446c ADD	%RDI,%RSI

0x44446f MOV	%RSI,%R13

0x444472 SUB	%R15,%R13

0x444475 MOVSXD	0x18(%RSP),%RAX

0x44447a SUB	$0x8,%R13

0x44447e SHR	$0x3,%R13

0x444482 ADD	%R9,%RAX

0x444485 INC	%R13

0x444488 LEA	(%R10,%RAX,8),%RDX

0x44448c AND	$0x7,%R13D

0x444490 JE	444541

0x444496 CMP	$0x1,%R13

0x44449a JE	44452a

0x4444a0 CMP	$0x2,%R13

0x4444a4 JE	444518

0x4444a6 CMP	$0x3,%R13

0x4444aa JE	444506

0x4444ac CMP	$0x4,%R13

0x4444b0 JE	4444f4

0x4444b2 CMP	$0x5,%R13

0x4444b6 JE	4444e2

0x4444b8 CMP	$0x6,%R13

0x4444bc JE	4444d0

0x4444be VMOVSD	(%RDX),%XMM5

0x4444c2 ADD	$0x8,%R15

0x4444c6 VMOVSD	%XMM5,-0x8(%R15)

0x4444cc SUB	$0x8,%RDX

0x4444d0 VMOVSD	(%RDX),%XMM6

0x4444d4 ADD	$0x8,%R15

0x4444d8 VMOVSD	%XMM6,-0x8(%R15)

0x4444de SUB	$0x8,%RDX

0x4444e2 VMOVSD	(%RDX),%XMM7

0x4444e6 ADD	$0x8,%R15

0x4444ea VMOVSD	%XMM7,-0x8(%R15)

0x4444f0 SUB	$0x8,%RDX

0x4444f4 VMOVSD	(%RDX),%XMM8

0x4444f8 ADD	$0x8,%R15

0x4444fc VMOVSD	%XMM8,-0x8(%R15)

0x444502 SUB	$0x8,%RDX

0x444506 VMOVSD	(%RDX),%XMM9

0x44450a ADD	$0x8,%R15

0x44450e VMOVSD	%XMM9,-0x8(%R15)

0x444514 SUB	$0x8,%RDX

0x444518 VMOVSD	(%RDX),%XMM10

0x44451c ADD	$0x8,%R15

0x444520 VMOVSD	%XMM10,-0x8(%R15)

0x444526 SUB	$0x8,%RDX

0x44452a VMOVSD	(%RDX),%XMM11

0x44452e ADD	$0x8,%R15

0x444532 VMOVSD	%XMM11,-0x8(%R15)

0x444538 SUB	$0x8,%RDX

0x44453c CMP	%R15,%RSI

0x44453f JE	4445a5

  (316) 0x444541 VMOVSD	(%RDX),%XMM12

  (316) 0x444545 ADD	$0x40,%R15

  (316) 0x444549 VMOVSD	%XMM12,-0x40(%R15)

  (316) 0x44454f VMOVSD	-0x8(%RDX),%XMM13

  (316) 0x444554 SUB	$0x40,%RDX

  (316) 0x444558 VMOVSD	%XMM13,-0x38(%R15)

  (316) 0x44455e VMOVSD	0x30(%RDX),%XMM14

  (316) 0x444563 VMOVSD	%XMM14,-0x30(%R15)

  (316) 0x444569 VMOVSD	0x28(%RDX),%XMM15

  (316) 0x44456e VMOVSD	%XMM15,-0x28(%R15)

  (316) 0x444574 VMOVSD	0x20(%RDX),%XMM1

  (316) 0x444579 VMOVSD	%XMM1,-0x20(%R15)

  (316) 0x44457f VMOVSD	0x18(%RDX),%XMM2

  (316) 0x444584 VMOVSD	%XMM2,-0x18(%R15)

  (316) 0x44458a VMOVSD	0x10(%RDX),%XMM3

  (316) 0x44458f VMOVSD	%XMM3,-0x10(%R15)

  (316) 0x444595 VMOVSD	0x8(%RDX),%XMM4

  (316) 0x44459a VMOVSD	%XMM4,-0x8(%R15)

  (316) 0x4445a0 CMP	%R15,%RSI

  (316) 0x4445a3 JNE	444541

0x4445a5 MOV	0x20(%RSP),%RSI

0x4445aa INC	%R11

0x4445ad ADD	%RSI,%R8

0x4445b0 CMP	%R11D,0x38(%RSP)

0x4445b5 JG	44419e

  (318) 0x4445db MOV	%EBX,%ESI

  (318) 0x4445dd XOR	%EDX,%EDX

  (318) 0x4445df XOR	%EAX,%EAX

  (318) 0x4445e1 JMP	444397

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp: 121 - 124

--------------------------------------------------------------------------------

121:   for (int k = (y_min - depth + 1); k < (y_max + y_inc + depth + 2); k++) {

122:     for (int j = 0; j < depth; ++j) {

123:       int index = buffer_offset + j + k * depth;

124:       right_snd[index] = field(x_max + 1 - j, k);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○98.25	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.75	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	2.23
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.03
Bottlenecks	micro-operation queue,
Function	clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]
Source	pack_kernel.cpp:122-124,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.98
Front-end cycles	11.17
P0 cycles	5.50
P1 cycles	5.40
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	3.50
P5 cycles	5.40
P6 cycles	5.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.20
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	67.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.61
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.08
Vector-efficiency ratio load	11.81
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.36

Metric	Value
CQA speedup if no scalar integer	2.23
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.03
Bottlenecks	micro-operation queue,
Function	clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]
Source	pack_kernel.cpp:122-124,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	11.17
CQA cycles if fully vectorized	0.98
Front-end cycles	11.17
P0 cycles	5.50
P1 cycles	5.40
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	3.50
P5 cycles	5.40
P6 cycles	5.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.20
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	67.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.61
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.08
Vector-efficiency ratio load	11.81
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.36

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]
Source file and lines	pack_kernel.cpp:121-124
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121-124
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 278 paths individually, rerun with max-paths=278
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 278 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 5.00 cycles (2.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 0.98 cycles (11.45x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	68
nb uops	67
loop length	283
used x86 registers	13
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.40	4.67	4.67	3.50	5.40	5.50	3.50	3.50	3.50	5.20	4.67
cycles	5.50	5.40	4.67	4.67	3.50	5.40	5.50	3.50	3.50	3.50	5.20	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.17
Dispatch	5.50
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.01 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.17 to 5.50 cycles (2.03x speedup).

ASM code

In the binary file, the address of the loop is: 44419e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x28(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R8,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMPL $0x2,0x3c(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JBE 444460 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R12,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R12,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R15,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOVSXD 0x18(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R10,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 444541 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4a1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 44452a <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x48a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 444518 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x478>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 444506 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x466>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444f4 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x454>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444e2 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x442>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444d0 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM11,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4445a5 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x505>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R11D,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 44419e <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0xfe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]
Source file and lines	pack_kernel.cpp:121-124
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121-124
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 278 paths individually, rerun with max-paths=278
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 5.00 cycles (2.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	68
nb uops	67
loop length	283
used x86 registers	13
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.40	4.67	4.67	3.50	5.40	5.50	3.50	3.50	3.50	5.20	4.67
cycles	5.50	5.40	4.67	4.67	3.50	5.40	5.50	3.50	3.50	3.50	5.20	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.17
Dispatch	5.50
Overall L1	11.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.01 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 44419e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x28(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R8,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R11,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMPL $0x2,0x3c(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JBE 444460 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R12,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R12,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R15,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOVSXD 0x18(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R10,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 444541 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4a1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 44452a <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x48a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 444518 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x478>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 444506 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x466>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444f4 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x454>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444e2 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x442>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4444d0 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM10,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM11,-0x8(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4445a5 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x505>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R11D,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 44419e <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0xfe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code