OV - exec - Loop 276

	Loop Id: 276	Module: exec	Source: context.h:69-69 [...]	Coverage: 0.27%

0x43bdc0 MOV	%R8D,%EAX

0x43bdc3 CLTD

0x43bdc4 IDIVL	0x78(%RSP)    [6]

0x43bdc8 MOV	0x38(%RSP),%ESI    [6]

0x43bdcc MOV	0x3c(%RSP),%EDI    [6]

0x43bdd0 MOV	%R11,%R14

0x43bdd3 INC	%R8D

0x43bdd6 ADD	%ESI,%EAX

0x43bdd8 MOVSXD	%EAX,%RCX

0x43bddb IMUL	%RCX,%R14

0x43bddf ADD	%EDI,%EDX

0x43bde1 MOV	%R12,%RDI

0x43bde4 IMUL	%RCX,%RDI

0x43bde8 MOVSXD	%EDX,%RSI

0x43bdeb INC	%EDX

0x43bded LEA	(%RSI,%R14,1),%R15

0x43bdf1 MOVSXD	%EDX,%RDX

0x43bdf4 VMOVSD	(%R9,%R15,8),%XMM0    [1]

0x43bdfa LEA	(%RSI,%RDI,1),%R15

0x43bdfe ADD	%RDX,%RDI

0x43be01 VMOVSD	(%R10,%R15,8),%XMM1    [2]

0x43be07 VMOVSD	(%R10,%RDI,8),%XMM11    [2]

0x43be0d INC	%EAX

0x43be0f VMULSD	%XMM1,%XMM1,%XMM2

0x43be13 VMULSD	%XMM11,%XMM11,%XMM12

0x43be18 CLTQ

0x43be1a MOV	%R11,%RDI

0x43be1d IMUL	%RAX,%RDI

0x43be21 IMUL	%R12,%RAX

0x43be25 ADD	%RDX,%R14

0x43be28 VMOVSD	(%R9,%R14,8),%XMM3    [1]

0x43be2e LEA	(%RSI,%RAX,1),%R15

0x43be32 LEA	(%RSI,%RDI,1),%R14

0x43be36 ADD	%RDX,%RDI

0x43be39 ADD	%RAX,%RDX

0x43be3c VFMADD132SD	%XMM0,%XMM2,%XMM0

0x43be41 VFMADD132SD	%XMM3,%XMM12,%XMM3

0x43be46 VMOVSD	(%R10,%R15,8),%XMM15    [2]

0x43be4c VMOVSD	(%R10,%RDX,8),%XMM1    [2]

0x43be52 VMULSD	%XMM15,%XMM15,%XMM6

0x43be57 VMULSD	%XMM1,%XMM1,%XMM2

0x43be5b VADDSD	%XMM3,%XMM0,%XMM13

0x43be5f VMOVSD	(%R9,%R14,8),%XMM14    [1]

0x43be65 VMOVSD	(%R9,%RDI,8),%XMM0    [1]

0x43be6b VFMADD231SD	%XMM14,%XMM14,%XMM6

0x43be70 VFMADD132SD	%XMM0,%XMM2,%XMM0

0x43be75 MOV	0x28(%RSP),%RAX    [6]

0x43be7a MOV	%RBX,%RDI

0x43be7d IMUL	%RCX,%RAX

0x43be81 IMUL	%RCX,%RDI

0x43be85 MOV	0x30(%RSP),%RDX    [6]

0x43be8a ADD	%RSI,%RAX

0x43be8d VADDSD	%XMM6,%XMM0,%XMM3

0x43be91 VMOVSD	(%RDX,%RAX,8),%XMM12    [7]

0x43be96 MOV	0x20(%RSP),%R14    [6]

0x43be9b ADD	%RSI,%RDI

0x43be9e VADDSD	%XMM13,%XMM3,%XMM11

0x43bea3 VMULSD	(%R14,%RDI,8),%XMM12,%XMM13    [5]

0x43bea9 MOV	0x60(%RSP),%RDX    [6]

0x43beae MOV	%R13,%R15

0x43beb1 IMUL	%RCX,%R15

0x43beb5 IMUL	%RDX,%RCX

0x43beb9 VMULSD	%XMM9,%XMM13,%XMM14

0x43bebe ADD	%RSI,%R15

0x43bec1 ADD	%RSI,%RCX

0x43bec4 MOV	0x68(%RSP),%RAX    [6]

0x43bec9 MOV	0x70(%RSP),%RSI    [6]

0x43bece VFMADD231SD	(%RAX,%R15,8),%XMM13,%XMM5    [3]

0x43bed4 VFMADD231SD	%XMM11,%XMM14,%XMM7

0x43bed9 VFMADD231SD	(%RSI,%RCX,8),%XMM12,%XMM4    [4]

0x43bedf VADDSD	%XMM12,%XMM10,%XMM10

0x43bee4 VADDSD	%XMM13,%XMM8,%XMM8

0x43bee9 CMP	%R8D,0x40(%RSP)    [6]

0x43beee JNE	43bdc0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 77 - 91

--------------------------------------------------------------------------------

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.68
CQA speedup if FP arith vectorized	2.52
CQA speedup if fully vectorized	10.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P1,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.10
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	13.33
P0 cycles	12.50
P1 cycles	15.10
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	7.80
P6 cycles	7.90
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	7.80
P11 cycles	7.33
DIV/SQRT cycles	6.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	74.00
Nb uops	77.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	10.00
FLOP/cycle	1.66
Nb FLOP add-sub	5.00
Nb FLOP mul	6.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.60
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.08
Vector-efficiency ratio load	12.02
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.68
CQA speedup if FP arith vectorized	2.52
CQA speedup if fully vectorized	10.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P1,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.10
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.50
Front-end cycles	13.33
P0 cycles	12.50
P1 cycles	15.10
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	7.80
P6 cycles	7.90
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	7.80
P11 cycles	7.33
DIV/SQRT cycles	6.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	74.00
Nb uops	77.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	10.00
FLOP/cycle	1.66
Nb FLOP add-sub	5.00
Nb FLOP mul	6.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.60
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.08
Vector-efficiency ratio load	12.02
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.10 to 9.00 cycles (1.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 15.10 to 1.50 cycles (10.07x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.10 to 13.33 cycles (1.13x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.10 to 12.67 cycles (1.19x speedup).

FMA

Detected 7 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77
CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

12: addition or subtraction (7 inside FMA instructions)
13: multiply (7 inside FMA instructions)

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	74
nb uops	77
loop length	308
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.50	12.00	7.33	7.33	0.00	7.80	7.90	0.00	0.00	0.00	7.80	7.33
cycles	12.50	15.10	7.33	7.33	0.00	7.80	7.90	0.00	0.00	0.00	7.80	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	6.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	13.33
Dispatch	15.10
DIV/SQRT	6.00
Data deps.	4.00
Overall L1	15.10

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.10 cycles. At this rate:

5% of peak load performance is reached (10.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43bdc0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD	1	0.50	0	0	0	0	0.50	0	0	1	0.50	scal (6.3%)
IDIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
IMUL %RCX,%R14	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EDI,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOVSXD %EDX,%RSI	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
INC %EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA (%RSI,%R14,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMOVSD (%R9,%R15,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RDI,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVSD (%R10,%R15,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
INC %EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CLTQ	1	0	0.50	0	0	0.50	0	0	0	1	0.33	scal (12.5%)
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%RAX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R14	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R14,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RDI,1),%R14	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VFMADD132SD %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM3,%XMM12,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R10,%R15,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM3,%XMM0,%XMM13	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R9,%R14,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9,%RDI,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD %XMM14,%XMM14,%XMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD %XMM6,%XMM0,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD %XMM13,%XMM3,%XMM11	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD (%R14,%RDI,8),%XMM12,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x60(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R15	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMULSD %XMM9,%XMM13,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RSI,%R15	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RAX,%R15,8),%XMM13,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD %XMM11,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RCX,8),%XMM12,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM12,%XMM10,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,0x40(%RSP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JNE 43bdc0 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x110>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.10 to 9.00 cycles (1.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.10 to 12.67 cycles (1.19x speedup).

FMA

Detected 7 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77
CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

12: addition or subtraction (7 inside FMA instructions)
13: multiply (7 inside FMA instructions)

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	74
nb uops	77
loop length	308
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.50	12.00	7.33	7.33	0.00	7.80	7.90	0.00	0.00	0.00	7.80	7.33
cycles	12.50	15.10	7.33	7.33	0.00	7.80	7.90	0.00	0.00	0.00	7.80	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	6.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	13.33
Dispatch	15.10
DIV/SQRT	6.00
Data deps.	4.00
Overall L1	15.10

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.10 cycles. At this rate:

5% of peak load performance is reached (10.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43bdc0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD	1	0.50	0	0	0	0	0.50	0	0	1	0.50	scal (6.3%)
IDIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
IMUL %RCX,%R14	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EDI,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOVSXD %EDX,%RSI	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
INC %EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA (%RSI,%R14,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMOVSD (%R9,%R15,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RDI,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVSD (%R10,%R15,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
INC %EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMULSD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CLTQ	1	0	0.50	0	0	0.50	0	0	0	1	0.33	scal (12.5%)
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %R12,%RAX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R14	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R14,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RAX,1),%R15	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RDI,1),%R14	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VFMADD132SD %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM3,%XMM12,%XMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R10,%R15,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R10,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM15,%XMM15,%XMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM3,%XMM0,%XMM13	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R9,%R14,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%R9,%RDI,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD %XMM14,%XMM14,%XMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD %XMM6,%XMM0,%XMM3	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VADDSD %XMM13,%XMM3,%XMM11	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD (%R14,%RDI,8),%XMM12,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x60(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R15	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %RDX,%RCX	1	0	1	0	0	0	0	0	0	3	1	N/A
VMULSD %XMM9,%XMM13,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RSI,%R15	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RAX,%R15,8),%XMM13,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD231SD %XMM11,%XMM14,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RCX,8),%XMM12,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM12,%XMM10,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,0x40(%RSP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JNE 43bdc0 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x110>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code