OV - exec - Loop 259

	Loop Id: 259	Module: exec	Source: calc_dt.cpp:52-75 [...]	Coverage: 3.04%

0x4392f0 VMOVDQA32	%ZMM28,%ZMM2

0x4392f6 VEXTRACTI32X8	$0x1,%ZMM2,%YMM4

0x4392fd VPMOVSXDQ	%YMM2,%ZMM1

0x439303 VPMOVSXDQ	%YMM4,%ZMM0

0x439309 VMOVDQA64	0x500(%RSP),%ZMM14    [34]

0x439311 VMOVDQA64	0x440(%RSP),%ZMM4    [34]

0x439319 VPSLLQ	$0x3,%ZMM1,%ZMM3

0x439320 VPSLLQ	$0x3,%ZMM0,%ZMM6

0x439327 VPADDQ	%ZMM14,%ZMM3,%ZMM15

0x43932d VPADDQ	%ZMM4,%ZMM1,%ZMM13

0x439333 VPADDQ	%ZMM14,%ZMM6,%ZMM5

0x439339 VMOVDQA64	0x480(%RSP),%ZMM14    [34]

0x439341 VPSLLQ	$0x3,%ZMM13,%ZMM3

0x439348 VMOVDQA64	0x4c0(%RSP),%ZMM8    [34]

0x439350 KMOVB	%K1,%K3

0x439354 VGATHERQPD	(,%ZMM15,1),%ZMM7{%K3}    [10]

0x43935f VPADDQ	%ZMM14,%ZMM3,%ZMM15

0x439365 KMOVB	%K1,%K4

0x439369 KMOVB	%K1,%K6

0x43936d VGATHERQPD	(,%ZMM5,1),%ZMM6{%K4}    [37]

0x439378 VGATHERQPD	(,%ZMM15,1),%ZMM13{%K6}    [9]

0x439383 VPADDQ	%ZMM4,%ZMM0,%ZMM5

0x439389 VMOVDQA64	0x3c0(%RSP),%ZMM15    [34]

0x439391 KMOVB	%K1,%K5

0x439395 VGATHERQPD	(%RDX,%ZMM8,1),%ZMM9{%K5}    [36]

0x43939c VPSLLQ	$0x3,%ZMM5,%ZMM8

0x4393a3 VPADDQ	%ZMM14,%ZMM8,%ZMM3

0x4393a9 VPADDQ	%ZMM15,%ZMM1,%ZMM14

0x4393af VPSLLQ	$0x3,%ZMM14,%ZMM5

0x4393b6 VMOVDQA64	0x400(%RSP),%ZMM14    [34]

0x4393be VPADDQ	%ZMM15,%ZMM0,%ZMM15

0x4393c4 VPADDQ	%ZMM14,%ZMM5,%ZMM8

0x4393ca VPSLLQ	$0x3,%ZMM15,%ZMM5

0x4393d1 VMOVDQA64	0x340(%RSP),%ZMM15    [34]

0x4393d9 VMOVDQA64	0x380(%RSP),%ZMM24    [34]

0x4393e1 VPADDQ	%ZMM14,%ZMM5,%ZMM14

0x4393e7 KMOVB	%K1,%K7

0x4393eb KMOVB	%K1,%K2

0x4393ef VGATHERQPD	(,%ZMM3,1),%ZMM4{%K7}    [35]

0x4393fa VGATHERQPD	(,%ZMM8,1),%ZMM3{%K2}    [7]

0x439405 VPADDQ	%ZMM15,%ZMM1,%ZMM8

0x43940b KMOVB	%K1,%K3

0x43940f VGATHERQPD	(,%ZMM14,1),%ZMM5{%K3}    [8]

0x43941a VPSLLQ	$0x3,%ZMM8,%ZMM14

0x439421 VPADDQ	%ZMM24,%ZMM14,%ZMM8

0x439427 VPADDQ	%ZMM15,%ZMM0,%ZMM15

0x43942d VADDPD	%ZMM5,%ZMM5,%ZMM5

0x439433 VADDPD	%ZMM3,%ZMM3,%ZMM3

0x439439 KMOVB	%K1,%K4

0x43943d VGATHERQPD	(,%ZMM8,1),%ZMM14{%K4}    [6]

0x439448 VPSLLQ	$0x3,%ZMM15,%ZMM8

0x43944f VPADDQ	%ZMM24,%ZMM8,%ZMM8

0x439455 KMOVB	%K1,%K5

0x439459 VGATHERQPD	(,%ZMM8,1),%ZMM15{%K5}    [5]

0x439464 VDIVPD	%ZMM15,%ZMM5,%ZMM8

0x43946a VMINPD	%ZMM9,%ZMM7,%ZMM7

0x439470 VFMADD132PD	%ZMM4,%ZMM8,%ZMM4

0x439476 VMINPD	%ZMM9,%ZMM6,%ZMM6

0x43947c VDIVPD	%ZMM14,%ZMM3,%ZMM14

0x439482 VFMADD231PD	%ZMM13,%ZMM13,%ZMM14

0x439488 VMOVAPD	0x300(%RSP),%ZMM15    [34]

0x439490 VSQRTPD	%ZMM4,%ZMM4

0x439496 VMULPD	%ZMM15,%ZMM7,%ZMM5

0x43949c VMULPD	%ZMM15,%ZMM6,%ZMM9

0x4394a2 VSQRTPD	%ZMM14,%ZMM13

0x4394a8 VMAXPD	%ZMM22,%ZMM4,%ZMM14

0x4394ae VMAXPD	%ZMM22,%ZMM13,%ZMM8

0x4394b4 VPADDQ	%ZMM29,%ZMM1,%ZMM4

0x4394ba VPSLLQ	$0x3,%ZMM4,%ZMM7

0x4394c1 VDIVPD	%ZMM8,%ZMM5,%ZMM3

0x4394c7 VDIVPD	%ZMM14,%ZMM9,%ZMM13

0x4394cd VMOVAPD	%ZMM3,0x600(%RSP)    [34]

0x4394d5 VMOVAPD	%ZMM13,0x5c0(%RSP)    [34]

0x4394dd VPADDQ	%ZMM12,%ZMM7,%ZMM15

0x4394e3 VPADDQ	%ZMM29,%ZMM0,%ZMM5

0x4394e9 VPADDQ	%ZMM19,%ZMM1,%ZMM9

0x4394ef VPSLLQ	$0x3,%ZMM5,%ZMM8

0x4394f6 VPSLLQ	$0x3,%ZMM9,%ZMM13

0x4394fd KMOVB	%K1,%K6

0x439501 VGATHERQPD	(,%ZMM15,1),%ZMM14{%K6}    [17]

0x43950c VPADDQ	%ZMM19,%ZMM0,%ZMM15

0x439512 VPADDQ	%ZMM12,%ZMM8,%ZMM3

0x439518 VPADDQ	%ZMM12,%ZMM13,%ZMM4

0x43951e VPSLLQ	$0x3,%ZMM15,%ZMM5

0x439525 VPADDD	0xc0(%RSP),%ZMM2,%ZMM2    [34]

0x43952d VPADDQ	%ZMM12,%ZMM5,%ZMM8

0x439533 KMOVB	%K1,%K7

0x439537 KMOVB	%K1,%K2

0x43953b VGATHERQPD	(,%ZMM3,1),%ZMM6{%K7}    [13]

0x439546 VGATHERQPD	(,%ZMM4,1),%ZMM7{%K2}    [16]

0x439551 VPADDQ	%ZMM31,%ZMM1,%ZMM3

0x439557 VPSLLQ	$0x3,%ZMM3,%ZMM13

0x43955e VPADDQ	%ZMM31,%ZMM0,%ZMM5

0x439564 VADDPD	%ZMM7,%ZMM14,%ZMM14

0x43956a KMOVB	%K1,%K3

0x43956e VGATHERQPD	(,%ZMM8,1),%ZMM9{%K3}    [23]

0x439579 VPADDQ	%ZMM26,%ZMM13,%ZMM4

0x43957f VPSLLQ	$0x3,%ZMM5,%ZMM8

0x439586 VADDPD	%ZMM9,%ZMM6,%ZMM6

0x43958c VPMOVSXDQ	%YMM2,%ZMM5

0x439592 VEXTRACTI32X8	$0x1,%ZMM2,%YMM9

0x439599 VPMOVSXDQ	%YMM9,%ZMM2

0x43959f VPADDQ	%ZMM26,%ZMM8,%ZMM3

0x4395a5 KMOVB	%K1,%K4

0x4395a9 VGATHERQPD	(,%ZMM4,1),%ZMM15{%K4}    [15]

0x4395b4 VPADDQ	%ZMM5,%ZMM29,%ZMM4

0x4395ba VMULPD	%ZMM15,%ZMM14,%ZMM7

0x4395c0 VPADDQ	%ZMM5,%ZMM19,%ZMM9

0x4395c6 VPSLLQ	$0x3,%ZMM4,%ZMM15

0x4395cd KMOVB	%K1,%K5

0x4395d1 VGATHERQPD	(,%ZMM3,1),%ZMM13{%K5}    [12]

0x4395dc VPADDQ	%ZMM2,%ZMM29,%ZMM3

0x4395e2 VMULPD	%ZMM13,%ZMM6,%ZMM6

0x4395e8 VPADDQ	%ZMM12,%ZMM15,%ZMM8

0x4395ee VPSLLQ	$0x3,%ZMM3,%ZMM13

0x4395f5 VPSLLQ	$0x3,%ZMM9,%ZMM15

0x4395fc VPADDQ	%ZMM12,%ZMM13,%ZMM14

0x439602 KMOVB	%K1,%K6

0x439606 VPADDQ	%ZMM2,%ZMM19,%ZMM13

0x43960c VGATHERQPD	(,%ZMM8,1),%ZMM4{%K6}    [21]

0x439617 VPADDQ	%ZMM12,%ZMM15,%ZMM8

0x43961d KMOVB	%K1,%K7

0x439621 KMOVB	%K1,%K2

0x439625 VGATHERQPD	(,%ZMM14,1),%ZMM3{%K7}    [14]

0x439630 VGATHERQPD	(,%ZMM8,1),%ZMM15{%K2}    [20]

0x43963b VPSLLQ	$0x3,%ZMM13,%ZMM14

0x439642 VPADDQ	%ZMM5,%ZMM31,%ZMM8

0x439648 VPADDQ	%ZMM12,%ZMM14,%ZMM9

0x43964e VPSLLQ	$0x3,%ZMM8,%ZMM14

0x439655 VADDPD	%ZMM15,%ZMM4,%ZMM4

0x43965b KMOVB	%K1,%K3

0x43965f VGATHERQPD	(,%ZMM9,1),%ZMM13{%K3}    [27]

0x43966a VPADDQ	%ZMM26,%ZMM14,%ZMM9

0x439670 VPADDQ	%ZMM2,%ZMM31,%ZMM8

0x439676 VADDPD	%ZMM13,%ZMM3,%ZMM3

0x43967c KMOVB	%K1,%K4

0x439680 VPADDD	0x100(%RSP),%ZMM28,%ZMM28    [34]

0x439688 VGATHERQPD	(,%ZMM9,1),%ZMM14{%K4}    [26]

0x439693 VMOVDQA64	0x280(%RSP),%ZMM13    [34]

0x43969b VPSLLQ	$0x3,%ZMM8,%ZMM9

0x4396a2 VPADDQ	%ZMM13,%ZMM1,%ZMM15

0x4396a8 VMULPD	%ZMM14,%ZMM4,%ZMM4

0x4396ae VPADDQ	%ZMM26,%ZMM9,%ZMM8

0x4396b4 VMOVDQA64	0x2c0(%RSP),%ZMM14    [34]

0x4396bc KMOVB	%K1,%K5

0x4396c0 VGATHERQPD	(,%ZMM8,1),%ZMM9{%K5}    [19]

0x4396cb VPSLLQ	$0x3,%ZMM15,%ZMM8

0x4396d2 VMULPD	%ZMM9,%ZMM3,%ZMM3

0x4396d8 VPADDQ	%ZMM13,%ZMM0,%ZMM13

0x4396de VPADDQ	%ZMM14,%ZMM8,%ZMM9

0x4396e4 KMOVB	%K1,%K6

0x4396e8 VPSLLQ	$0x3,%ZMM13,%ZMM8

0x4396ef VGATHERQPD	(,%ZMM9,1),%ZMM15{%K6}    [25]

0x4396fa VMULPD	%ZMM22,%ZMM15,%ZMM24

0x439700 VPADDQ	%ZMM14,%ZMM8,%ZMM9

0x439706 VMOVAPD	0x240(%RSP),%ZMM13    [34]

0x43970e VANDPD	%ZMM10,%ZMM4,%ZMM8

0x439714 KMOVB	%K1,%K7

0x439718 VGATHERQPD	(,%ZMM9,1),%ZMM14{%K7}    [24]

0x439723 VANDPD	%ZMM10,%ZMM7,%ZMM9

0x439729 VMAXPD	%ZMM9,%ZMM8,%ZMM8

0x43972f VMULPD	%ZMM13,%ZMM15,%ZMM16

0x439735 VMULPD	%ZMM22,%ZMM14,%ZMM20

0x43973b VMAXPD	%ZMM24,%ZMM8,%ZMM9

0x439741 VMULPD	%ZMM13,%ZMM14,%ZMM17

0x439747 VANDPD	%ZMM10,%ZMM3,%ZMM13

0x43974d VDIVPD	%ZMM9,%ZMM16,%ZMM8

0x439753 VANDPD	%ZMM10,%ZMM6,%ZMM9

0x439759 VMOVAPD	%ZMM8,0x580(%RSP)    [34]

0x439761 VMAXPD	%ZMM9,%ZMM13,%ZMM8

0x439767 VPADDQ	%ZMM30,%ZMM1,%ZMM9

0x43976d KMOVB	%K1,%K2

0x439771 VMAXPD	%ZMM20,%ZMM8,%ZMM13

0x439777 VPSLLQ	$0x3,%ZMM9,%ZMM8

0x43977e KMOVB	%K1,%K3

0x439782 VDIVPD	%ZMM13,%ZMM17,%ZMM17

0x439788 VPADDQ	%ZMM11,%ZMM8,%ZMM13

0x43978e VPADDQ	%ZMM30,%ZMM0,%ZMM8

0x439794 VGATHERQPD	(,%ZMM13,1),%ZMM9{%K2}    [11]

0x43979f VPSLLQ	$0x3,%ZMM8,%ZMM13

0x4397a6 VPADDQ	%ZMM11,%ZMM13,%ZMM13

0x4397ac VGATHERQPD	(,%ZMM13,1),%ZMM8{%K3}    [4]

0x4397b7 VPADDQ	%ZMM30,%ZMM5,%ZMM13

0x4397bd VPSLLQ	$0x3,%ZMM13,%ZMM13

0x4397c4 VPADDQ	%ZMM11,%ZMM13,%ZMM13

0x4397ca KMOVB	%K1,%K4

0x4397ce VGATHERQPD	(,%ZMM13,1),%ZMM27{%K4}    [3]

0x4397d9 VPADDQ	%ZMM30,%ZMM2,%ZMM13

0x4397df VMOVDQA64	0x200(%RSP),%ZMM25    [34]

0x4397e7 VPSLLQ	$0x3,%ZMM13,%ZMM13

0x4397ee VMOVAPD	%ZMM27,0x540(%RSP)    [34]

0x4397f6 VPADDQ	%ZMM11,%ZMM13,%ZMM13

0x4397fc KMOVB	%K1,%K5

0x439800 VGATHERQPD	(,%ZMM13,1),%ZMM27{%K5}    [2]

0x43980b VPADDQ	%ZMM25,%ZMM1,%ZMM13

0x439811 VPSLLQ	$0x3,%ZMM13,%ZMM13

0x439818 VPADDQ	%ZMM23,%ZMM13,%ZMM13

0x43981e KMOVB	%K1,%K6

0x439822 VGATHERQPD	(,%ZMM13,1),%ZMM16{%K6}    [1]

0x43982d VPADDQ	%ZMM25,%ZMM0,%ZMM13

0x439833 VADDPD	0x540(%RSP),%ZMM9,%ZMM9    [34]

0x43983b VPSLLQ	$0x3,%ZMM13,%ZMM13

0x439842 VPADDQ	%ZMM23,%ZMM13,%ZMM13

0x439848 VADDPD	%ZMM27,%ZMM8,%ZMM8

0x43984e KMOVB	%K1,%K7

0x439852 VPADDQ	%ZMM18,%ZMM0,%ZMM27

0x439858 VGATHERQPD	(,%ZMM13,1),%ZMM25{%K7}    [30]

0x439863 VPADDQ	%ZMM18,%ZMM5,%ZMM5

0x439869 VPADDQ	%ZMM18,%ZMM1,%ZMM13

0x43986f VMULPD	%ZMM16,%ZMM9,%ZMM9

0x439875 VPSLLQ	$0x3,%ZMM13,%ZMM13

0x43987c VPSLLQ	$0x3,%ZMM27,%ZMM16

0x439883 VPSLLQ	$0x3,%ZMM5,%ZMM5

0x43988a VPADDQ	%ZMM11,%ZMM16,%ZMM27

0x439890 VPADDQ	%ZMM11,%ZMM13,%ZMM13

0x439896 VMOVDQA64	0x1c0(%RSP),%ZMM16    [34]

0x43989e VPADDQ	%ZMM11,%ZMM5,%ZMM5

0x4398a4 VPADDQ	%ZMM18,%ZMM2,%ZMM2

0x4398aa VMULPD	%ZMM25,%ZMM8,%ZMM8

0x4398b0 KMOVB	%K1,%K2

0x4398b4 KMOVB	%K1,%K3

0x4398b8 VGATHERQPD	(,%ZMM13,1),%ZMM25{%K2}    [29]

0x4398c3 KMOVB	%K1,%K4

0x4398c7 VGATHERQPD	(,%ZMM27,1),%ZMM13{%K3}    [22]

0x4398d2 VGATHERQPD	(,%ZMM5,1),%ZMM27{%K4}    [18]

0x4398dd VPSLLQ	$0x3,%ZMM2,%ZMM5

0x4398e4 VPADDQ	%ZMM11,%ZMM5,%ZMM2

0x4398ea VPADDQ	%ZMM16,%ZMM1,%ZMM1

0x4398f0 VADDPD	%ZMM27,%ZMM25,%ZMM25

0x4398f6 KMOVB	%K1,%K5

0x4398fa VGATHERQPD	(,%ZMM2,1),%ZMM5{%K5}    [33]

0x439905 VPSLLQ	$0x3,%ZMM1,%ZMM2

0x43990c VPADDQ	%ZMM23,%ZMM2,%ZMM1

0x439912 KMOVB	%K1,%K6

0x439916 VGATHERQPD	(,%ZMM1,1),%ZMM2{%K6}    [32]

0x439921 VMULPD	%ZMM2,%ZMM25,%ZMM27

0x439927 VPADDQ	%ZMM16,%ZMM0,%ZMM0

0x43992d VPSLLQ	$0x3,%ZMM0,%ZMM1

0x439934 VADDPD	%ZMM5,%ZMM13,%ZMM13

0x43993a VPADDQ	%ZMM23,%ZMM1,%ZMM0

0x439940 VMOVAPD	0x180(%RSP),%ZMM5    [34]

0x439948 VANDPD	%ZMM10,%ZMM9,%ZMM2

0x43994e KMOVB	%K1,%K7

0x439952 VGATHERQPD	(,%ZMM0,1),%ZMM1{%K7}    [31]

0x43995d VANDPD	%ZMM10,%ZMM27,%ZMM0

0x439963 VMAXPD	%ZMM2,%ZMM0,%ZMM0

0x439969 VMULPD	%ZMM1,%ZMM13,%ZMM13

0x43996f VMULPD	%ZMM5,%ZMM15,%ZMM1

0x439975 VMAXPD	%ZMM24,%ZMM0,%ZMM2

0x43997b VADDPD	%ZMM27,%ZMM4,%ZMM4

0x439981 VADDPD	%ZMM9,%ZMM7,%ZMM7

0x439987 VADDPD	%ZMM13,%ZMM3,%ZMM3

0x43998d VDIVPD	%ZMM2,%ZMM1,%ZMM0

0x439993 VMULPD	%ZMM5,%ZMM14,%ZMM2

0x439999 VANDPD	%ZMM10,%ZMM13,%ZMM1

0x43999f VANDPD	%ZMM10,%ZMM8,%ZMM5

0x4399a5 VSUBPD	%ZMM7,%ZMM4,%ZMM9

0x4399ab VMAXPD	%ZMM5,%ZMM1,%ZMM1

0x4399b1 VADDPD	%ZMM8,%ZMM6,%ZMM6

0x4399b7 VMOVAPD	0x140(%RSP),%ZMM7    [34]

0x4399bf VMAXPD	%ZMM20,%ZMM1,%ZMM5

0x4399c5 VMULPD	0x35f71(%RIP),%ZMM9,%ZMM1    [28]

0x4399cf VSUBPD	%ZMM6,%ZMM3,%ZMM8

0x4399d5 VDIVPD	%ZMM5,%ZMM2,%ZMM2

0x4399db VBROADCASTSD	0x34beb(%RIP),%ZMM5    [28]

0x4399e5 VMULPD	0x35f51(%RIP),%ZMM8,%ZMM13    [28]

0x4399ef VDIVPD	%ZMM15,%ZMM1,%ZMM15

0x4399f5 VCMPPD	$0x1,0x35f80(%RIP),%ZMM15,%K2    [28]

0x439a00 VMOVAPD	%ZMM21,%ZMM9

0x439a06 VDIVPD	%ZMM15,%ZMM5,%ZMM4

0x439a0c VMULPD	%ZMM7,%ZMM4,%ZMM9{%K2}

0x439a12 VDIVPD	%ZMM14,%ZMM13,%ZMM14

0x439a18 VCMPPD	$0x1,0x35f5d(%RIP),%ZMM14,%K3    [28]

0x439a23 VMOVAPD	%ZMM21,%ZMM6

0x439a29 INC	%R9D

0x439a2c VMINPD	0x600(%RSP),%ZMM9,%ZMM1    [34]

0x439a34 VBROADCASTSD	0x34b92(%RIP),%ZMM15    [28]

0x439a3e VMINPD	0x680(%RSP),%ZMM21,%ZMM8    [34]

0x439a46 VDIVPD	%ZMM14,%ZMM15,%ZMM3

0x439a4c VMULPD	%ZMM7,%ZMM3,%ZMM6{%K3}

0x439a52 VMINPD	0x640(%RSP),%ZMM21,%ZMM4    [34]

0x439a5a VMINPD	%ZMM0,%ZMM1,%ZMM0

0x439a60 VMINPD	%ZMM17,%ZMM8,%ZMM13

0x439a66 VMINPD	0x580(%RSP),%ZMM4,%ZMM9    [34]

0x439a6e VMINPD	0x5c0(%RSP),%ZMM6,%ZMM14    [34]

0x439a76 VMINPD	%ZMM0,%ZMM9,%ZMM7

0x439a7c VMINPD	%ZMM2,%ZMM14,%ZMM2

0x439a82 VMOVAPD	%ZMM7,0x640(%RSP)    [34]

0x439a8a VMINPD	%ZMM2,%ZMM13,%ZMM5

0x439a90 VMOVAPD	%ZMM5,0x680(%RSP)    [34]

0x439a98 CMP	%R9D,%R13D

0x439a9b JNE	4392f0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 52 - 75

--------------------------------------------------------------------------------

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:52-75,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	228.00
CQA cycles if no scalar integer	228.00
CQA cycles if FP arith vectorized	228.00
CQA cycles if fully vectorized	228.00
Front-end cycles	76.83
P0 cycles	180.00
P1 cycles	19.00
P2 cycles	103.33
P3 cycles	103.33
P4 cycles	3.00
P5 cycles	180.00
P6 cycles	1.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.40
P11 cycles	103.33
DIV/SQRT cycles	228.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	292.00
Nb uops	461.00
Nb loads	65.00
Nb stores	6.00
Nb stack references	24.00
FLOP/cycle	1.89
Nb FLOP add-sub	128.00
Nb FLOP mul	160.00
Nb FLOP fma	16.00
Nb FLOP div	96.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.44
Bytes prefetched	0.00
Bytes loaded	4048.00
Bytes stored	384.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	35.00
Vectorization ratio all	99.21
Vectorization ratio load	96.92
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	98.21
Vector-efficiency ratio all	98.13
Vector-efficiency ratio load	97.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	95.76

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:52-75,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	228.00
CQA cycles if no scalar integer	228.00
CQA cycles if FP arith vectorized	228.00
CQA cycles if fully vectorized	228.00
Front-end cycles	76.83
P0 cycles	180.00
P1 cycles	19.00
P2 cycles	103.33
P3 cycles	103.33
P4 cycles	3.00
P5 cycles	180.00
P6 cycles	1.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.40
P11 cycles	103.33
DIV/SQRT cycles	228.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	292.00
Nb uops	461.00
Nb loads	65.00
Nb stores	6.00
Nb stack references	24.00
FLOP/cycle	1.89
Nb FLOP add-sub	128.00
Nb FLOP mul	160.00
Nb FLOP fma	16.00
Nb FLOP div	96.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.44
Bytes prefetched	0.00
Bytes loaded	4048.00
Bytes stored	384.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	35.00
Vectorization ratio all	99.21
Vectorization ratio load	96.92
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	98.21
Vector-efficiency ratio all	98.13
Vector-efficiency ratio load	97.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	95.76

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:52-75
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX loads are used in vector version.
98% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 228.00 to 180.00 cycles (1.27x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 228.00 to 159.00 cycles (1.43x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:69
VDIVPD: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:57
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:57
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:66
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:66
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:67
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:70
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:67
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:70
VGATHERQPD: 35 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:53
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
VSQRTPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:56
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 35 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 35 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:53
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

76 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 432 FP arithmetical operations:

144: addition or subtraction (16 inside FMA instructions)
176: multiply (16 inside FMA instructions)
96: divide
16: square root

The binary loop is loading 4048 bytes (506 double precision FP elements). The binary loop is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	292
nb uops	461
loop length	1969
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	32
nb stack references	24
ADD-SUB / MUL ratio	0.80

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	76.83 cycles
front end	76.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	180.00	0.60	103.33	103.33	3.00	180.00	1.00	3.00	3.00	3.00	0.40	103.33
cycles	180.00	19.00	103.33	103.33	3.00	180.00	1.00	3.00	3.00	3.00	0.40	103.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	228.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	76.83
Dispatch	180.00
DIV/SQRT	228.00
Data deps.	1.00
Overall L1	228.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	99%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	98%

Vector efficiency ratios

INT

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	92%

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 228.00 cycles. At this rate:

9% of peak load performance is reached (17.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4392f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQA32 %ZMM28,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM2,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0x500(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA64 0x440(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM1,%ZMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM0,%ZMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM14,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM6,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x480(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x4c0(%RSP),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM15,1),%ZMM7{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM14,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM5,1),%ZMM6{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM15,1),%ZMM13{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM4,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM8,1),%ZMM9{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM14,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x400(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM5,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x340(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA64 0x380(%RSP),%ZMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM5,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM4{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM3{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM15,%ZMM1,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM5{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM24,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM14{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM24,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM15,%ZMM5,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMINPD %ZMM9,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM4,%ZMM8,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM3,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD 0x300(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSQRTPD %ZMM4,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	23-32	18	vect (100.0%)
VMULPD %ZMM15,%ZMM7,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM14,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	23-32	18	vect (100.0%)
VMAXPD %ZMM22,%ZMM4,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM22,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM29,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM4,%ZMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VDIVPD %ZMM8,%ZMM5,%ZMM3	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM14,%ZMM9,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVAPD %ZMM3,0x600(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %ZMM13,0x5c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM12,%ZMM7,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM29,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM19,%ZMM1,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM15,1),%ZMM14{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM19,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDD 0xc0(%RSP),%ZMM2,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM12,%ZMM5,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM6{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM4,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM31,%ZMM1,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM3,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM31,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM9{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM26,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM9,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM2,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM9,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDQ %ZMM26,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM15{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM5,%ZMM29,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM14,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM4,%ZMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM2,%ZMM29,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM15,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM3,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM12,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM2,%ZMM19,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM4{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM12,%ZMM15,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM3{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM15{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM5,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM14,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM15,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM9,1),%ZMM13{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM26,%ZMM14,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDD 0x100(%RSP),%ZMM28,%ZMM28	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VGATHERQPD (,%ZMM9,1),%ZMM14{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMOVDQA64 0x280(%RSP),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM13,%ZMM1,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM26,%ZMM9,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x2c0(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM9{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMULPD %ZMM9,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPSLLQ $0x3,%ZMM13,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VGATHERQPD (,%ZMM9,1),%ZMM15{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM22,%ZMM15,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x240(%RSP),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM4,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM9,1),%ZMM14{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM7,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM9,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM15,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM14,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM24,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM14,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM3,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM9,%ZMM16,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM10,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM8,0x580(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMAXPD %ZMM9,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM30,%ZMM1,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMAXPD %ZMM20,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VDIVPD %ZMM13,%ZMM17,%ZMM17	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPADDQ %ZMM11,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM30,%ZMM0,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM9{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM8{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM30,%ZMM5,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM27{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM30,%ZMM2,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x200(%RSP),%ZMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVAPD %ZMM27,0x540(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM27{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM25,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM16{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM25,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD 0x540(%RSP),%ZMM9,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM18,%ZMM0,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM25{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM18,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM18,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM9,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM27,%ZMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM16,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x1c0(%RSP),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM11,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM18,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM25{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM27,1),%ZMM13{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM5,1),%ZMM27{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM2,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM5,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM16,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM2,1),%ZMM5{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM1,%ZMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM1,1),%ZMM2{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM2,%ZMM25,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM0,%ZMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM5,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM23,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x180(%RSP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM9,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM0,1),%ZMM1{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM15,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM24,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM2,%ZMM1,%ZMM0	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM5,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM8,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM4,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMAXPD %ZMM5,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM8,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMAXPD %ZMM20,%ZMM1,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x35f71(%RIP),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM3,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM5,%ZMM2,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VBROADCASTSD 0x34beb(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD 0x35f51(%RIP),%ZMM8,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM15,%ZMM1,%ZMM15	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VCMPPD $0x1,0x35f80(%RIP),%ZMM15,%K2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VDIVPD %ZMM15,%ZMM5,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM7,%ZMM4,%ZMM9{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM13,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VCMPPD $0x1,0x35f5d(%RIP),%ZMM14,%K3	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
INC %R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMINPD 0x600(%RSP),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VBROADCASTSD 0x34b92(%RIP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMINPD 0x680(%RSP),%ZMM21,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM15,%ZMM3	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM7,%ZMM3,%ZMM6{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD 0x640(%RSP),%ZMM21,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM17,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD 0x580(%RSP),%ZMM4,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD 0x5c0(%RSP),%ZMM6,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM7,0x640(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMINPD %ZMM2,%ZMM13,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM5,0x680(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4392f0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x400>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:52-75
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all SSE/AVX instructions).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX loads are used in vector version.
98% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 228.00 to 159.00 cycles (1.43x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:69
VDIVPD: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:57
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:57
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:66
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:66
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:67
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:70
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:67
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:70
VGATHERQPD: 35 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:53
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
VSQRTPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:56
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 35 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 35 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:53
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:54
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:59
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:62
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:64

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

76 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 432 FP arithmetical operations:

144: addition or subtraction (16 inside FMA instructions)
176: multiply (16 inside FMA instructions)
96: divide
16: square root

The binary loop is loading 4048 bytes (506 double precision FP elements). The binary loop is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	292
nb uops	461
loop length	1969
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	32
nb stack references	24
ADD-SUB / MUL ratio	0.80

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	76.83 cycles
front end	76.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	180.00	0.60	103.33	103.33	3.00	180.00	1.00	3.00	3.00	3.00	0.40	103.33
cycles	180.00	19.00	103.33	103.33	3.00	180.00	1.00	3.00	3.00	3.00	0.40	103.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	228.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	76.83
Dispatch	180.00
DIV/SQRT	228.00
Data deps.	1.00
Overall L1	228.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	99%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	98%

Vector efficiency ratios

INT

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	92%

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 228.00 cycles. At this rate:

9% of peak load performance is reached (17.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4392f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQA32 %ZMM28,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM2,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM2,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM4,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0x500(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA64 0x440(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM1,%ZMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM0,%ZMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM14,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM4,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM6,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x480(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x4c0(%RSP),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM15,1),%ZMM7{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM14,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM5,1),%ZMM6{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM15,1),%ZMM13{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM4,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM8,1),%ZMM9{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM14,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x400(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM5,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVDQA64 0x340(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA64 0x380(%RSP),%ZMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM5,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM4{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM3{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM15,%ZMM1,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM5{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM24,%ZMM14,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM15,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM14{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM24,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM15,%ZMM5,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMINPD %ZMM9,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM4,%ZMM8,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM9,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM3,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD 0x300(%RSP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSQRTPD %ZMM4,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	23-32	18	vect (100.0%)
VMULPD %ZMM15,%ZMM7,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM14,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	23-32	18	vect (100.0%)
VMAXPD %ZMM22,%ZMM4,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM22,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM29,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM4,%ZMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VDIVPD %ZMM8,%ZMM5,%ZMM3	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM14,%ZMM9,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMOVAPD %ZMM3,0x600(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %ZMM13,0x5c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM12,%ZMM7,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM29,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM19,%ZMM1,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM15,1),%ZMM14{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM19,%ZMM0,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDD 0xc0(%RSP),%ZMM2,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VPADDQ %ZMM12,%ZMM5,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM6{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM4,1),%ZMM7{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM31,%ZMM1,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM3,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM31,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM9{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM26,%ZMM13,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM9,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM2,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM9,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDQ %ZMM26,%ZMM8,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM4,1),%ZMM15{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM5,%ZMM29,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM14,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM19,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM4,%ZMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM3,1),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM2,%ZMM29,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM15,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM3,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM15	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM12,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM2,%ZMM19,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM4{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM12,%ZMM15,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM14,1),%ZMM3{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM8,1),%ZMM15{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM5,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM12,%ZMM14,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM15,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM9,1),%ZMM13{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM26,%ZMM14,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDD 0x100(%RSP),%ZMM28,%ZMM28	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VGATHERQPD (,%ZMM9,1),%ZMM14{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMOVDQA64 0x280(%RSP),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM13,%ZMM1,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM26,%ZMM9,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x2c0(%RSP),%ZMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM8,1),%ZMM9{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM15,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMULPD %ZMM9,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM13,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPSLLQ $0x3,%ZMM13,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VGATHERQPD (,%ZMM9,1),%ZMM15{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM22,%ZMM15,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM14,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x240(%RSP),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM4,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM9,1),%ZMM14{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM7,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM9,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM15,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM14,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM24,%ZMM8,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM14,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM3,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM9,%ZMM16,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM10,%ZMM6,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM8,0x580(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMAXPD %ZMM9,%ZMM13,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM30,%ZMM1,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMAXPD %ZMM20,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM9,%ZMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VDIVPD %ZMM13,%ZMM17,%ZMM17	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPADDQ %ZMM11,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM30,%ZMM0,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM9{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM8,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM8{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM30,%ZMM5,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM27{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM30,%ZMM2,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x200(%RSP),%ZMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VMOVAPD %ZMM27,0x540(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM27{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM25,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM16{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM25,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD 0x540(%RSP),%ZMM9,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM18,%ZMM0,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VGATHERQPD (,%ZMM13,1),%ZMM25{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM18,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM18,%ZMM1,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM9,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM13,%ZMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM27,%ZMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPSLLQ $0x3,%ZMM5,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM16,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM11,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 0x1c0(%RSP),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDQ %ZMM11,%ZMM5,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM18,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM13,1),%ZMM25{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM27,1),%ZMM13{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (,%ZMM5,1),%ZMM27{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM2,%ZMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM11,%ZMM5,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM16,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM25,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM2,1),%ZMM5{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPSLLQ $0x3,%ZMM1,%ZMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VPADDQ %ZMM23,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM1,1),%ZMM2{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM2,%ZMM25,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDQ %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPSLLQ $0x3,%ZMM0,%ZMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	2-4	1	vect (100.0%)
VADDPD %ZMM5,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM23,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD 0x180(%RSP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM9,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (,%ZMM0,1),%ZMM1{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMAXPD %ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM15,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM24,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM27,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM2,%ZMM1,%ZMM0	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM5,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM8,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM4,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMAXPD %ZMM5,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM8,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMAXPD %ZMM20,%ZMM1,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x35f71(%RIP),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM3,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM5,%ZMM2,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VBROADCASTSD 0x34beb(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMULPD 0x35f51(%RIP),%ZMM8,%ZMM13	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM15,%ZMM1,%ZMM15	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VCMPPD $0x1,0x35f80(%RIP),%ZMM15,%K2	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VDIVPD %ZMM15,%ZMM5,%ZMM4	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM7,%ZMM4,%ZMM9{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM13,%ZMM14	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VCMPPD $0x1,0x35f5d(%RIP),%ZMM14,%K3	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
INC %R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMINPD 0x600(%RSP),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VBROADCASTSD 0x34b92(%RIP),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VMINPD 0x680(%RSP),%ZMM21,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VDIVPD %ZMM14,%ZMM15,%ZMM3	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VMULPD %ZMM7,%ZMM3,%ZMM6{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD 0x640(%RSP),%ZMM21,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM17,%ZMM8,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD 0x580(%RSP),%ZMM4,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD 0x5c0(%RSP),%ZMM6,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM7,0x640(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMINPD %ZMM2,%ZMM13,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM5,0x680(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4392f0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x400>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code