OV - exec - Loop 215

	Loop Id: 215	Module: exec	Source: advec_cell.cpp:163-202 [...]	Coverage: 3.32%

0x42fce0 VMOVUPD	(%R8,%RDX,1),%ZMM10    [4]

0x42fce7 VMOVUPD	0x40(%R8,%RDX,1),%ZMM11    [4]

0x42fcef VCMPPD	$0xe,%ZMM26,%ZMM10,%K3

0x42fcf6 VCMPPD	$0xe,%ZMM26,%ZMM11,%K2

0x42fcfd VMOVDQA32	0x280(%RSP),%ZMM6    [8]

0x42fd05 VPBLENDMQ	%ZMM29,%ZMM25,%ZMM13{%K3}

0x42fd0b VPMOVSXDQ	%YMM6,%ZMM7

0x42fd11 VPADDD	0x80(%RSP),%ZMM6,%ZMM8    [8]

0x42fd19 VEXTRACTI32X8	$0x1,%ZMM6,%YMM9

0x42fd20 VMOVDQA64	0xc0(%RSP),%ZMM6    [8]

0x42fd28 VPBLENDMQ	%ZMM29,%ZMM25,%ZMM12{%K2}

0x42fd2e VPMULLQ	%ZMM6,%ZMM12,%ZMM5

0x42fd34 VPMULLQ	%ZMM6,%ZMM13,%ZMM21

0x42fd3a VPMOVSXDQ	%YMM9,%ZMM2

0x42fd40 VMOVDQA64	0x100(%RSP),%ZMM0    [8]

0x42fd48 VMOVDQA32	%ZMM8,0x280(%RSP)    [8]

0x42fd50 VPADDQ	%ZMM2,%ZMM5,%ZMM23

0x42fd56 VANDPD	(%R8,%RDX,1),%ZMM28,%ZMM8    [4]

0x42fd5d VANDPD	0x40(%R8,%RDX,1),%ZMM28,%ZMM11    [4]

0x42fd65 VBROADCASTSD	(%R12),%ZMM6    [2]

0x42fd6c VPADDQ	%ZMM7,%ZMM21,%ZMM21

0x42fd72 VPBLENDMQ	%ZMM29,%ZMM22,%ZMM3{%K3}

0x42fd78 VPBLENDMQ	%ZMM29,%ZMM22,%ZMM4{%K2}

0x42fd7e VPBLENDMQ	%ZMM0,%ZMM22,%ZMM17{%K3}

0x42fd84 VPBLENDMQ	%ZMM0,%ZMM22,%ZMM16{%K2}

0x42fd8a KMOVB	%K1,%K4

0x42fd8e KMOVB	%K1,%K5

0x42fd92 VGATHERQPD	(%R9,%ZMM21,8),%ZMM1{%K4}    [1]

0x42fd99 VGATHERQPD	(%R9,%ZMM23,8),%ZMM10{%K5}    [1]

0x42fda0 KMOVB	%K1,%K6

0x42fda4 KMOVB	%K1,%K7

0x42fda8 VGATHERQPD	(%R13,%ZMM3,8),%ZMM0{%K6}    [5]

0x42fdb0 VGATHERQPD	(%R13,%ZMM4,8),%ZMM3{%K7}    [5]

0x42fdb8 VDIVPD	%ZMM1,%ZMM8,%ZMM9

0x42fdbe VDIVPD	%ZMM10,%ZMM11,%ZMM8

0x42fdc4 VDIVPD	%ZMM0,%ZMM6,%ZMM1

0x42fdca VDIVPD	%ZMM3,%ZMM6,%ZMM11

0x42fdd0 VBROADCASTSD	0x3f83e(%RIP),%ZMM6    [7]

0x42fdda VADDPD	%ZMM31,%ZMM9,%ZMM4

0x42fde0 VSUBPD	%ZMM9,%ZMM6,%ZMM3

0x42fde6 VADDPD	%ZMM31,%ZMM8,%ZMM10

0x42fdec VMULPD	%ZMM1,%ZMM4,%ZMM5

0x42fdf2 VMOVAPD	%ZMM3,0x2c0(%RSP)    [8]

0x42fdfa VMULPD	%ZMM11,%ZMM10,%ZMM0

0x42fe00 VPMULLQ	%ZMM27,%ZMM16,%ZMM3

0x42fe06 VPMULLQ	%ZMM27,%ZMM17,%ZMM10

0x42fe0c VMOVAPD	%ZMM5,0x300(%RSP)    [8]

0x42fe14 VBROADCASTSD	0x3f7fa(%RIP),%ZMM4    [7]

0x42fe1e VPMULLQ	%ZMM27,%ZMM12,%ZMM5

0x42fe24 VPBLENDMQ	%ZMM25,%ZMM29,%ZMM15{%K3}

0x42fe2a VPADDQ	%ZMM7,%ZMM10,%ZMM11

0x42fe30 VPBLENDMQ	%ZMM25,%ZMM29,%ZMM14{%K2}

0x42fe36 VPADDQ	%ZMM2,%ZMM3,%ZMM10

0x42fe3c VSUBPD	%ZMM8,%ZMM4,%ZMM20

0x42fe42 VPMULLQ	%ZMM27,%ZMM14,%ZMM18

0x42fe48 KMOVB	%K1,%K4

0x42fe4c KMOVB	%K1,%K5

0x42fe50 VGATHERQPD	(%RAX,%ZMM11,8),%ZMM4{%K4}    [3]

0x42fe57 VGATHERQPD	(%RAX,%ZMM10,8),%ZMM11{%K5}    [3]

0x42fe5e VPMULLQ	%ZMM27,%ZMM15,%ZMM10

0x42fe64 VPMULLQ	%ZMM27,%ZMM13,%ZMM1

0x42fe6a VPADDQ	%ZMM2,%ZMM5,%ZMM24

0x42fe70 KMOVB	%K1,%K2

0x42fe74 VGATHERQPD	(%RAX,%ZMM24,8),%ZMM5{%K2}    [3]

0x42fe7b VSUBPD	%ZMM11,%ZMM5,%ZMM3

0x42fe81 VPADDQ	%ZMM2,%ZMM18,%ZMM19

0x42fe87 VPADDQ	%ZMM7,%ZMM10,%ZMM11

0x42fe8d KMOVB	%K1,%K6

0x42fe91 KMOVB	%K1,%K7

0x42fe95 VGATHERQPD	(%RAX,%ZMM11,8),%ZMM10{%K6}    [3]

0x42fe9c VGATHERQPD	(%RAX,%ZMM19,8),%ZMM11{%K7}    [3]

0x42fea3 VSUBPD	%ZMM5,%ZMM11,%ZMM11

0x42fea9 VPADDQ	%ZMM7,%ZMM1,%ZMM1

0x42feaf KMOVB	%K1,%K3

0x42feb3 VGATHERQPD	(%RAX,%ZMM1,8),%ZMM6{%K3}    [3]

0x42feba VSUBPD	%ZMM6,%ZMM10,%ZMM10

0x42fec0 VCMPPD	$0x2,%ZMM26,%ZMM11,%K2

0x42fec7 VSUBPD	%ZMM4,%ZMM6,%ZMM4

0x42fecd VCMPPD	$0x2,%ZMM26,%ZMM10,%K3

0x42fed4 VBLENDMPD	0x3f7a2(%RIP),%ZMM31,%ZMM19{%K2}    [7]

0x42fede VMOVAPD	%ZMM19,0x1c0(%RSP)    [8]

0x42fee6 VMULPD	%ZMM11,%ZMM3,%ZMM19

0x42feec VBLENDMPD	0x3f78a(%RIP),%ZMM31,%ZMM18{%K3}    [7]

0x42fef6 VMOVAPD	%ZMM18,0x200(%RSP)    [8]

0x42fefe VMULPD	%ZMM10,%ZMM4,%ZMM18

0x42ff04 VANDPD	%ZMM28,%ZMM11,%ZMM11

0x42ff0a VMOVAPD	%ZMM19,0x140(%RSP)    [8]

0x42ff12 VMULPD	%ZMM11,%ZMM20,%ZMM19

0x42ff18 VANDPD	%ZMM28,%ZMM10,%ZMM10

0x42ff1e VMOVAPD	%ZMM18,0x180(%RSP)    [8]

0x42ff26 VMULPD	0x2c0(%RSP),%ZMM10,%ZMM18    [8]

0x42ff2e VANDPD	%ZMM28,%ZMM3,%ZMM3

0x42ff34 VFMADD231PD	%ZMM3,%ZMM0,%ZMM19

0x42ff3a VANDPD	%ZMM28,%ZMM4,%ZMM4

0x42ff40 VMINPD	%ZMM11,%ZMM3,%ZMM3

0x42ff46 VFMADD231PD	0x300(%RSP),%ZMM4,%ZMM18    [8]

0x42ff4e VSUBPD	%ZMM9,%ZMM31,%ZMM9

0x42ff54 VMULPD	0x3f762(%RIP),%ZMM19,%ZMM19    [7]

0x42ff5e VSUBPD	%ZMM8,%ZMM31,%ZMM8

0x42ff64 VMOVAPD	0x180(%RSP),%ZMM11    [8]

0x42ff6c VMULPD	0x3f74a(%RIP),%ZMM18,%ZMM18    [7]

0x42ff76 VMINPD	%ZMM10,%ZMM4,%ZMM4

0x42ff7c VMINPD	%ZMM3,%ZMM19,%ZMM3

0x42ff82 VCMPPD	$0xe,%ZMM26,%ZMM11,%K4

0x42ff89 VMULPD	0x1c0(%RSP),%ZMM8,%ZMM8    [8]

0x42ff91 VMULPD	0x200(%RSP),%ZMM9,%ZMM11    [8]

0x42ff99 VMOVAPD	0x140(%RSP),%ZMM19    [8]

0x42ffa1 VMINPD	%ZMM4,%ZMM18,%ZMM10

0x42ffa7 VCMPPD	$0xe,%ZMM26,%ZMM19,%K5

0x42ffae VPMULLQ	%ZMM30,%ZMM13,%ZMM13

0x42ffb4 VFMADD231PD	%ZMM11,%ZMM10,%ZMM6{%K4}

0x42ffba VFMADD231PD	%ZMM8,%ZMM3,%ZMM5{%K5}

0x42ffc0 VPMULLQ	%ZMM30,%ZMM12,%ZMM12

0x42ffc6 VPMULLQ	%ZMM30,%ZMM17,%ZMM17

0x42ffcc VPMULLQ	%ZMM30,%ZMM16,%ZMM16

0x42ffd2 VMULPD	(%R8,%RDX,1),%ZMM6,%ZMM6    [4]

0x42ffd9 VMULPD	0x40(%R8,%RDX,1),%ZMM5,%ZMM5    [4]

0x42ffe1 VPMULLQ	%ZMM30,%ZMM15,%ZMM15

0x42ffe7 VPMULLQ	%ZMM30,%ZMM14,%ZMM14

0x42ffed VPADDQ	%ZMM2,%ZMM12,%ZMM3

0x42fff3 VMOVUPD	%ZMM6,(%RDI,%RDX,1)    [6]

0x42fffa VMOVUPD	%ZMM5,0x40(%RDI,%RDX,1)    [6]

0x430002 KMOVB	%K1,%K6

0x430006 KMOVB	%K1,%K7

0x43000a VGATHERQPD	(%RAX,%ZMM1,8),%ZMM4{%K6}    [3]

0x430011 VGATHERQPD	(%RAX,%ZMM24,8),%ZMM8{%K7}    [3]

0x430018 VPADDQ	%ZMM7,%ZMM13,%ZMM1

0x43001e VPADDQ	%ZMM2,%ZMM16,%ZMM24

0x430024 KMOVB	%K1,%K2

0x430028 VGATHERQPD	(%R9,%ZMM23,8),%ZMM10{%K2}    [1]

0x43002f VPADDQ	%ZMM7,%ZMM17,%ZMM23

0x430035 VPADDQ	%ZMM2,%ZMM14,%ZMM2

0x43003b VPADDQ	%ZMM7,%ZMM15,%ZMM7

0x430041 KMOVB	%K1,%K3

0x430045 KMOVB	%K1,%K4

0x430049 VGATHERQPD	(%R9,%ZMM21,8),%ZMM9{%K3}    [1]

0x430050 KMOVB	%K1,%K5

0x430054 VGATHERQPD	(%RCX,%ZMM1,8),%ZMM21{%K4}    [10]

0x43005b VGATHERQPD	(%RCX,%ZMM3,8),%ZMM13{%K5}    [10]

0x430062 KMOVB	%K1,%K6

0x430066 KMOVB	%K1,%K7

0x43006a VGATHERQPD	(%RCX,%ZMM23,8),%ZMM1{%K6}    [10]

0x430071 VGATHERQPD	(%RCX,%ZMM24,8),%ZMM11{%K7}    [10]

0x430078 VSUBPD	%ZMM1,%ZMM21,%ZMM3

0x43007e KMOVB	%K1,%K3

0x430082 VSUBPD	%ZMM11,%ZMM13,%ZMM1

0x430088 VGATHERQPD	(%RCX,%ZMM7,8),%ZMM12{%K3}    [10]

0x43008f KMOVB	%K1,%K2

0x430093 VGATHERQPD	(%RCX,%ZMM2,8),%ZMM11{%K2}    [10]

0x43009a VSUBPD	%ZMM13,%ZMM11,%ZMM7

0x4300a0 VSUBPD	%ZMM21,%ZMM12,%ZMM2

0x4300a6 VANDPD	%ZMM28,%ZMM1,%ZMM11

0x4300ac VMULPD	%ZMM7,%ZMM1,%ZMM12

0x4300b2 VMULPD	%ZMM2,%ZMM3,%ZMM15

0x4300b8 VCMPPD	$0x2,%ZMM26,%ZMM2,%K4

0x4300bf VCMPPD	$0x2,%ZMM26,%ZMM7,%K5

0x4300c6 VANDPD	%ZMM28,%ZMM2,%ZMM2

0x4300cc VANDPD	%ZMM28,%ZMM7,%ZMM7

0x4300d2 VMULPD	%ZMM7,%ZMM20,%ZMM20

0x4300d8 VMULPD	0x2c0(%RSP),%ZMM2,%ZMM1    [8]

0x4300e0 VANDPD	%ZMM28,%ZMM3,%ZMM3

0x4300e6 VMULPD	%ZMM9,%ZMM4,%ZMM4

0x4300ec VMULPD	%ZMM10,%ZMM8,%ZMM8

0x4300f2 VFMADD132PD	%ZMM11,%ZMM20,%ZMM0

0x4300f8 VFMADD231PD	0x300(%RSP),%ZMM3,%ZMM1    [8]

0x430100 VMINPD	%ZMM7,%ZMM11,%ZMM11

0x430106 VMINPD	%ZMM2,%ZMM3,%ZMM3

0x43010c VBLENDMPD	0x3f56a(%RIP),%ZMM31,%ZMM14{%K4}    [7]

0x430116 VMULPD	0x3f5a0(%RIP),%ZMM0,%ZMM0    [7]

0x430120 VMULPD	0x3f596(%RIP),%ZMM1,%ZMM1    [7]

0x43012a VBLENDMPD	0x3f54c(%RIP),%ZMM31,%ZMM18{%K5}    [7]

0x430134 VCMPPD	$0xe,%ZMM26,%ZMM15,%K6

0x43013b VCMPPD	$0xe,%ZMM26,%ZMM12,%K7

0x430142 VMINPD	%ZMM11,%ZMM0,%ZMM7

0x430148 VMINPD	%ZMM3,%ZMM1,%ZMM2

0x43014e VANDPD	%ZMM28,%ZMM6,%ZMM15

0x430154 VMULPD	%ZMM18,%ZMM7,%ZMM0

0x43015a VMULPD	%ZMM14,%ZMM2,%ZMM14

0x430160 VANDPD	%ZMM28,%ZMM5,%ZMM12

0x430166 VDIVPD	%ZMM4,%ZMM15,%ZMM9

0x43016c VDIVPD	%ZMM8,%ZMM12,%ZMM10

0x430172 VSUBPD	%ZMM9,%ZMM31,%ZMM11

0x430178 VSUBPD	%ZMM10,%ZMM31,%ZMM7

0x43017e VFMADD231PD	%ZMM14,%ZMM11,%ZMM21{%K6}

0x430184 VFMADD231PD	%ZMM0,%ZMM7,%ZMM13{%K7}

0x43018a VMULPD	%ZMM6,%ZMM21,%ZMM19

0x430190 VMULPD	%ZMM5,%ZMM13,%ZMM6

0x430196 VMOVUPD	%ZMM19,(%RSI,%RDX,1)    [9]

0x43019d VMOVUPD	%ZMM6,0x40(%RSI,%RDX,1)    [9]

0x4301a5 SUB	$-0x80,%RDX

0x4301a9 CMP	%RDX,%R10

0x4301ac JNE	42fce0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 163 - 202

--------------------------------------------------------------------------------

163:           if (vol_flux_y(i, j) > 0.0) {

[...]

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○97.58	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.42	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source	advec_cell.cpp:163-163,advec_cell.cpp:174-202,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	124.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	124.00
CQA cycles if fully vectorized	124.00
Front-end cycles	57.17
P0 cycles	124.00
P1 cycles	24.00
P2 cycles	63.00
P3 cycles	63.00
P4 cycles	5.50
P5 cycles	124.00
P6 cycles	1.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.00
P11 cycles	63.00
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	192.00
Nb uops	339.00
Nb loads	49.00
Nb stores	11.00
Nb stack references	10.00
FLOP/cycle	4.00
Nb FLOP add-sub	128.00
Nb FLOP mul	192.00
Nb FLOP fma	64.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.61
Bytes prefetched	0.00
Bytes loaded	2968.00
Bytes stored	704.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	98.22
Vectorization ratio load	93.88
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	95.59
Vector-efficiency ratio all	97.56
Vector-efficiency ratio load	94.64
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.93

Metric	Value
CQA speedup if no scalar integer	1.09
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source	advec_cell.cpp:163-163,advec_cell.cpp:174-202,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	124.00
CQA cycles if no scalar integer	114.00
CQA cycles if FP arith vectorized	124.00
CQA cycles if fully vectorized	124.00
Front-end cycles	57.17
P0 cycles	124.00
P1 cycles	24.00
P2 cycles	63.00
P3 cycles	63.00
P4 cycles	5.50
P5 cycles	124.00
P6 cycles	1.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.00
P11 cycles	63.00
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	192.00
Nb uops	339.00
Nb loads	49.00
Nb stores	11.00
Nb stack references	10.00
FLOP/cycle	4.00
Nb FLOP add-sub	128.00
Nb FLOP mul	192.00
Nb FLOP fma	64.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.61
Bytes prefetched	0.00
Bytes loaded	2968.00
Bytes stored	704.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	98.22
Vectorization ratio load	93.88
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	95.59
Vector-efficiency ratio all	97.56
Vector-efficiency ratio load	94.64
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source file and lines	advec_cell.cpp:163-202
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163,174-202
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 124.00 to 114.00 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions).

Details

98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX loads are used in vector version.
95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 124.00 to 115.00 cycles (1.08x speedup).

Special instructions executing on a single port

1.29x slowdown from special instructions executing on a single port.

Details

KMOVB: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VCMPPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
VEXTRACTI32X8: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VPMOVSXDQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VPMULLQ: 14 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

192: addition or subtraction (64 inside FMA instructions)
256: multiply (64 inside FMA instructions)
48: divide

The binary loop is loading 2968 bytes (371 double precision FP elements). The binary loop is storing 704 bytes (88 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	192
nb uops	339
loop length	1234
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	32
nb stack references	10
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	57.17 cycles
front end	57.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	124.00	0.00	63.00	63.00	5.50	124.00	1.00	5.50	5.50	5.50	0.00	63.00
cycles	124.00	24.00	63.00	63.00	5.50	124.00	1.00	5.50	5.50	5.50	0.00	63.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	57.17
Dispatch	124.00
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	124.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	97%
load	93%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	98%
load	93%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Vector efficiency ratios

INT

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	86%

all	97%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	97%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 124.00 cycles. At this rate:

12% of peak load performance is reached (23.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42fce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RDX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM10,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM11,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVDQA32 0x280(%RSP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM25,%ZMM13{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM6,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDD 0x80(%RSP),%ZMM6,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM6,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0xc0(%RSP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM25,%ZMM12{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM12,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM13,%ZMM21	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM9,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0x100(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA32 %ZMM8,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD (%R8,%RDX,1),%ZMM28,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VANDPD 0x40(%R8,%RDX,1),%ZMM28,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VBROADCASTSD (%R12),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPADDQ %ZMM7,%ZMM21,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM22,%ZMM3{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM22,%ZMM4{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM0,%ZMM22,%ZMM17{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM0,%ZMM22,%ZMM16{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM21,8),%ZMM1{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%R9,%ZMM23,8),%ZMM10{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R13,%ZMM3,8),%ZMM0{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%R13,%ZMM4,8),%ZMM3{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM1,%ZMM8,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM10,%ZMM11,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM0,%ZMM6,%ZMM1	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM3,%ZMM6,%ZMM11	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VBROADCASTSD 0x3f83e(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VADDPD %ZMM31,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM6,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM31,%ZMM8,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM4,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM3,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM10,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM16,%ZMM3	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM17,%ZMM10	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VMOVAPD %ZMM5,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VBROADCASTSD 0x3f7fa(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMULLQ %ZMM27,%ZMM12,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBLENDMQ %ZMM25,%ZMM29,%ZMM15{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM25,%ZMM29,%ZMM14{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM4,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM14,%ZMM18	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM11,8),%ZMM4{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM10,8),%ZMM11{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMULLQ %ZMM27,%ZMM15,%ZMM10	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM13,%ZMM1	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM24,8),%ZMM5{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM11,%ZMM5,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM18,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM11,8),%ZMM10{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM19,8),%ZMM11{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM5,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM1,8),%ZMM6{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM6,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM11,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM4,%ZMM6,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM10,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VBLENDMPD 0x3f7a2(%RIP),%ZMM31,%ZMM19{%K2}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVAPD %ZMM19,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM3,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD 0x3f78a(%RIP),%ZMM31,%ZMM18{%K3}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVAPD %ZMM18,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM10,%ZMM4,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM19,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM20,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM18,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD 0x2c0(%RSP),%ZMM10,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM0,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM11,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x300(%RSP),%ZMM4,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM31,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x3f762(%RIP),%ZMM19,%ZMM19	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x180(%RSP),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD 0x3f74a(%RIP),%ZMM18,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM10,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM3,%ZMM19,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM11,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMULPD 0x1c0(%RSP),%ZMM8,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x200(%RSP),%ZMM9,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%ZMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMINPD %ZMM4,%ZMM18,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM19,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMULLQ %ZMM30,%ZMM13,%ZMM13	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM10,%ZMM6{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM3,%ZMM5{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM12,%ZMM12	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM17,%ZMM17	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM16,%ZMM16	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VMULPD (%R8,%RDX,1),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x40(%R8,%RDX,1),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM15,%ZMM15	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM14,%ZMM14	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM12,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM5,0x40(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM1,8),%ZMM4{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM24,8),%ZMM8{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM7,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM16,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM23,8),%ZMM10{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM7,%ZMM17,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM15,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM21,8),%ZMM9{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM1,8),%ZMM21{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RCX,%ZMM3,8),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM23,8),%ZMM1{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RCX,%ZMM24,8),%ZMM11{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM1,%ZMM21,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VSUBPD %ZMM11,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM7,8),%ZMM12{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM2,8),%ZMM11{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM13,%ZMM11,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM21,%ZMM12,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM1,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM2,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM7,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM28,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM20,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x2c0(%RSP),%ZMM2,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM20,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x300(%RSP),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM7,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM2,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD 0x3f56a(%RIP),%ZMM31,%ZMM14{%K4}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMULPD 0x3f5a0(%RIP),%ZMM0,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x3f596(%RIP),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VBLENDMPD 0x3f54c(%RIP),%ZMM31,%ZMM18{%K5}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM15,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM12,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM11,%ZMM0,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM3,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM6,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM7,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM4,%ZMM15,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM8,%ZMM12,%ZMM10	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM9,%ZMM31,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM31,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM11,%ZMM21{%K6}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM7,%ZMM13{%K7}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM21,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM13,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM19,(%RSI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM6,0x40(%RSI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42fce0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source file and lines	advec_cell.cpp:163-202
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163,174-202
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions).

Details

98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX loads are used in vector version.
95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 124.00 to 115.00 cycles (1.08x speedup).

Special instructions executing on a single port

1.29x slowdown from special instructions executing on a single port.

Details

KMOVB: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VCMPPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
VEXTRACTI32X8: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VPMOVSXDQ: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
VPMULLQ: 14 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

192: addition or subtraction (64 inside FMA instructions)
256: multiply (64 inside FMA instructions)
48: divide

The binary loop is loading 2968 bytes (371 double precision FP elements). The binary loop is storing 704 bytes (88 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	192
nb uops	339
loop length	1234
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	32
nb stack references	10
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	57.17 cycles
front end	57.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	124.00	0.00	63.00	63.00	5.50	124.00	1.00	5.50	5.50	5.50	0.00	63.00
cycles	124.00	24.00	63.00	63.00	5.50	124.00	1.00	5.50	5.50	5.50	0.00	63.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	57.17
Dispatch	124.00
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	124.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	97%
load	93%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	98%
load	93%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Vector efficiency ratios

INT

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	86%

all	97%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

INT+FP

all	97%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 124.00 cycles. At this rate:

12% of peak load performance is reached (23.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42fce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RDX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%RDX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM10,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM11,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVDQA32 0x280(%RSP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM25,%ZMM13{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM6,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDD 0x80(%RSP),%ZMM6,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM6,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0xc0(%RSP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM25,%ZMM12{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM12,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM6,%ZMM13,%ZMM21	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM9,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 0x100(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQA32 %ZMM8,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD (%R8,%RDX,1),%ZMM28,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VANDPD 0x40(%R8,%RDX,1),%ZMM28,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VBROADCASTSD (%R12),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPADDQ %ZMM7,%ZMM21,%ZMM21	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM22,%ZMM3{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM29,%ZMM22,%ZMM4{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM0,%ZMM22,%ZMM17{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM0,%ZMM22,%ZMM16{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM21,8),%ZMM1{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%R9,%ZMM23,8),%ZMM10{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R13,%ZMM3,8),%ZMM0{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%R13,%ZMM4,8),%ZMM3{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM1,%ZMM8,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM10,%ZMM11,%ZMM8	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM0,%ZMM6,%ZMM1	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM3,%ZMM6,%ZMM11	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VBROADCASTSD 0x3f83e(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VADDPD %ZMM31,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM6,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM31,%ZMM8,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM4,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM3,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM10,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM16,%ZMM3	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM17,%ZMM10	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VMOVAPD %ZMM5,0x300(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VBROADCASTSD 0x3f7fa(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMULLQ %ZMM27,%ZMM12,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBLENDMQ %ZMM25,%ZMM29,%ZMM15{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM25,%ZMM29,%ZMM14{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM4,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM14,%ZMM18	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM11,8),%ZMM4{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM10,8),%ZMM11{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMULLQ %ZMM27,%ZMM15,%ZMM10	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM27,%ZMM13,%ZMM1	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM24,8),%ZMM5{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM11,%ZMM5,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM18,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM10,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM11,8),%ZMM10{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM19,8),%ZMM11{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM5,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM1,8),%ZMM6{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM6,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM11,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VSUBPD %ZMM4,%ZMM6,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM10,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VBLENDMPD 0x3f7a2(%RIP),%ZMM31,%ZMM19{%K2}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVAPD %ZMM19,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM3,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD 0x3f78a(%RIP),%ZMM31,%ZMM18{%K3}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVAPD %ZMM18,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM10,%ZMM4,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM19,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD %ZMM11,%ZMM20,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM18,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMULPD 0x2c0(%RSP),%ZMM10,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM0,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM11,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x300(%RSP),%ZMM4,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM31,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x3f762(%RIP),%ZMM19,%ZMM19	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM31,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x180(%RSP),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMULPD 0x3f74a(%RIP),%ZMM18,%ZMM18	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM10,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM3,%ZMM19,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM11,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMULPD 0x1c0(%RSP),%ZMM8,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x200(%RSP),%ZMM9,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%ZMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMINPD %ZMM4,%ZMM18,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM19,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMULLQ %ZMM30,%ZMM13,%ZMM13	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM10,%ZMM6{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM3,%ZMM5{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM12,%ZMM12	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM17,%ZMM17	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM16,%ZMM16	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VMULPD (%R8,%RDX,1),%ZMM6,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x40(%R8,%RDX,1),%ZMM5,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM15,%ZMM15	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM30,%ZMM14,%ZMM14	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM12,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM5,0x40(%RDI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM1,8),%ZMM4{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM24,8),%ZMM8{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM7,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM16,%ZMM24	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM23,8),%ZMM10{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM7,%ZMM17,%ZMM23	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM14,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM15,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R9,%ZMM21,8),%ZMM9{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM1,8),%ZMM21{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RCX,%ZMM3,8),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM23,8),%ZMM1{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RCX,%ZMM24,8),%ZMM11{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM1,%ZMM21,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VSUBPD %ZMM11,%ZMM13,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM7,8),%ZMM12{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM2,8),%ZMM11{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM13,%ZMM11,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM21,%ZMM12,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM1,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM3,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM2,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x2,%ZMM26,%ZMM7,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM28,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM20,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x2c0(%RSP),%ZMM2,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM8,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM20,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x300(%RSP),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMINPD %ZMM7,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM2,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD 0x3f56a(%RIP),%ZMM31,%ZMM14{%K4}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMULPD 0x3f5a0(%RIP),%ZMM0,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMULPD 0x3f596(%RIP),%ZMM1,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VBLENDMPD 0x3f54c(%RIP),%ZMM31,%ZMM18{%K5}	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM15,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM26,%ZMM12,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM11,%ZMM0,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM3,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM6,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM7,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM28,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM4,%ZMM15,%ZMM9	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VDIVPD %ZMM8,%ZMM12,%ZMM10	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM9,%ZMM31,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM31,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM11,%ZMM21{%K6}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM7,%ZMM13{%K7}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM21,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM13,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM19,(%RSI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM6,0x40(%RSI,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42fce0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code