OV - exec - Loop 212

	Loop Id: 212	Module: exec	Source: advec_cell.cpp:71-110 [...]	Coverage: 3.46%

0x42ede8 VMOVDQA32	%ZMM27,%ZMM10

0x42edee VMOVUPD	(%R12,%RAX,1),%ZMM26    [3]

0x42edf5 VPADDD	0x140(%RSP),%ZMM10,%ZMM14    [10]

0x42edfd VMOVUPD	0x40(%R12,%RAX,1),%ZMM12    [3]

0x42ee05 VPADDD	0x408f1(%RIP),%ZMM10,%ZMM11    [8]

0x42ee0f VCMPPD	$0xe,%ZMM8,%ZMM26,%K3

0x42ee16 VPMINSD	0xc0(%RSP),%ZMM14,%ZMM0    [10]

0x42ee1e VCMPPD	$0xe,%ZMM8,%ZMM12,%K2

0x42ee25 VPMOVSXDQ	%YMM10,%ZMM4

0x42ee2b VEXTRACTI32X8	$0x1,%ZMM11,%YMM1

0x42ee32 VEXTRACTI32X8	$0x1,%ZMM10,%YMM6

0x42ee39 VPMOVSXDQ	%YMM0,%ZMM14

0x42ee3f VMOVDQA64	%ZMM4,%ZMM18

0x42ee45 VPMOVSXDQ	%YMM11,%ZMM18{%K3}

0x42ee4b VPMOVSXDQ	%YMM6,%ZMM13

0x42ee51 VMOVDQA	%YMM11,%YMM2

0x42ee55 VPMOVSXDQ	%YMM11,%ZMM7

0x42ee5b VPMOVSXDQ	%YMM1,%ZMM21

0x42ee61 VMOVDQA64	%ZMM14,%ZMM11

0x42ee67 VPADDD	0x180(%RSP),%ZMM10,%ZMM15    [10]

0x42ee6f VMOVDQA64	%ZMM13,%ZMM21{%K2}

0x42ee75 VPMOVSXDQ	%YMM2,%ZMM11{%K3}

0x42ee7b VEXTRACTI32X8	$0x1,%ZMM0,%YMM3

0x42ee82 VANDPD	%ZMM5,%ZMM26,%ZMM2

0x42ee88 VMOVDQA64	%ZMM13,%ZMM17

0x42ee8e KMOVB	%K1,%K4

0x42ee92 VGATHERQPD	(%RDI,%ZMM18,8),%ZMM13{%K4}    [7]

0x42ee99 VPMOVSXDQ	%YMM1,%ZMM17{%K2}

0x42ee9f VDIVPD	%ZMM13,%ZMM2,%ZMM10

0x42eea5 VPMOVSXDQ	%YMM3,%ZMM0

0x42eeab VADDPD	%ZMM9,%ZMM10,%ZMM3

0x42eeb1 VMOVUPD	(%RBX,%RAX,1),%ZMM16    [4]

0x42eeb8 VPBLENDMQ	%ZMM4,%ZMM7,%ZMM22{%K3}

0x42eebe VPMOVSXDQ	%YMM15,%ZMM14{%K3}

0x42eec4 VEXTRACTI32X8	$0x1,%ZMM15,%YMM4

0x42eecb VMOVDQA64	%ZMM0,%ZMM6

0x42eed1 VANDPD	%ZMM5,%ZMM12,%ZMM7

0x42eed7 KMOVB	%K1,%K5

0x42eedb VGATHERQPD	(%RDI,%ZMM17,8),%ZMM15{%K5}    [7]

0x42eee2 VPMOVSXDQ	%YMM4,%ZMM0{%K2}

0x42eee8 VPMOVSXDQ	%YMM1,%ZMM6{%K2}

0x42eeee VDIVPD	%ZMM15,%ZMM7,%ZMM7

0x42eef4 KMOVB	%K1,%K6

0x42eef8 VADDPD	%ZMM9,%ZMM7,%ZMM4

0x42eefe VGATHERQPD	(%RSI,%ZMM11,8),%ZMM1{%K6}    [5]

0x42ef05 VMOVUPD	0x40(%RBX,%RAX,1),%ZMM11    [4]

0x42ef0d VDIVPD	%ZMM1,%ZMM16,%ZMM19

0x42ef13 KMOVB	%K1,%K7

0x42ef17 VMULPD	%ZMM3,%ZMM19,%ZMM16

0x42ef1d VGATHERQPD	(%RSI,%ZMM6,8),%ZMM12{%K7}    [5]

0x42ef24 KMOVB	%K1,%K3

0x42ef28 KMOVB	%K1,%K4

0x42ef2c VGATHERQPD	(%RDX,%ZMM18,8),%ZMM3{%K3}    [6]

0x42ef33 VGATHERQPD	(%RDX,%ZMM14,8),%ZMM13{%K4}    [6]

0x42ef3a VDIVPD	%ZMM12,%ZMM11,%ZMM6

0x42ef40 KMOVB	%K1,%K2

0x42ef44 VSUBPD	%ZMM13,%ZMM3,%ZMM11

0x42ef4a VGATHERQPD	(%RDX,%ZMM17,8),%ZMM2{%K2}    [6]

0x42ef51 KMOVB	%K1,%K5

0x42ef55 KMOVB	%K1,%K7

0x42ef59 VGATHERQPD	(%RDX,%ZMM0,8),%ZMM15{%K5}    [6]

0x42ef60 VGATHERQPD	(%RDX,%ZMM21,8),%ZMM13{%K7}    [6]

0x42ef67 VMULPD	%ZMM4,%ZMM6,%ZMM1

0x42ef6d VSUBPD	%ZMM2,%ZMM13,%ZMM13

0x42ef73 VSUBPD	%ZMM15,%ZMM2,%ZMM6

0x42ef79 VSUBPD	%ZMM7,%ZMM25,%ZMM20

0x42ef7f KMOVB	%K1,%K6

0x42ef83 VGATHERQPD	(%RDX,%ZMM22,8),%ZMM12{%K6}    [6]

0x42ef8a VSUBPD	%ZMM3,%ZMM12,%ZMM15

0x42ef90 VMULPD	%ZMM13,%ZMM6,%ZMM28

0x42ef96 VSUBPD	%ZMM10,%ZMM25,%ZMM4

0x42ef9c VCMPPD	$0x2,%ZMM8,%ZMM13,%K2

0x42efa3 VANDPD	%ZMM5,%ZMM13,%ZMM13

0x42efa9 VMULPD	%ZMM13,%ZMM20,%ZMM19

0x42efaf VANDPD	%ZMM5,%ZMM15,%ZMM12

0x42efb5 VMULPD	%ZMM15,%ZMM11,%ZMM30

0x42efbb VCMPPD	$0x2,%ZMM8,%ZMM15,%K3

0x42efc2 VMULPD	%ZMM12,%ZMM4,%ZMM15

0x42efc8 VANDPD	%ZMM5,%ZMM6,%ZMM6

0x42efce VFMADD231PD	%ZMM6,%ZMM1,%ZMM19

0x42efd4 VANDPD	%ZMM5,%ZMM11,%ZMM11

0x42efda VMINPD	%ZMM13,%ZMM6,%ZMM6

0x42efe0 VFMADD231PD	%ZMM11,%ZMM16,%ZMM15

0x42efe6 VSUBPD	%ZMM7,%ZMM9,%ZMM7

0x42efec VMULPD	%ZMM23,%ZMM19,%ZMM19

0x42eff2 VSUBPD	%ZMM10,%ZMM9,%ZMM10

0x42eff8 VBLENDMPD	%ZMM24,%ZMM9,%ZMM29{%K3}

0x42effe VMULPD	%ZMM23,%ZMM15,%ZMM15

0x42f004 VBLENDMPD	%ZMM24,%ZMM9,%ZMM31{%K2}

0x42f00a VMINPD	%ZMM12,%ZMM11,%ZMM11

0x42f010 VMINPD	%ZMM6,%ZMM19,%ZMM13

0x42f016 VMULPD	%ZMM31,%ZMM7,%ZMM6

0x42f01c VMULPD	%ZMM29,%ZMM10,%ZMM7

0x42f022 VMINPD	%ZMM11,%ZMM15,%ZMM12

0x42f028 VCMPPD	$0xe,%ZMM8,%ZMM30,%K4

0x42f02f VCMPPD	$0xe,%ZMM8,%ZMM28,%K5

0x42f036 KMOVB	%K1,%K7

0x42f03a VFMADD231PD	%ZMM7,%ZMM12,%ZMM3{%K4}

0x42f040 VFMADD231PD	%ZMM6,%ZMM13,%ZMM2{%K5}

0x42f046 KMOVB	%K1,%K2

0x42f04a KMOVB	%K1,%K5

0x42f04e KMOVB	%K1,%K3

0x42f052 VMULPD	%ZMM3,%ZMM26,%ZMM3

0x42f058 VMULPD	0x40(%R12,%RAX,1),%ZMM2,%ZMM2    [3]

0x42f060 KMOVB	%K1,%K4

0x42f064 KMOVB	%K1,%K6

0x42f068 VPADDD	0x1c0(%RSP),%ZMM27,%ZMM27    [10]

0x42f070 VMOVUPD	%ZMM3,(%R11,%RAX,1)    [2]

0x42f077 VMOVUPD	%ZMM2,0x40(%R11,%RAX,1)    [2]

0x42f07f VGATHERQPD	(%RCX,%ZMM17,8),%ZMM13{%K5}    [9]

0x42f086 VGATHERQPD	(%RDI,%ZMM17,8),%ZMM11{%K2}    [7]

0x42f08d VGATHERQPD	(%RDX,%ZMM17,8),%ZMM7{%K7}    [6]

0x42f094 KMOVB	%K1,%K2

0x42f098 VGATHERQPD	(%RCX,%ZMM21,8),%ZMM17{%K2}    [9]

0x42f09f VGATHERQPD	(%RDI,%ZMM18,8),%ZMM12{%K3}    [7]

0x42f0a6 KMOVB	%K1,%K3

0x42f0aa VGATHERQPD	(%RCX,%ZMM22,8),%ZMM26{%K3}    [9]

0x42f0b1 VSUBPD	%ZMM13,%ZMM17,%ZMM22

0x42f0b7 VGATHERQPD	(%RCX,%ZMM18,8),%ZMM6{%K4}    [9]

0x42f0be VGATHERQPD	(%RDX,%ZMM18,8),%ZMM10{%K6}    [6]

0x42f0c5 VANDPD	%ZMM5,%ZMM22,%ZMM28

0x42f0cb VSUBPD	%ZMM6,%ZMM26,%ZMM18

0x42f0d1 KMOVB	%K1,%K6

0x42f0d5 KMOVB	%K1,%K7

0x42f0d9 VGATHERQPD	(%RCX,%ZMM14,8),%ZMM15{%K6}    [9]

0x42f0e0 VMULPD	%ZMM28,%ZMM20,%ZMM20

0x42f0e6 VGATHERQPD	(%RCX,%ZMM0,8),%ZMM14{%K7}    [9]

0x42f0ed VSUBPD	%ZMM14,%ZMM13,%ZMM14

0x42f0f3 VANDPD	%ZMM5,%ZMM18,%ZMM30

0x42f0f9 VMULPD	%ZMM30,%ZMM4,%ZMM4

0x42f0ff VSUBPD	%ZMM15,%ZMM6,%ZMM0

0x42f105 VMULPD	%ZMM22,%ZMM14,%ZMM15

0x42f10b VANDPD	%ZMM5,%ZMM14,%ZMM14

0x42f111 VFMADD132PD	%ZMM14,%ZMM20,%ZMM1

0x42f117 VMULPD	%ZMM18,%ZMM0,%ZMM31

0x42f11d VANDPD	%ZMM5,%ZMM0,%ZMM0

0x42f123 VFMADD231PD	%ZMM0,%ZMM16,%ZMM4

0x42f129 VMINPD	%ZMM28,%ZMM14,%ZMM14

0x42f12f VMULPD	%ZMM23,%ZMM1,%ZMM1

0x42f135 VCMPPD	$0x2,%ZMM8,%ZMM22,%K5

0x42f13c VMINPD	%ZMM30,%ZMM0,%ZMM0

0x42f142 VMULPD	%ZMM23,%ZMM4,%ZMM4

0x42f148 VCMPPD	$0x2,%ZMM8,%ZMM18,%K4

0x42f14f VMINPD	%ZMM14,%ZMM1,%ZMM1

0x42f155 VBLENDMPD	%ZMM24,%ZMM9,%ZMM21{%K5}

0x42f15b VMULPD	%ZMM12,%ZMM10,%ZMM10

0x42f161 VMULPD	%ZMM21,%ZMM1,%ZMM14

0x42f167 VMINPD	%ZMM0,%ZMM4,%ZMM1

0x42f16d VBLENDMPD	%ZMM24,%ZMM9,%ZMM29{%K4}

0x42f173 VMULPD	%ZMM11,%ZMM7,%ZMM7

0x42f179 VMULPD	%ZMM29,%ZMM1,%ZMM4

0x42f17f VANDPD	%ZMM5,%ZMM3,%ZMM0

0x42f185 VCMPPD	$0xe,%ZMM8,%ZMM31,%K6

0x42f18c VDIVPD	%ZMM10,%ZMM0,%ZMM12

0x42f192 VSUBPD	%ZMM12,%ZMM9,%ZMM1

0x42f198 VCMPPD	$0xe,%ZMM8,%ZMM15,%K7

0x42f19f VANDPD	%ZMM5,%ZMM2,%ZMM15

0x42f1a5 VFMADD231PD	%ZMM1,%ZMM4,%ZMM6{%K6}

0x42f1ab VDIVPD	%ZMM7,%ZMM15,%ZMM11

0x42f1b1 VSUBPD	%ZMM11,%ZMM9,%ZMM4

0x42f1b7 VFMADD231PD	%ZMM4,%ZMM14,%ZMM13{%K7}

0x42f1bd VMULPD	%ZMM6,%ZMM3,%ZMM3

0x42f1c3 VMULPD	%ZMM13,%ZMM2,%ZMM2

0x42f1c9 VMOVUPD	%ZMM3,(%R10,%RAX,1)    [1]

0x42f1d0 VMOVUPD	%ZMM2,0x40(%R10,%RAX,1)    [1]

0x42f1d8 SUB	$-0x80,%RAX

0x42f1dc CMP	%R15,%RAX

0x42f1df JNE	42ede8

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 71 - 110

--------------------------------------------------------------------------------

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

[...]

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

Coverage (%)	Name	Source Location	Module
○97.67	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.33	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	advec_cell.cpp:71-72,advec_cell.cpp:79-110,stl_algobase.h:238-238
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	101.00
CQA cycles if no scalar integer	96.00
CQA cycles if FP arith vectorized	101.00
CQA cycles if fully vectorized	100.00
Front-end cycles	43.33
P0 cycles	101.00
P1 cycles	24.00
P2 cycles	56.67
P3 cycles	56.67
P4 cycles	2.00
P5 cycles	101.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	56.67
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	168.00
Nb uops	259.00
Nb loads	30.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	4.91
Nb FLOP add-sub	128.00
Nb FLOP mul	192.00
Nb FLOP fma	64.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.54
Bytes prefetched	0.00
Bytes loaded	1920.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	94.14
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.24

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	advec_cell.cpp:71-72,advec_cell.cpp:79-110,stl_algobase.h:238-238
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	101.00
CQA cycles if no scalar integer	96.00
CQA cycles if FP arith vectorized	101.00
CQA cycles if fully vectorized	100.00
Front-end cycles	43.33
P0 cycles	101.00
P1 cycles	24.00
P2 cycles	56.67
P3 cycles	56.67
P4 cycles	2.00
P5 cycles	101.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	56.67
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	168.00
Nb uops	259.00
Nb loads	30.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	4.91
Nb FLOP add-sub	128.00
Nb FLOP mul	192.00
Nb FLOP fma	64.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.54
Bytes prefetched	0.00
Bytes loaded	1920.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	94.14
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.24

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-72,79-110
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 101.00 to 96.00 cycles (1.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using 94% register length (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 101.00 to 100.00 cycles (1.01x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 101.00 to 92.00 cycles (1.10x speedup).

Special instructions executing on a single port

1.05x slowdown from special instructions executing on a single port.

Details

KMOVB: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
VCMPPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:84
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:105
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:105
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:103
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:103
VEXTRACTI32X8: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
VPMINSD: 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238
VPMOVSXDQ: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:72
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

192: addition or subtraction (64 inside FMA instructions)
256: multiply (64 inside FMA instructions)
48: divide

The binary loop is loading 1920 bytes (240 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	168
nb uops	259
loop length	1021
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	32
nb stack references	4
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	43.33 cycles
front end	43.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	101.00	0.00	56.67	56.67	2.00	101.00	1.00	2.00	2.00	2.00	0.00	56.67
cycles	101.00	24.00	56.67	56.67	2.00	101.00	1.00	2.00	2.00	2.00	0.00	56.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	43.33
Dispatch	101.00
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	101.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	70%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 101.00 cycles. At this rate:

9% of peak load performance is reached (19.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ede8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQA32 %ZMM27,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDD 0x140(%RSP),%ZMM10,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPD 0x40(%R12,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDD 0x408f1(%RIP),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM26,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMINSD 0xc0(%RSP),%ZMM14,%ZMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	1	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM12,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMOVSXDQ %YMM10,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM11,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM10,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM0,%ZMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM4,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPMOVSXDQ %YMM11,%ZMM18{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM6,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA %YMM11,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM11,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM14,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPADDD 0x180(%RSP),%ZMM10,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVDQA64 %ZMM13,%ZMM21{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM11{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VANDPD %ZMM5,%ZMM26,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 %ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDI,%ZMM18,8),%ZMM13{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMOVSXDQ %YMM1,%ZMM17{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VDIVPD %ZMM13,%ZMM2,%ZMM10	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM3,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM9,%ZMM10,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM4,%ZMM7,%ZMM22{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM15,%ZMM14{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM15,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VANDPD %ZMM5,%ZMM12,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDI,%ZMM17,8),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMOVSXDQ %YMM4,%ZMM0{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM6{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VDIVPD %ZMM15,%ZMM7,%ZMM7	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VADDPD %ZMM9,%ZMM7,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RSI,%ZMM11,8),%ZMM1{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VDIVPD %ZMM1,%ZMM16,%ZMM19	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %ZMM3,%ZMM19,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VGATHERQPD (%RSI,%ZMM6,8),%ZMM12{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM18,8),%ZMM3{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM14,8),%ZMM13{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM12,%ZMM11,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VSUBPD %ZMM13,%ZMM3,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RDX,%ZMM17,8),%ZMM2{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM0,8),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM21,8),%ZMM13{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM4,%ZMM6,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM2,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM25,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM22,8),%ZMM12{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM3,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM25,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM13,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM5,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM20,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM15,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM11,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM15,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMULPD %ZMM12,%ZMM4,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM1,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM13,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM9,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM29{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM15,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM31{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM12,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM6,%ZMM19,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM31,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM29,%ZMM10,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM11,%ZMM15,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM30,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM28,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD231PD %ZMM7,%ZMM12,%ZMM3{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM13,%ZMM2{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %ZMM3,%ZMM26,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x40(%R12,%RAX,1),%ZMM2,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDD 0x1c0(%RSP),%ZMM27,%ZMM27	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPD %ZMM3,(%R11,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,0x40(%R11,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VGATHERQPD (%RCX,%ZMM17,8),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDI,%ZMM17,8),%ZMM11{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM17,8),%ZMM7{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM21,8),%ZMM17{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDI,%ZMM18,8),%ZMM12{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM22,8),%ZMM26{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM13,%ZMM17,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM18,8),%ZMM6{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM18,8),%ZMM10{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM5,%ZMM22,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM26,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM14,8),%ZMM15{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM28,%ZMM20,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM0,8),%ZMM14{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM14,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM18,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM6,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM14,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD132PD %ZMM14,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM0,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM16,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM28,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM22,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM30,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM18,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM14,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM21{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM4,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM29{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM29,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM3,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM31,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM10,%ZMM0,%ZMM12	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM12,%ZMM9,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM15,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM5,%ZMM2,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM4,%ZMM6{%K6}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM7,%ZMM15,%ZMM11	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM11,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM14,%ZMM13{%K7}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%R10,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,0x40(%R10,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42ede8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x348>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-72,79-110
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 101.00 to 92.00 cycles (1.10x speedup).

Special instructions executing on a single port

1.05x slowdown from special instructions executing on a single port.

Details

KMOVB: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
VCMPPD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:84
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:90
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:105
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:105
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:103
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:103
VEXTRACTI32X8: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
VPMINSD: 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:238
VPMOVSXDQ: 12 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:72
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 20 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:83
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:86
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:100
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:98
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:99

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

192: addition or subtraction (64 inside FMA instructions)
256: multiply (64 inside FMA instructions)
48: divide

The binary loop is loading 1920 bytes (240 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	168
nb uops	259
loop length	1021
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	32
nb stack references	4
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	43.33 cycles
front end	43.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	101.00	0.00	56.67	56.67	2.00	101.00	1.00	2.00	2.00	2.00	0.00	56.67
cycles	101.00	24.00	56.67	56.67	2.00	101.00	1.00	2.00	2.00	2.00	0.00	56.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	43.33
Dispatch	101.00
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	101.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	70%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 101.00 cycles. At this rate:

9% of peak load performance is reached (19.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ede8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQA32 %ZMM27,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDD 0x140(%RSP),%ZMM10,%ZMM14	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPD 0x40(%R12,%RAX,1),%ZMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPADDD 0x408f1(%RIP),%ZMM10,%ZMM11	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM26,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMINSD 0xc0(%RSP),%ZMM14,%ZMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	1	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM12,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPMOVSXDQ %YMM10,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM11,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM10,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM0,%ZMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM4,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPMOVSXDQ %YMM11,%ZMM18{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM6,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA %YMM11,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPMOVSXDQ %YMM11,%ZMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM21	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM14,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPADDD 0x180(%RSP),%ZMM10,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVDQA64 %ZMM13,%ZMM21{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPMOVSXDQ %YMM2,%ZMM11{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM0,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VANDPD %ZMM5,%ZMM26,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVDQA64 %ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDI,%ZMM18,8),%ZMM13{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMOVSXDQ %YMM1,%ZMM17{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VDIVPD %ZMM13,%ZMM2,%ZMM10	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VPMOVSXDQ %YMM3,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM9,%ZMM10,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPBLENDMQ %ZMM4,%ZMM7,%ZMM22{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM15,%ZMM14{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM15,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMOVDQA64 %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VANDPD %ZMM5,%ZMM12,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDI,%ZMM17,8),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPMOVSXDQ %YMM4,%ZMM0{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM6{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VDIVPD %ZMM15,%ZMM7,%ZMM7	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VADDPD %ZMM9,%ZMM7,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RSI,%ZMM11,8),%ZMM1{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VDIVPD %ZMM1,%ZMM16,%ZMM19	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %ZMM3,%ZMM19,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VGATHERQPD (%RSI,%ZMM6,8),%ZMM12{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM18,8),%ZMM3{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM14,8),%ZMM13{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VDIVPD %ZMM12,%ZMM11,%ZMM6	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VSUBPD %ZMM13,%ZMM3,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RDX,%ZMM17,8),%ZMM2{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM0,8),%ZMM15{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM21,8),%ZMM13{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM4,%ZMM6,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM2,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM25,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RDX,%ZMM22,8),%ZMM12{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM3,%ZMM12,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM25,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM13,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM5,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM20,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM15,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM11,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM15,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMULPD %ZMM12,%ZMM4,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM1,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM13,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM9,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM19,%ZMM19	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM9,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM29{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM15,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM31{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMINPD %ZMM12,%ZMM11,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM6,%ZMM19,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM31,%ZMM7,%ZMM6	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM29,%ZMM10,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM11,%ZMM15,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM30,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM28,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VFMADD231PD %ZMM7,%ZMM12,%ZMM3{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM13,%ZMM2{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMULPD %ZMM3,%ZMM26,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD 0x40(%R12,%RAX,1),%ZMM2,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDD 0x1c0(%RSP),%ZMM27,%ZMM27	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPD %ZMM3,(%R11,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,0x40(%R11,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VGATHERQPD (%RCX,%ZMM17,8),%ZMM13{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDI,%ZMM17,8),%ZMM11{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM17,8),%ZMM7{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM21,8),%ZMM17{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDI,%ZMM18,8),%ZMM12{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM22,8),%ZMM26{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM13,%ZMM17,%ZMM22	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM18,8),%ZMM6{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RDX,%ZMM18,8),%ZMM10{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VANDPD %ZMM5,%ZMM22,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VSUBPD %ZMM6,%ZMM26,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RCX,%ZMM14,8),%ZMM15{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM28,%ZMM20,%ZMM20	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VGATHERQPD (%RCX,%ZMM0,8),%ZMM14{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM14,%ZMM13,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM18,%ZMM30	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM6,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM14,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD132PD %ZMM14,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM0,%ZMM31	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM16,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM28,%ZMM14,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM22,%K5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM30,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0x2,%ZMM8,%ZMM18,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMINPD %ZMM14,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM21{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM10,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM21,%ZMM1,%ZMM14	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM0,%ZMM4,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBLENDMPD %ZMM24,%ZMM9,%ZMM29{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM29,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPD %ZMM5,%ZMM3,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM31,%K6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM10,%ZMM0,%ZMM12	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM12,%ZMM9,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM15,%K7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM5,%ZMM2,%ZMM15	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM4,%ZMM6{%K6}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM7,%ZMM15,%ZMM11	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM11,%ZMM9,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM14,%ZMM13{%K7}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%R10,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD %ZMM2,0x40(%R10,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 42ede8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x348>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code