OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:62-66 [...]	Coverage (incl. loops): 2.53% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 62 - 66

--------------------------------------------------------------------------------

62: #pragma omp parallel for simd collapse(2)

63:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x431c70 PUSH	%RBP

0x431c71 MOV	%RSP,%RBP

0x431c74 PUSH	%R15

0x431c76 PUSH	%R14

0x431c78 PUSH	%R13

0x431c7a PUSH	%R12

0x431c7c PUSH	%RBX

0x431c7d AND	$-0x40,%RSP

0x431c81 ADD	$-0x80,%RSP

0x431c85 MOV	0x28(%RDI),%EAX

0x431c88 MOV	0x2c(%RDI),%ECX

0x431c8b MOV	0x20(%RDI),%EDX

0x431c8e ADD	$0x4,%ECX

0x431c91 DEC	%EDX

0x431c93 LEA	-0x1(%RAX),%R12D

0x431c97 MOV	%ECX,0x3c(%RSP)

0x431c9b MOV	%EDX,0x38(%RSP)

0x431c9f MOV	0x24(%RDI),%ESI

0x431ca2 CMP	%ECX,%R12D

0x431ca5 JGE	432283

0x431cab MOV	%ECX,%EBX

0x431cad LEA	0x4(%RSI),%R15D

0x431cb1 SUB	%R12D,%EBX

0x431cb4 CMP	%R15D,%EDX

0x431cb7 JGE	432283

0x431cbd MOV	%RDI,%R14

0x431cc0 MOV	%R15D,%EDI

0x431cc3 SUB	%EDX,%EDI

0x431cc5 MOV	%EDI,0x70(%RSP)

0x431cc9 CALL	404630 <omp_get_num_threads@plt>

0x431cce MOV	%EAX,%R13D

0x431cd1 CALL	404520 <omp_get_thread_num@plt>

0x431cd6 MOV	%EAX,%R8D

0x431cd9 MOV	0x70(%RSP),%EAX

0x431cdd XOR	%EDX,%EDX

0x431cdf IMUL	%EBX,%EAX

0x431ce2 DIV	%R13D

0x431ce5 MOV	%EAX,%ESI

0x431ce7 CMP	%EDX,%R8D

0x431cea JB	4322a4

0x431cf0 IMUL	%ESI,%R8D

0x431cf4 LEA	(%R8,%RDX,1),%R13D

0x431cf8 LEA	(%RSI,%R13,1),%R9D

0x431cfc MOV	%R9D,0x34(%RSP)

0x431d01 CMP	%R9D,%R13D

0x431d04 JAE	432283

0x431d0a XOR	%EDX,%EDX

0x431d0c MOV	%R13D,%EAX

0x431d0f DIVL	0x70(%RSP)

0x431d13 MOV	0x38(%RSP),%R10D

0x431d18 MOV	0x18(%R14),%RCX

0x431d1c MOV	0x8(%R14),%R11

0x431d20 MOV	0x10(%R14),%RBX

0x431d24 MOV	%RCX,0x20(%RSP)

0x431d29 MOV	%R11,0x28(%RSP)

0x431d2e MOV	%RBX,0x10(%RSP)

0x431d33 ADD	%EDX,%R10D

0x431d36 MOV	%R15D,%EDX

0x431d39 SUB	%R10D,%EDX

0x431d3c ADD	%R12D,%EAX

0x431d3f CMP	%EDX,%ESI

0x431d41 CMOVBE	%ESI,%EDX

0x431d44 MOV	(%R14),%R15

0x431d47 LEA	(%R13,%RDX,1),%R14D

0x431d4c MOV	%R10D,0x74(%RSP)

0x431d51 MOV	%R15,0x18(%RSP)

0x431d56 MOVSXD	%EAX,%RCX

0x431d59 CMP	%R14D,%R13D

0x431d5c JAE	432268

0x431d62 NOPW	(%RAX,%RAX,1)

  (220) 0x431d68 MOV	0x18(%RSP),%R9

  (220) 0x431d6d MOV	0x28(%RSP),%RSI

  (220) 0x431d72 MOV	0x20(%RSP),%RDI

  (220) 0x431d77 MOV	(%R9),%RAX

  (220) 0x431d7a MOV	0x10(%RSP),%R10

  (220) 0x431d7f LEA	0x1(%RCX),%R12

  (220) 0x431d83 MOV	0x10(%RDI),%R8

  (220) 0x431d87 MOV	0x10(%RSI),%R15

  (220) 0x431d8b MOV	(%RDI),%RDI

  (220) 0x431d8e MOV	(%RSI),%RSI

  (220) 0x431d91 MOV	%R12,0x40(%RSP)

  (220) 0x431d96 IMUL	%RAX,%R12

  (220) 0x431d9a IMUL	%RCX,%RSI

  (220) 0x431d9e IMUL	%RCX,%RDI

  (220) 0x431da2 IMUL	(%R10),%RCX

  (220) 0x431da6 MOV	0x10(%R9),%R11

  (220) 0x431daa MOV	%R12,%RBX

  (220) 0x431dad MOV	0x10(%R10),%R9

  (220) 0x431db1 MOV	%RCX,0x68(%RSP)

  (220) 0x431db6 SUB	%RAX,%RBX

  (220) 0x431db9 MOV	%RCX,%R10

  (220) 0x431dbc LEA	-0x1(%RDX),%ECX

  (220) 0x431dbf MOV	%RSI,0x48(%RSP)

  (220) 0x431dc4 MOV	%R8,0x58(%RSP)

  (220) 0x431dc9 MOV	%RDI,0x50(%RSP)

  (220) 0x431dce MOV	%RBX,0x60(%RSP)

  (220) 0x431dd3 MOV	%R9,0x78(%RSP)

  (220) 0x431dd8 CMP	$0x6,%ECX

  (220) 0x431ddb JBE	432298

  (220) 0x431de1 MOVSXD	0x74(%RSP),%RAX

  (220) 0x431de6 LEA	(%RBX,%RAX,1),%RBX

  (220) 0x431dea LEA	(%RSI,%RAX,1),%R9

  (220) 0x431dee LEA	(%R11,%RBX,8),%RSI

  (220) 0x431df2 MOV	%EDX,%EBX

  (220) 0x431df4 LEA	(%RDI,%RAX,1),%RDI

  (220) 0x431df8 LEA	(%R12,%RAX,1),%RCX

  (220) 0x431dfc SHR	$0x3,%EBX

  (220) 0x431dff ADD	%R10,%RAX

  (220) 0x431e02 MOV	0x78(%RSP),%R10

  (220) 0x431e07 SAL	$0x6,%RBX

  (220) 0x431e0b LEA	(%R8,%RDI,8),%R8

  (220) 0x431e0f LEA	(%R11,%RCX,8),%RDI

  (220) 0x431e13 LEA	(%R10,%RAX,8),%RCX

  (220) 0x431e17 LEA	-0x40(%RBX),%R10

  (220) 0x431e1b SHR	$0x6,%R10

  (220) 0x431e1f INC	%R10

  (220) 0x431e22 LEA	(%R15,%R9,8),%R9

  (220) 0x431e26 XOR	%EAX,%EAX

  (220) 0x431e28 AND	$0x7,%R10D

  (220) 0x431e2c JE	431f78

  (220) 0x431e32 CMP	$0x1,%R10

  (220) 0x431e36 JE	431f48

  (220) 0x431e3c CMP	$0x2,%R10

  (220) 0x431e40 JE	431f21

  (220) 0x431e46 CMP	$0x3,%R10

  (220) 0x431e4a JE	431efa

  (220) 0x431e50 CMP	$0x4,%R10

  (220) 0x431e54 JE	431ed3

  (220) 0x431e56 CMP	$0x5,%R10

  (220) 0x431e5a JE	431eac

  (220) 0x431e5c CMP	$0x6,%R10

  (220) 0x431e60 JE	431e85

  (220) 0x431e62 VMOVUPD	(%R9),%ZMM0

  (220) 0x431e68 MOV	$0x40,%EAX

  (220) 0x431e6d VMOVUPD	%ZMM0,(%R8)

  (220) 0x431e73 VADDPD	(%RDI),%ZMM0,%ZMM1

  (220) 0x431e79 VSUBPD	(%RSI),%ZMM1,%ZMM2

  (220) 0x431e7f VMOVUPD	%ZMM2,(%RCX)

  (220) 0x431e85 VMOVUPD	(%R9,%RAX,1),%ZMM3

  (220) 0x431e8c VMOVUPD	%ZMM3,(%R8,%RAX,1)

  (220) 0x431e93 VADDPD	(%RDI,%RAX,1),%ZMM3,%ZMM4

  (220) 0x431e9a VSUBPD	(%RSI,%RAX,1),%ZMM4,%ZMM5

  (220) 0x431ea1 VMOVUPD	%ZMM5,(%RCX,%RAX,1)

  (220) 0x431ea8 ADD	$0x40,%RAX

  (220) 0x431eac VMOVUPD	(%R9,%RAX,1),%ZMM6

  (220) 0x431eb3 VMOVUPD	%ZMM6,(%R8,%RAX,1)

  (220) 0x431eba VADDPD	(%RDI,%RAX,1),%ZMM6,%ZMM7

  (220) 0x431ec1 VSUBPD	(%RSI,%RAX,1),%ZMM7,%ZMM8

  (220) 0x431ec8 VMOVUPD	%ZMM8,(%RCX,%RAX,1)

  (220) 0x431ecf ADD	$0x40,%RAX

  (220) 0x431ed3 VMOVUPD	(%R9,%RAX,1),%ZMM9

  (220) 0x431eda VMOVUPD	%ZMM9,(%R8,%RAX,1)

  (220) 0x431ee1 VADDPD	(%RDI,%RAX,1),%ZMM9,%ZMM10

  (220) 0x431ee8 VSUBPD	(%RSI,%RAX,1),%ZMM10,%ZMM11

  (220) 0x431eef VMOVUPD	%ZMM11,(%RCX,%RAX,1)

  (220) 0x431ef6 ADD	$0x40,%RAX

  (220) 0x431efa VMOVUPD	(%R9,%RAX,1),%ZMM12

  (220) 0x431f01 VMOVUPD	%ZMM12,(%R8,%RAX,1)

  (220) 0x431f08 VADDPD	(%RDI,%RAX,1),%ZMM12,%ZMM13

  (220) 0x431f0f VSUBPD	(%RSI,%RAX,1),%ZMM13,%ZMM14

  (220) 0x431f16 VMOVUPD	%ZMM14,(%RCX,%RAX,1)

  (220) 0x431f1d ADD	$0x40,%RAX

  (220) 0x431f21 VMOVUPD	(%R9,%RAX,1),%ZMM15

  (220) 0x431f28 VMOVUPD	%ZMM15,(%R8,%RAX,1)

  (220) 0x431f2f VADDPD	(%RDI,%RAX,1),%ZMM15,%ZMM0

  (220) 0x431f36 VSUBPD	(%RSI,%RAX,1),%ZMM0,%ZMM1

  (220) 0x431f3d VMOVUPD	%ZMM1,(%RCX,%RAX,1)

  (220) 0x431f44 ADD	$0x40,%RAX

  (220) 0x431f48 VMOVUPD	(%R9,%RAX,1),%ZMM2

  (220) 0x431f4f VMOVUPD	%ZMM2,(%R8,%RAX,1)

  (220) 0x431f56 VADDPD	(%RDI,%RAX,1),%ZMM2,%ZMM3

  (220) 0x431f5d VSUBPD	(%RSI,%RAX,1),%ZMM3,%ZMM4

  (220) 0x431f64 VMOVUPD	%ZMM4,(%RCX,%RAX,1)

  (220) 0x431f6b ADD	$0x40,%RAX

  (220) 0x431f6f CMP	%RBX,%RAX

  (220) 0x431f72 JE	4320c2

    (221) 0x431f78 VMOVUPD	(%R9,%RAX,1),%ZMM5

    (221) 0x431f7f VMOVUPD	%ZMM5,(%R8,%RAX,1)

    (221) 0x431f86 VADDPD	(%RDI,%RAX,1),%ZMM5,%ZMM6

    (221) 0x431f8d VSUBPD	(%RSI,%RAX,1),%ZMM6,%ZMM7

    (221) 0x431f94 VMOVUPD	%ZMM7,(%RCX,%RAX,1)

    (221) 0x431f9b VMOVUPD	0x40(%R9,%RAX,1),%ZMM8

    (221) 0x431fa3 VMOVUPD	%ZMM8,0x40(%R8,%RAX,1)

    (221) 0x431fab VADDPD	0x40(%RDI,%RAX,1),%ZMM8,%ZMM9

    (221) 0x431fb3 VSUBPD	0x40(%RSI,%RAX,1),%ZMM9,%ZMM10

    (221) 0x431fbb VMOVUPD	%ZMM10,0x40(%RCX,%RAX,1)

    (221) 0x431fc3 VMOVUPD	0x80(%R9,%RAX,1),%ZMM11

    (221) 0x431fcb VMOVUPD	%ZMM11,0x80(%R8,%RAX,1)

    (221) 0x431fd3 VADDPD	0x80(%RDI,%RAX,1),%ZMM11,%ZMM12

    (221) 0x431fdb VSUBPD	0x80(%RSI,%RAX,1),%ZMM12,%ZMM13

    (221) 0x431fe3 VMOVUPD	%ZMM13,0x80(%RCX,%RAX,1)

    (221) 0x431feb VMOVUPD	0xc0(%R9,%RAX,1),%ZMM14

    (221) 0x431ff3 VMOVUPD	%ZMM14,0xc0(%R8,%RAX,1)

    (221) 0x431ffb VADDPD	0xc0(%RDI,%RAX,1),%ZMM14,%ZMM15

    (221) 0x432003 VSUBPD	0xc0(%RSI,%RAX,1),%ZMM15,%ZMM0

    (221) 0x43200b VMOVUPD	%ZMM0,0xc0(%RCX,%RAX,1)

    (221) 0x432013 VMOVUPD	0x100(%R9,%RAX,1),%ZMM1

    (221) 0x43201b VMOVUPD	%ZMM1,0x100(%R8,%RAX,1)

    (221) 0x432023 VADDPD	0x100(%RDI,%RAX,1),%ZMM1,%ZMM2

    (221) 0x43202b VSUBPD	0x100(%RSI,%RAX,1),%ZMM2,%ZMM3

    (221) 0x432033 VMOVUPD	%ZMM3,0x100(%RCX,%RAX,1)

    (221) 0x43203b VMOVUPD	0x140(%R9,%RAX,1),%ZMM4

    (221) 0x432043 VMOVUPD	%ZMM4,0x140(%R8,%RAX,1)

    (221) 0x43204b VADDPD	0x140(%RDI,%RAX,1),%ZMM4,%ZMM5

    (221) 0x432053 VSUBPD	0x140(%RSI,%RAX,1),%ZMM5,%ZMM6

    (221) 0x43205b VMOVUPD	%ZMM6,0x140(%RCX,%RAX,1)

    (221) 0x432063 VMOVUPD	0x180(%R9,%RAX,1),%ZMM7

    (221) 0x43206b VMOVUPD	%ZMM7,0x180(%R8,%RAX,1)

    (221) 0x432073 VADDPD	0x180(%RDI,%RAX,1),%ZMM7,%ZMM8

    (221) 0x43207b VSUBPD	0x180(%RSI,%RAX,1),%ZMM8,%ZMM9

    (221) 0x432083 VMOVUPD	%ZMM9,0x180(%RCX,%RAX,1)

    (221) 0x43208b VMOVUPD	0x1c0(%R9,%RAX,1),%ZMM10

    (221) 0x432093 VMOVUPD	%ZMM10,0x1c0(%R8,%RAX,1)

    (221) 0x43209b VADDPD	0x1c0(%RDI,%RAX,1),%ZMM10,%ZMM11

    (221) 0x4320a3 VSUBPD	0x1c0(%RSI,%RAX,1),%ZMM11,%ZMM12

    (221) 0x4320ab VMOVUPD	%ZMM12,0x1c0(%RCX,%RAX,1)

    (221) 0x4320b3 ADD	$0x200,%RAX

    (221) 0x4320b9 CMP	%RBX,%RAX

    (221) 0x4320bc JNE	431f78

  (220) 0x4320c2 MOV	0x74(%RSP),%R9D

  (220) 0x4320c7 MOV	%EDX,%R8D

  (220) 0x4320ca AND	$-0x8,%R8D

  (220) 0x4320ce LEA	(%R8,%R9,1),%ESI

  (220) 0x4320d2 ADD	%R8D,%R13D

  (220) 0x4320d5 TEST	$0x7,%DL

  (220) 0x4320d8 JE	432232

  (220) 0x4320de SUB	%R8D,%EDX

  (220) 0x4320e1 LEA	-0x1(%RDX),%EDI

  (220) 0x4320e4 CMP	$0x2,%EDI

  (220) 0x4320e7 JBE	43215e

  (220) 0x4320e9 MOVSXD	0x74(%RSP),%RCX

  (220) 0x4320ee MOV	0x48(%RSP),%RBX

  (220) 0x4320f3 MOV	0x50(%RSP),%RAX

  (220) 0x4320f8 LEA	(%RBX,%RCX,1),%R10

  (220) 0x4320fc ADD	%R8,%R10

  (220) 0x4320ff VMOVUPD	(%R15,%R10,8),%YMM13

  (220) 0x432105 LEA	(%RAX,%RCX,1),%R9

  (220) 0x432109 MOV	0x58(%RSP),%RDI

  (220) 0x43210e ADD	%R8,%R9

  (220) 0x432111 LEA	(%R12,%RCX,1),%RBX

  (220) 0x432115 VMOVUPD	%YMM13,(%RDI,%R9,8)

  (220) 0x43211b ADD	%R8,%RBX

  (220) 0x43211e MOV	0x60(%RSP),%R10

  (220) 0x432123 VADDPD	(%R11,%RBX,8),%YMM13,%YMM14

  (220) 0x432129 ADD	%RCX,%R10

  (220) 0x43212c MOV	0x68(%RSP),%RAX

  (220) 0x432131 ADD	%R8,%R10

  (220) 0x432134 ADD	%RAX,%RCX

  (220) 0x432137 VSUBPD	(%R11,%R10,8),%YMM14,%YMM15

  (220) 0x43213d ADD	%R8,%RCX

  (220) 0x432140 MOV	0x78(%RSP),%R8

  (220) 0x432145 VMOVUPD	%YMM15,(%R8,%RCX,8)

  (220) 0x43214b MOV	%EDX,%ECX

  (220) 0x43214d AND	$-0x4,%ECX

  (220) 0x432150 ADD	%ECX,%ESI

  (220) 0x432152 ADD	%ECX,%R13D

  (220) 0x432155 AND	$0x3,%EDX

  (220) 0x432158 JE	432232

  (220) 0x43215e MOV	0x48(%RSP),%RBX

  (220) 0x432163 MOVSXD	%ESI,%RAX

  (220) 0x432166 LEA	(%RBX,%RAX,1),%RDX

  (220) 0x43216a MOV	0x50(%RSP),%RDI

  (220) 0x43216f VMOVSD	(%R15,%RDX,8),%XMM0

  (220) 0x432175 MOV	0x58(%RSP),%R8

  (220) 0x43217a LEA	(%RDI,%RAX,1),%R9

  (220) 0x43217e VMOVSD	%XMM0,(%R8,%R9,8)

  (220) 0x432184 LEA	(%R12,%RAX,1),%R10

  (220) 0x432188 VADDSD	(%R11,%R10,8),%XMM0,%XMM1

  (220) 0x43218e MOV	0x68(%RSP),%R9

  (220) 0x432193 MOV	0x60(%RSP),%R10

  (220) 0x432198 LEA	(%R9,%RAX,1),%RDX

  (220) 0x43219c ADD	%R10,%RAX

  (220) 0x43219f VSUBSD	(%R11,%RAX,8),%XMM1,%XMM2

  (220) 0x4321a5 MOV	0x78(%RSP),%RCX

  (220) 0x4321aa LEA	0x1(%R13),%EAX

  (220) 0x4321ae VMOVSD	%XMM2,(%RCX,%RDX,8)

  (220) 0x4321b3 CMP	%R14D,%EAX

  (220) 0x4321b6 JAE	432232

  (220) 0x4321b8 LEA	0x1(%RSI),%EAX

  (220) 0x4321bb CLTQ

  (220) 0x4321bd LEA	(%RBX,%RAX,1),%RDX

  (220) 0x4321c1 VMOVSD	(%R15,%RDX,8),%XMM3

  (220) 0x4321c7 LEA	(%RDI,%RAX,1),%RCX

  (220) 0x4321cb VMOVSD	%XMM3,(%R8,%RCX,8)

  (220) 0x4321d1 LEA	(%R12,%RAX,1),%RCX

  (220) 0x4321d5 VADDSD	(%R11,%RCX,8),%XMM3,%XMM4

  (220) 0x4321db LEA	(%R9,%RAX,1),%RDX

  (220) 0x4321df ADD	%R10,%RAX

  (220) 0x4321e2 VSUBSD	(%R11,%RAX,8),%XMM4,%XMM5

  (220) 0x4321e8 MOV	%R10,%RCX

  (220) 0x4321eb MOV	0x78(%RSP),%R10

  (220) 0x4321f0 ADD	$0x2,%R13D

  (220) 0x4321f4 VMOVSD	%XMM5,(%R10,%RDX,8)

  (220) 0x4321fa CMP	%R14D,%R13D

  (220) 0x4321fd JAE	432232

  (220) 0x4321ff ADD	$0x2,%ESI

  (220) 0x432202 MOVSXD	%ESI,%R13

  (220) 0x432205 ADD	%R13,%RBX

  (220) 0x432208 VMOVSD	(%R15,%RBX,8),%XMM6

  (220) 0x43220e ADD	%R13,%RDI

  (220) 0x432211 VMOVSD	%XMM6,(%R8,%RDI,8)

  (220) 0x432217 ADD	%R13,%R12

  (220) 0x43221a VADDSD	(%R11,%R12,8),%XMM6,%XMM7

  (220) 0x432220 ADD	%R13,%RCX

  (220) 0x432223 ADD	%R13,%R9

  (220) 0x432226 VSUBSD	(%R11,%RCX,8),%XMM7,%XMM8

  (220) 0x43222c VMOVSD	%XMM8,(%R10,%R9,8)

  (220) 0x432232 MOV	0x40(%RSP),%RCX

  (220) 0x432237 MOV	%R14D,%R13D

  (220) 0x43223a CMP	%ECX,0x3c(%RSP)

  (220) 0x43223e JLE	432280

  (220) 0x432240 MOV	0x34(%RSP),%ESI

  (220) 0x432244 MOV	0x70(%RSP),%EDX

  (220) 0x432248 SUB	%R13D,%ESI

  (220) 0x43224b CMP	%EDX,%ESI

  (220) 0x43224d MOV	0x38(%RSP),%R14D

  (220) 0x432252 CMOVBE	%ESI,%EDX

  (220) 0x432255 MOV	%R14D,0x74(%RSP)

  (220) 0x43225a LEA	(%R13,%RDX,1),%R14D

  (220) 0x43225f CMP	%R14D,%R13D

  (220) 0x432262 JB	431d68

(222) 0x432268 LEA	0x1(%RCX),%R12

(222) 0x43226c MOV	%R12,0x40(%RSP)

(222) 0x432271 MOV	0x40(%RSP),%RCX

(222) 0x432276 CMP	%ECX,0x3c(%RSP)

(222) 0x43227a JG	432240

0x43227c NOPL	(%RAX)

0x432280 VZEROUPPER

0x432283 LEA	-0x28(%RBP),%RSP

0x432287 POP	%RBX

0x432288 POP	%R12

0x43228a POP	%R13

0x43228c POP	%R14

0x43228e POP	%R15

0x432290 POP	%RBP

0x432291 RET

0x432292 NOPW	(%RAX,%RAX,1)

  (220) 0x432298 MOV	0x74(%RSP),%ESI

  (220) 0x43229c XOR	%R8D,%R8D

  (220) 0x43229f JMP	4320de

0x4322a4 INC	%ESI

0x4322a6 XOR	%EDX,%EDX

0x4322a8 JMP	431cf0

0x4322ad NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.64	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.36	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.00 to 3.00 cycles (5.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:66
DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	85
nb uops	96
loop length	288
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00
cycles	7.20	12.33	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	12.33
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

1% of peak load performance is reached (3.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 12.33 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 431c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4322a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x634>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVL 0x70(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVBE %ESI,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R13,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CMP %R14D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432268 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 431cf0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:66
DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	85
nb uops	96
loop length	288
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00
cycles	7.20	12.33	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	12.33
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

1% of peak load performance is reached (3.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 431c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4322a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x634>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432283 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVL 0x70(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVBE %ESI,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R13,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CMP %R14D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 432268 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 431cf0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.53	0.73
▼Loop 222 - advec_mom.cpp:64-66 - exec–	0.00	0.00
▼Loop 220 - advec_mom.cpp:64-66 - exec–	0.01	0.01
○Loop 221 - advec_mom.cpp:65-66 - exec	2.53	0.73

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code