OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage (incl. loops): 2.98% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x431560 PUSH	%RBP

0x431561 MOV	%RSP,%RBP

0x431564 PUSH	%R15

0x431566 PUSH	%R14

0x431568 PUSH	%R13

0x43156a PUSH	%R12

0x43156c PUSH	%RBX

0x43156d AND	$-0x40,%RSP

0x431571 SUB	$0xc0,%RSP

0x431578 MOV	0x30(%RDI),%EAX

0x43157b MOV	0x34(%RDI),%EBX

0x43157e MOV	0x28(%RDI),%EDX

0x431581 ADD	$0x4,%EBX

0x431584 DEC	%EDX

0x431586 LEA	-0x1(%RAX),%R12D

0x43158a MOV	%EBX,0x5c(%RSP)

0x43158e MOV	%EDX,0x58(%RSP)

0x431592 MOV	0x2c(%RDI),%ECX

0x431595 CMP	%EBX,%R12D

0x431598 JGE	431c2b

0x43159e MOV	%EBX,%R14D

0x4315a1 LEA	0x4(%RCX),%R15D

0x4315a5 SUB	%R12D,%R14D

0x4315a8 CMP	%R15D,%EDX

0x4315ab JGE	431c2b

0x4315b1 MOV	%R15D,%ESI

0x4315b4 SUB	%EDX,%ESI

0x4315b6 MOV	%RDI,%RBX

0x4315b9 MOV	%ESI,0xa0(%RSP)

0x4315c0 CALL	404630 <omp_get_num_threads@plt>

0x4315c5 MOV	%EAX,%R13D

0x4315c8 CALL	404520 <omp_get_thread_num@plt>

0x4315cd MOV	%EAX,%EDI

0x4315cf MOV	0xa0(%RSP),%EAX

0x4315d6 XOR	%EDX,%EDX

0x4315d8 IMUL	%R14D,%EAX

0x4315dc DIV	%R13D

0x4315df MOV	%EAX,%R13D

0x4315e2 CMP	%EDX,%EDI

0x4315e4 JB	431c5f

0x4315ea IMUL	%R13D,%EDI

0x4315ee LEA	(%RDI,%RDX,1),%R14D

0x4315f2 LEA	(%R13,%R14,1),%R8D

0x4315f7 MOV	%R8D,0x54(%RSP)

0x4315fc CMP	%R8D,%R14D

0x4315ff JAE	431c2b

0x431605 MOV	%R14D,%EAX

0x431608 XOR	%EDX,%EDX

0x43160a DIVL	0xa0(%RSP)

0x431611 MOV	0x58(%RSP),%R9D

0x431616 MOV	0x20(%RBX),%RCX

0x43161a MOV	0x10(%RBX),%R10

0x43161e MOV	(%RBX),%R11

0x431621 MOV	%R10,0x48(%RSP)

0x431626 MOV	%R11,0x40(%RSP)

0x43162b MOV	%RCX,0x38(%RSP)

0x431630 ADD	%EDX,%R9D

0x431633 MOV	%R15D,%EDX

0x431636 MOV	0x8(%RBX),%R15

0x43163a MOV	0x18(%RBX),%RBX

0x43163e MOV	%R9D,0xa8(%RSP)

0x431646 MOV	%R15,0x30(%RSP)

0x43164b MOV	%RBX,0x28(%RSP)

0x431650 ADD	%R12D,%EAX

0x431653 SUB	%R9D,%EDX

0x431656 MOVSXD	%EAX,%RCX

0x431659 NOPL	(%RAX)

(218) 0x431660 CMP	%EDX,%R13D

(218) 0x431663 CMOVBE	%R13D,%EDX

(218) 0x431667 LEA	(%R14,%RDX,1),%R12D

(218) 0x43166b MOV	%R12D,0xa4(%RSP)

(218) 0x431673 CMP	%R12D,%R14D

(218) 0x431676 JAE	431c40

(218) 0x43167c MOV	0x30(%RSP),%RBX

(218) 0x431681 MOV	0x48(%RSP),%R13

(218) 0x431686 MOV	0x40(%RSP),%R8

(218) 0x43168b MOV	0x38(%RSP),%RAX

(218) 0x431690 MOV	(%RBX),%R12

(218) 0x431693 MOV	0x10(%RAX),%R11

(218) 0x431697 LEA	0x1(%RCX),%RSI

(218) 0x43169b MOV	(%R13),%RDI

(218) 0x43169f MOV	(%R8),%R9

(218) 0x4316a2 MOV	0x10(%R8),%R15

(218) 0x4316a6 MOV	(%RAX),%R8

(218) 0x4316a9 MOV	0x28(%RSP),%RAX

(218) 0x4316ae MOV	%RSI,0x60(%RSP)

(218) 0x4316b3 IMUL	%R12,%RSI

(218) 0x4316b7 IMUL	%RCX,%RDI

(218) 0x4316bb IMUL	%RCX,%R9

(218) 0x4316bf IMUL	%RCX,%R8

(218) 0x4316c3 IMUL	(%RAX),%RCX

(218) 0x4316c7 MOV	0x10(%R13),%R10

(218) 0x4316cb MOV	%R11,0xb8(%RSP)

(218) 0x4316d3 MOV	0x10(%RBX),%R13

(218) 0x4316d7 MOV	0x10(%RAX),%R11

(218) 0x4316db MOV	%RSI,%RBX

(218) 0x4316de SUB	%R12,%RBX

(218) 0x4316e1 MOV	%RCX,0x88(%RSP)

(218) 0x4316e9 MOV	%RCX,%R12

(218) 0x4316ec LEA	-0x1(%RDX),%ECX

(218) 0x4316ef MOV	%R10,0x90(%RSP)

(218) 0x4316f7 MOV	%RDI,0x68(%RSP)

(218) 0x4316fc MOV	%R9,0x70(%RSP)

(218) 0x431701 MOV	%R8,0x78(%RSP)

(218) 0x431706 MOV	%RSI,0x80(%RSP)

(218) 0x43170e MOV	%RBX,0x98(%RSP)

(218) 0x431716 MOV	%R11,0xb0(%RSP)

(218) 0x43171e CMP	$0x6,%ECX

(218) 0x431721 JBE	431c50

(218) 0x431727 MOVSXD	0xa8(%RSP),%RAX

(218) 0x43172f MOV	0xb8(%RSP),%RCX

(218) 0x431737 LEA	(%RDI,%RAX,1),%RDI

(218) 0x43173b LEA	(%RSI,%RAX,1),%RSI

(218) 0x43173f LEA	(%RBX,%RAX,1),%RBX

(218) 0x431743 LEA	0x1(%R9,%RAX,1),%R9

(218) 0x431748 LEA	(%R8,%RAX,1),%R8

(218) 0x43174c ADD	%R12,%RAX

(218) 0x43174f MOV	0xb0(%RSP),%R12

(218) 0x431757 LEA	(%RCX,%R8,8),%R8

(218) 0x43175b LEA	(%R12,%RAX,8),%RCX

(218) 0x43175f MOV	%EDX,%R12D

(218) 0x431762 SHR	$0x3,%R12D

(218) 0x431766 SAL	$0x6,%R12

(218) 0x43176a LEA	(%R10,%RDI,8),%R11

(218) 0x43176e LEA	(%R13,%RSI,8),%RDI

(218) 0x431773 LEA	(%R13,%RBX,8),%RSI

(218) 0x431778 LEA	-0x40(%R12),%RBX

(218) 0x43177d SHR	$0x6,%RBX

(218) 0x431781 SAL	$0x3,%R9

(218) 0x431785 INC	%RBX

(218) 0x431788 LEA	(%R15,%R9,1),%R10

(218) 0x43178c XOR	%EAX,%EAX

(218) 0x43178e LEA	-0x8(%R15,%R9,1),%R9

(218) 0x431793 AND	$0x3,%EBX

(218) 0x431796 JE	43185c

(218) 0x43179c CMP	$0x1,%RBX

(218) 0x4317a0 JE	431818

(218) 0x4317a2 CMP	$0x2,%RBX

(218) 0x4317a6 JE	4317dd

(218) 0x4317a8 VMOVUPD	(%R11),%ZMM0

(218) 0x4317ae MOV	$0x40,%EAX

(218) 0x4317b3 VADDPD	(%R10),%ZMM0,%ZMM1

(218) 0x4317b9 VSUBPD	(%R9),%ZMM1,%ZMM2

(218) 0x4317bf VMOVUPD	%ZMM2,(%R8)

(218) 0x4317c5 VMOVUPD	(%RDI),%ZMM3

(218) 0x4317cb VSUBPD	(%RSI),%ZMM3,%ZMM4

(218) 0x4317d1 VADDPD	%ZMM2,%ZMM4,%ZMM5

(218) 0x4317d7 VMOVUPD	%ZMM5,(%RCX)

(218) 0x4317dd VMOVUPD	(%R11,%RAX,1),%ZMM6

(218) 0x4317e4 VADDPD	(%R10,%RAX,1),%ZMM6,%ZMM7

(218) 0x4317eb VSUBPD	(%R9,%RAX,1),%ZMM7,%ZMM8

(218) 0x4317f2 VMOVUPD	%ZMM8,(%R8,%RAX,1)

(218) 0x4317f9 VMOVUPD	(%RDI,%RAX,1),%ZMM9

(218) 0x431800 VSUBPD	(%RSI,%RAX,1),%ZMM9,%ZMM10

(218) 0x431807 VADDPD	%ZMM8,%ZMM10,%ZMM11

(218) 0x43180d VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(218) 0x431814 ADD	$0x40,%RAX

(218) 0x431818 VMOVUPD	(%R11,%RAX,1),%ZMM12

(218) 0x43181f VADDPD	(%R10,%RAX,1),%ZMM12,%ZMM13

(218) 0x431826 VSUBPD	(%R9,%RAX,1),%ZMM13,%ZMM14

(218) 0x43182d VMOVUPD	%ZMM14,(%R8,%RAX,1)

(218) 0x431834 VMOVUPD	(%RDI,%RAX,1),%ZMM15

(218) 0x43183b VSUBPD	(%RSI,%RAX,1),%ZMM15,%ZMM0

(218) 0x431842 VADDPD	%ZMM14,%ZMM0,%ZMM1

(218) 0x431848 VMOVUPD	%ZMM1,(%RCX,%RAX,1)

(218) 0x43184f ADD	$0x40,%RAX

(218) 0x431853 CMP	%RAX,%R12

(218) 0x431856 JE	43195c

  (219) 0x43185c VMOVUPD	(%R11,%RAX,1),%ZMM2

  (219) 0x431863 VADDPD	(%R10,%RAX,1),%ZMM2,%ZMM3

  (219) 0x43186a VSUBPD	(%R9,%RAX,1),%ZMM3,%ZMM4

  (219) 0x431871 VMOVUPD	%ZMM4,(%R8,%RAX,1)

  (219) 0x431878 VMOVUPD	(%RDI,%RAX,1),%ZMM5

  (219) 0x43187f VSUBPD	(%RSI,%RAX,1),%ZMM5,%ZMM6

  (219) 0x431886 VADDPD	%ZMM4,%ZMM6,%ZMM7

  (219) 0x43188c VMOVUPD	%ZMM7,(%RCX,%RAX,1)

  (219) 0x431893 VMOVUPD	0x40(%R11,%RAX,1),%ZMM8

  (219) 0x43189b VADDPD	0x40(%R10,%RAX,1),%ZMM8,%ZMM9

  (219) 0x4318a3 VSUBPD	0x40(%R9,%RAX,1),%ZMM9,%ZMM10

  (219) 0x4318ab VMOVUPD	%ZMM10,0x40(%R8,%RAX,1)

  (219) 0x4318b3 VMOVUPD	0x40(%RDI,%RAX,1),%ZMM11

  (219) 0x4318bb VSUBPD	0x40(%RSI,%RAX,1),%ZMM11,%ZMM12

  (219) 0x4318c3 VADDPD	%ZMM10,%ZMM12,%ZMM13

  (219) 0x4318c9 VMOVUPD	%ZMM13,0x40(%RCX,%RAX,1)

  (219) 0x4318d1 VMOVUPD	0x80(%R11,%RAX,1),%ZMM14

  (219) 0x4318d9 VADDPD	0x80(%R10,%RAX,1),%ZMM14,%ZMM15

  (219) 0x4318e1 VSUBPD	0x80(%R9,%RAX,1),%ZMM15,%ZMM0

  (219) 0x4318e9 VMOVUPD	%ZMM0,0x80(%R8,%RAX,1)

  (219) 0x4318f1 VMOVUPD	0x80(%RDI,%RAX,1),%ZMM1

  (219) 0x4318f9 VSUBPD	0x80(%RSI,%RAX,1),%ZMM1,%ZMM2

  (219) 0x431901 VADDPD	%ZMM0,%ZMM2,%ZMM3

  (219) 0x431907 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (219) 0x43190f VMOVUPD	0xc0(%R11,%RAX,1),%ZMM4

  (219) 0x431917 VADDPD	0xc0(%R10,%RAX,1),%ZMM4,%ZMM5

  (219) 0x43191f VSUBPD	0xc0(%R9,%RAX,1),%ZMM5,%ZMM6

  (219) 0x431927 VMOVUPD	%ZMM6,0xc0(%R8,%RAX,1)

  (219) 0x43192f VMOVUPD	0xc0(%RDI,%RAX,1),%ZMM7

  (219) 0x431937 VSUBPD	0xc0(%RSI,%RAX,1),%ZMM7,%ZMM8

  (219) 0x43193f VADDPD	%ZMM6,%ZMM8,%ZMM9

  (219) 0x431945 VMOVUPD	%ZMM9,0xc0(%RCX,%RAX,1)

  (219) 0x43194d ADD	$0x100,%RAX

  (219) 0x431953 CMP	%RAX,%R12

  (219) 0x431956 JNE	43185c

(218) 0x43195c MOV	0xa8(%RSP),%R11D

(218) 0x431964 MOV	%EDX,%R10D

(218) 0x431967 AND	$-0x8,%R10D

(218) 0x43196b LEA	(%R10,%R11,1),%ECX

(218) 0x43196f ADD	%R10D,%R14D

(218) 0x431972 TEST	$0x7,%DL

(218) 0x431975 JE	431bf1

(218) 0x43197b SUB	%R10D,%EDX

(218) 0x43197e LEA	-0x1(%RDX),%R9D

(218) 0x431982 CMP	$0x2,%R9D

(218) 0x431986 JBE	431a45

(218) 0x43198c MOVSXD	0xa8(%RSP),%R8

(218) 0x431994 MOV	0x70(%RSP),%RDI

(218) 0x431999 MOV	0x68(%RSP),%RBX

(218) 0x43199e LEA	(%RDI,%R8,1),%RSI

(218) 0x4319a2 LEA	0x1(%R10,%RSI,1),%R12

(218) 0x4319a7 VMOVUPD	(%R15,%R12,8),%YMM10

(218) 0x4319ad LEA	(%RBX,%R8,1),%RAX

(218) 0x4319b1 VSUBPD	-0x8(%R15,%R12,8),%YMM10,%YMM11

(218) 0x4319b8 MOV	0x90(%RSP),%R11

(218) 0x4319c0 ADD	%R10,%RAX

(218) 0x4319c3 MOV	0x78(%RSP),%R9

(218) 0x4319c8 VADDPD	(%R11,%RAX,8),%YMM11,%YMM12

(218) 0x4319ce MOV	0x80(%RSP),%R12

(218) 0x4319d6 LEA	(%R9,%R8,1),%RDI

(218) 0x4319da MOV	0xb8(%RSP),%RSI

(218) 0x4319e2 ADD	%R10,%RDI

(218) 0x4319e5 LEA	(%R12,%R8,1),%RBX

(218) 0x4319e9 MOV	0x98(%RSP),%RAX

(218) 0x4319f1 VMOVUPD	%YMM12,(%RSI,%RDI,8)

(218) 0x4319f6 ADD	%R10,%RBX

(218) 0x4319f9 VMOVUPD	(%R13,%RBX,8),%YMM13

(218) 0x431a00 LEA	(%RAX,%R8,1),%R11

(218) 0x431a04 ADD	%R10,%R11

(218) 0x431a07 VSUBPD	(%R13,%R11,8),%YMM13,%YMM14

(218) 0x431a0e MOV	0x88(%RSP),%R9

(218) 0x431a16 VADDPD	%YMM12,%YMM14,%YMM15

(218) 0x431a1b ADD	%R9,%R8

(218) 0x431a1e ADD	%R10,%R8

(218) 0x431a21 MOV	0xb0(%RSP),%R10

(218) 0x431a29 VMOVUPD	%YMM15,(%R10,%R8,8)

(218) 0x431a2f MOV	%EDX,%R8D

(218) 0x431a32 AND	$-0x4,%R8D

(218) 0x431a36 ADD	%R8D,%ECX

(218) 0x431a39 ADD	%R8D,%R14D

(218) 0x431a3c AND	$0x3,%EDX

(218) 0x431a3f JE	431bf1

(218) 0x431a45 MOV	0x70(%RSP),%RBX

(218) 0x431a4a LEA	0x1(%RCX),%EDX

(218) 0x431a4d MOVSXD	%EDX,%RDI

(218) 0x431a50 LEA	(%RBX,%RDI,1),%RSI

(218) 0x431a54 LEA	(%R15,%RSI,8),%RSI

(218) 0x431a58 MOVSXD	%ECX,%RAX

(218) 0x431a5b VMOVSD	(%RSI),%XMM0

(218) 0x431a5f LEA	(%RBX,%RAX,1),%R12

(218) 0x431a63 VSUBSD	(%R15,%R12,8),%XMM0,%XMM1

(218) 0x431a69 MOV	0x68(%RSP),%R11

(218) 0x431a6e MOV	0x90(%RSP),%R10

(218) 0x431a76 LEA	(%R11,%RAX,1),%R9

(218) 0x431a7a VADDSD	(%R10,%R9,8),%XMM1,%XMM2

(218) 0x431a80 MOV	0x78(%RSP),%R10

(218) 0x431a85 MOV	0xb8(%RSP),%R8

(218) 0x431a8d MOV	0x80(%RSP),%R12

(218) 0x431a95 LEA	(%R10,%RAX,1),%RDX

(218) 0x431a99 VMOVSD	%XMM2,(%R8,%RDX,8)

(218) 0x431a9f MOV	0x88(%RSP),%R9

(218) 0x431aa7 LEA	(%R12,%RAX,1),%R8

(218) 0x431aab MOV	0x98(%RSP),%RDX

(218) 0x431ab3 VMOVSD	(%R13,%R8,8),%XMM3

(218) 0x431aba MOV	%RDI,0xa8(%RSP)

(218) 0x431ac2 LEA	(%R9,%RAX,1),%RDI

(218) 0x431ac6 ADD	%RDX,%RAX

(218) 0x431ac9 VSUBSD	(%R13,%RAX,8),%XMM3,%XMM4

(218) 0x431ad0 MOV	0xb0(%RSP),%RAX

(218) 0x431ad8 LEA	0x1(%R14),%R8D

(218) 0x431adc VADDSD	%XMM2,%XMM4,%XMM5

(218) 0x431ae0 VMOVSD	%XMM5,(%RAX,%RDI,8)

(218) 0x431ae5 MOV	0xa4(%RSP),%EDI

(218) 0x431aec CMP	%EDI,%R8D

(218) 0x431aef JAE	431bf1

(218) 0x431af5 LEA	0x2(%RCX),%EAX

(218) 0x431af8 CLTQ

(218) 0x431afa LEA	(%RBX,%RAX,1),%RDX

(218) 0x431afe LEA	(%R15,%RDX,8),%R8

(218) 0x431b02 MOV	0xa8(%RSP),%RDI

(218) 0x431b0a MOV	%R8,0x88(%RSP)

(218) 0x431b12 MOV	0x90(%RSP),%RDX

(218) 0x431b1a LEA	(%RDI,%R11,1),%R8

(218) 0x431b1e VMOVSD	(%RDX,%R8,8),%XMM6

(218) 0x431b24 MOV	0x88(%RSP),%R8

(218) 0x431b2c MOV	0x98(%RSP),%RDX

(218) 0x431b34 VADDSD	(%R8),%XMM6,%XMM7

(218) 0x431b39 MOV	0xb8(%RSP),%R8

(218) 0x431b41 ADD	$0x2,%R14D

(218) 0x431b45 VSUBSD	(%RSI),%XMM7,%XMM8

(218) 0x431b49 LEA	(%R10,%RDI,1),%RSI

(218) 0x431b4d VMOVSD	%XMM8,(%R8,%RSI,8)

(218) 0x431b53 LEA	(%R12,%RDI,1),%R8

(218) 0x431b57 VMOVSD	(%R13,%R8,8),%XMM9

(218) 0x431b5e LEA	(%R9,%RDI,1),%RSI

(218) 0x431b62 ADD	%RDX,%RDI

(218) 0x431b65 VSUBSD	(%R13,%RDI,8),%XMM9,%XMM10

(218) 0x431b6c MOV	0xb0(%RSP),%RDI

(218) 0x431b74 VADDSD	%XMM8,%XMM10,%XMM11

(218) 0x431b79 VMOVSD	%XMM11,(%RDI,%RSI,8)

(218) 0x431b7e MOV	0xa4(%RSP),%ESI

(218) 0x431b85 CMP	%ESI,%R14D

(218) 0x431b88 JAE	431bf1

(218) 0x431b8a ADD	$0x3,%ECX

(218) 0x431b8d MOVSXD	%ECX,%R14

(218) 0x431b90 ADD	%RBX,%R14

(218) 0x431b93 VMOVSD	(%R15,%R14,8),%XMM12

(218) 0x431b99 MOV	0x90(%RSP),%R15

(218) 0x431ba1 ADD	%RAX,%R11

(218) 0x431ba4 VADDSD	(%R15,%R11,8),%XMM12,%XMM13

(218) 0x431baa MOV	0x88(%RSP),%RCX

(218) 0x431bb2 MOV	0xb8(%RSP),%RBX

(218) 0x431bba VSUBSD	(%RCX),%XMM13,%XMM14

(218) 0x431bbe ADD	%RAX,%R10

(218) 0x431bc1 MOV	0x98(%RSP),%RDX

(218) 0x431bc9 VMOVSD	%XMM14,(%RBX,%R10,8)

(218) 0x431bcf ADD	%RAX,%R12

(218) 0x431bd2 VMOVSD	(%R13,%R12,8),%XMM15

(218) 0x431bd9 ADD	%RAX,%RDX

(218) 0x431bdc VSUBSD	(%R13,%RDX,8),%XMM15,%XMM0

(218) 0x431be3 ADD	%RAX,%R9

(218) 0x431be6 VADDSD	%XMM14,%XMM0,%XMM1

(218) 0x431beb VMOVSD	%XMM1,(%RDI,%R9,8)

(218) 0x431bf1 MOV	0xa4(%RSP),%R14D

(218) 0x431bf9 MOV	0x60(%RSP),%RCX

(218) 0x431bfe CMP	%ECX,0x5c(%RSP)

(218) 0x431c02 JLE	431c28

(218) 0x431c04 MOV	0x54(%RSP),%R13D

(218) 0x431c09 MOV	0x58(%RSP),%R8D

(218) 0x431c0e MOV	0xa0(%RSP),%EDX

(218) 0x431c15 MOV	%R8D,0xa8(%RSP)

(218) 0x431c1d SUB	%R14D,%R13D

(218) 0x431c20 JMP	431660

0x431c25 NOPL	(%RAX)

0x431c28 VZEROUPPER

0x431c2b LEA	-0x28(%RBP),%RSP

0x431c2f POP	%RBX

0x431c30 POP	%R12

0x431c32 POP	%R13

0x431c34 POP	%R14

0x431c36 POP	%R15

0x431c38 POP	%RBP

0x431c39 RET

0x431c3a NOPW	(%RAX,%RAX,1)

(218) 0x431c40 LEA	0x1(%RCX),%RSI

(218) 0x431c44 MOV	%RSI,0x60(%RSP)

(218) 0x431c49 JMP	431bf9

0x431c4b NOPL	(%RAX,%RAX,1)

(218) 0x431c50 MOV	0xa8(%RSP),%ECX

(218) 0x431c57 XOR	%R10D,%R10D

(218) 0x431c5a JMP	43197b

0x431c5f INC	%R13D

0x431c62 XOR	%EDX,%EDX

0x431c64 JMP	4315ea

0x431c69 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.41	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.50 to 3.00 cycles (5.17x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	83
nb uops	93
loop length	305
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.87 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 431560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EBX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EBX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xa0(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 431c5f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R14,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0xa0(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x58(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4315ea <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	83
nb uops	93
loop length	305
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.87 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 431560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EBX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EBX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xa0(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 431c5f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R14,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 431c2b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0xa0(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x58(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4315ea <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.98	0.86
▼Loop 218 - advec_mom.cpp:53-57 - exec–	0.01	0.01
○Loop 219 - advec_mom.cpp:56-57 - exec	2.97	0.86

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code