OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage (incl. loops): 3.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x430e80 PUSH	%RBP

0x430e81 MOV	%RSP,%RBP

0x430e84 PUSH	%R15

0x430e86 PUSH	%R14

0x430e88 PUSH	%R13

0x430e8a PUSH	%R12

0x430e8c PUSH	%RBX

0x430e8d AND	$-0x40,%RSP

0x430e91 SUB	$0xc0,%RSP

0x430e98 MOV	0x30(%RDI),%EAX

0x430e9b MOV	0x34(%RDI),%ECX

0x430e9e MOV	0x28(%RDI),%EDX

0x430ea1 ADD	$0x4,%ECX

0x430ea4 DEC	%EDX

0x430ea6 LEA	-0x1(%RAX),%R12D

0x430eaa MOV	%ECX,0x60(%RSP)

0x430eae MOV	%EDX,0x5c(%RSP)

0x430eb2 MOV	0x2c(%RDI),%ESI

0x430eb5 CMP	%ECX,%R12D

0x430eb8 JGE	431513

0x430ebe MOV	%ECX,%R14D

0x430ec1 LEA	0x4(%RSI),%R15D

0x430ec5 SUB	%R12D,%R14D

0x430ec8 CMP	%R15D,%EDX

0x430ecb JGE	431513

0x430ed1 MOV	%RDI,%RBX

0x430ed4 MOV	%R15D,%EDI

0x430ed7 SUB	%EDX,%EDI

0x430ed9 MOV	%EDI,0x64(%RSP)

0x430edd CALL	404630 <omp_get_num_threads@plt>

0x430ee2 MOV	%EAX,%R13D

0x430ee5 CALL	404520 <omp_get_thread_num@plt>

0x430eea MOV	%EAX,%R8D

0x430eed MOV	0x64(%RSP),%EAX

0x430ef1 XOR	%EDX,%EDX

0x430ef3 IMUL	%R14D,%EAX

0x430ef7 DIV	%R13D

0x430efa MOV	%EAX,%R13D

0x430efd CMP	%EDX,%R8D

0x430f00 JB	431547

0x430f06 IMUL	%R13D,%R8D

0x430f0a LEA	(%R8,%RDX,1),%R14D

0x430f0e LEA	(%R13,%R14,1),%R9D

0x430f13 MOV	%R9D,0x58(%RSP)

0x430f18 CMP	%R9D,%R14D

0x430f1b JAE	431513

0x430f21 MOV	%R14D,%EAX

0x430f24 XOR	%EDX,%EDX

0x430f26 DIVL	0x64(%RSP)

0x430f2a MOV	0x5c(%RSP),%R10D

0x430f2f MOV	0x8(%RBX),%RCX

0x430f33 MOV	0x10(%RBX),%R11

0x430f37 MOV	(%RBX),%RDI

0x430f3a MOV	%R11,0x50(%RSP)

0x430f3f MOV	%RDI,0x38(%RSP)

0x430f44 MOV	%RCX,0x48(%RSP)

0x430f49 ADD	%EDX,%R10D

0x430f4c MOV	%R15D,%EDX

0x430f4f MOV	0x20(%RBX),%R15

0x430f53 MOV	0x18(%RBX),%RBX

0x430f57 MOV	%R10D,0xac(%RSP)

0x430f5f MOV	%R15,0x40(%RSP)

0x430f64 MOV	%RBX,0x30(%RSP)

0x430f69 ADD	%R12D,%EAX

0x430f6c SUB	%R10D,%EDX

0x430f6f MOVSXD	%EAX,%RCX

0x430f72 NOPW	(%RAX,%RAX,1)

(216) 0x430f78 CMP	%EDX,%R13D

(216) 0x430f7b CMOVBE	%R13D,%EDX

(216) 0x430f7f LEA	(%R14,%RDX,1),%R12D

(216) 0x430f83 MOV	%R12D,0xa8(%RSP)

(216) 0x430f8b CMP	%R12D,%R14D

(216) 0x430f8e JAE	431528

(216) 0x430f94 MOV	0x48(%RSP),%R8

(216) 0x430f99 MOV	0x40(%RSP),%R11

(216) 0x430f9e MOV	(%R8),%RAX

(216) 0x430fa1 MOV	0x50(%RSP),%R13

(216) 0x430fa6 MOV	0x10(%R11),%R15

(216) 0x430faa MOV	0x38(%RSP),%R12

(216) 0x430faf LEA	0x1(%RCX),%RDI

(216) 0x430fb3 MOV	0x10(%R13),%R9

(216) 0x430fb7 MOV	(%R13),%R10

(216) 0x430fbb MOV	%RDI,0x68(%RSP)

(216) 0x430fc0 MOV	%R15,0xb0(%RSP)

(216) 0x430fc8 IMUL	%RAX,%RDI

(216) 0x430fcc MOV	0x10(%R8),%R13

(216) 0x430fd0 MOV	(%R11),%RSI

(216) 0x430fd3 MOV	0x30(%RSP),%R8

(216) 0x430fd8 MOV	0x10(%R12),%R15

(216) 0x430fdd MOV	(%R12),%R12

(216) 0x430fe1 IMUL	%RCX,%R10

(216) 0x430fe5 IMUL	%RCX,%RSI

(216) 0x430fe9 IMUL	%RCX,%R12

(216) 0x430fed IMUL	(%R8),%RCX

(216) 0x430ff1 MOV	%RDI,%RBX

(216) 0x430ff4 SUB	%RAX,%RBX

(216) 0x430ff7 MOV	0x10(%R8),%RAX

(216) 0x430ffb MOV	%RCX,0xa0(%RSP)

(216) 0x431003 LEA	-0x1(%RDX),%ECX

(216) 0x431006 MOV	%R9,0x98(%RSP)

(216) 0x43100e MOV	%R10,0x70(%RSP)

(216) 0x431013 MOV	%RDI,0x78(%RSP)

(216) 0x431018 MOV	%RBX,0x80(%RSP)

(216) 0x431020 MOV	%RSI,0x88(%RSP)

(216) 0x431028 MOV	%R12,0x90(%RSP)

(216) 0x431030 MOV	%RAX,0xb8(%RSP)

(216) 0x431038 CMP	$0x6,%ECX

(216) 0x43103b JBE	431538

(216) 0x431041 MOVSXD	0xac(%RSP),%RAX

(216) 0x431049 MOV	0xa0(%RSP),%RCX

(216) 0x431051 LEA	(%R10,%RAX,1),%R11

(216) 0x431055 LEA	0x1(%R12,%RAX,1),%R12

(216) 0x43105a SAL	$0x3,%R12

(216) 0x43105e LEA	(%R9,%R11,8),%R11

(216) 0x431062 LEA	(%RDI,%RAX,1),%R9

(216) 0x431066 LEA	(%RBX,%RAX,1),%RDI

(216) 0x43106a MOV	0xb0(%RSP),%RBX

(216) 0x431072 LEA	(%RSI,%RAX,1),%R8

(216) 0x431076 LEA	(%R13,%R9,8),%R10

(216) 0x43107b LEA	-0x8(%R15,%R12,1),%RSI

(216) 0x431080 LEA	(%R13,%RDI,8),%R9

(216) 0x431085 LEA	(%R15,%R12,1),%RDI

(216) 0x431089 MOV	%EDX,%R12D

(216) 0x43108c LEA	(%RBX,%R8,8),%R8

(216) 0x431090 SHR	$0x3,%R12D

(216) 0x431094 MOV	0xb8(%RSP),%RBX

(216) 0x43109c ADD	%RCX,%RAX

(216) 0x43109f SAL	$0x6,%R12

(216) 0x4310a3 LEA	(%RBX,%RAX,8),%RCX

(216) 0x4310a7 LEA	-0x40(%R12),%RBX

(216) 0x4310ac SHR	$0x6,%RBX

(216) 0x4310b0 INC	%RBX

(216) 0x4310b3 XOR	%EAX,%EAX

(216) 0x4310b5 AND	$0x3,%EBX

(216) 0x4310b8 JE	43117e

(216) 0x4310be CMP	$0x1,%RBX

(216) 0x4310c2 JE	43113a

(216) 0x4310c4 CMP	$0x2,%RBX

(216) 0x4310c8 JE	4310ff

(216) 0x4310ca VMOVUPD	(%R11),%ZMM0

(216) 0x4310d0 MOV	$0x40,%EAX

(216) 0x4310d5 VADDPD	(%R10),%ZMM0,%ZMM1

(216) 0x4310db VSUBPD	(%R9),%ZMM1,%ZMM2

(216) 0x4310e1 VMOVUPD	%ZMM2,(%R8)

(216) 0x4310e7 VMOVUPD	(%RDI),%ZMM3

(216) 0x4310ed VSUBPD	(%RSI),%ZMM3,%ZMM4

(216) 0x4310f3 VADDPD	%ZMM2,%ZMM4,%ZMM5

(216) 0x4310f9 VMOVUPD	%ZMM5,(%RCX)

(216) 0x4310ff VMOVUPD	(%R11,%RAX,1),%ZMM6

(216) 0x431106 VADDPD	(%R10,%RAX,1),%ZMM6,%ZMM7

(216) 0x43110d VSUBPD	(%R9,%RAX,1),%ZMM7,%ZMM8

(216) 0x431114 VMOVUPD	%ZMM8,(%R8,%RAX,1)

(216) 0x43111b VMOVUPD	(%RDI,%RAX,1),%ZMM9

(216) 0x431122 VSUBPD	(%RSI,%RAX,1),%ZMM9,%ZMM10

(216) 0x431129 VADDPD	%ZMM8,%ZMM10,%ZMM11

(216) 0x43112f VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(216) 0x431136 ADD	$0x40,%RAX

(216) 0x43113a VMOVUPD	(%R11,%RAX,1),%ZMM12

(216) 0x431141 VADDPD	(%R10,%RAX,1),%ZMM12,%ZMM13

(216) 0x431148 VSUBPD	(%R9,%RAX,1),%ZMM13,%ZMM14

(216) 0x43114f VMOVUPD	%ZMM14,(%R8,%RAX,1)

(216) 0x431156 VMOVUPD	(%RDI,%RAX,1),%ZMM15

(216) 0x43115d VSUBPD	(%RSI,%RAX,1),%ZMM15,%ZMM0

(216) 0x431164 VADDPD	%ZMM14,%ZMM0,%ZMM1

(216) 0x43116a VMOVUPD	%ZMM1,(%RCX,%RAX,1)

(216) 0x431171 ADD	$0x40,%RAX

(216) 0x431175 CMP	%RAX,%R12

(216) 0x431178 JE	43127e

  (217) 0x43117e VMOVUPD	(%R11,%RAX,1),%ZMM2

  (217) 0x431185 VADDPD	(%R10,%RAX,1),%ZMM2,%ZMM3

  (217) 0x43118c VSUBPD	(%R9,%RAX,1),%ZMM3,%ZMM4

  (217) 0x431193 VMOVUPD	%ZMM4,(%R8,%RAX,1)

  (217) 0x43119a VMOVUPD	(%RDI,%RAX,1),%ZMM5

  (217) 0x4311a1 VSUBPD	(%RSI,%RAX,1),%ZMM5,%ZMM6

  (217) 0x4311a8 VADDPD	%ZMM4,%ZMM6,%ZMM7

  (217) 0x4311ae VMOVUPD	%ZMM7,(%RCX,%RAX,1)

  (217) 0x4311b5 VMOVUPD	0x40(%R11,%RAX,1),%ZMM8

  (217) 0x4311bd VADDPD	0x40(%R10,%RAX,1),%ZMM8,%ZMM9

  (217) 0x4311c5 VSUBPD	0x40(%R9,%RAX,1),%ZMM9,%ZMM10

  (217) 0x4311cd VMOVUPD	%ZMM10,0x40(%R8,%RAX,1)

  (217) 0x4311d5 VMOVUPD	0x40(%RDI,%RAX,1),%ZMM11

  (217) 0x4311dd VSUBPD	0x40(%RSI,%RAX,1),%ZMM11,%ZMM12

  (217) 0x4311e5 VADDPD	%ZMM10,%ZMM12,%ZMM13

  (217) 0x4311eb VMOVUPD	%ZMM13,0x40(%RCX,%RAX,1)

  (217) 0x4311f3 VMOVUPD	0x80(%R11,%RAX,1),%ZMM14

  (217) 0x4311fb VADDPD	0x80(%R10,%RAX,1),%ZMM14,%ZMM15

  (217) 0x431203 VSUBPD	0x80(%R9,%RAX,1),%ZMM15,%ZMM0

  (217) 0x43120b VMOVUPD	%ZMM0,0x80(%R8,%RAX,1)

  (217) 0x431213 VMOVUPD	0x80(%RDI,%RAX,1),%ZMM1

  (217) 0x43121b VSUBPD	0x80(%RSI,%RAX,1),%ZMM1,%ZMM2

  (217) 0x431223 VADDPD	%ZMM0,%ZMM2,%ZMM3

  (217) 0x431229 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (217) 0x431231 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM4

  (217) 0x431239 VADDPD	0xc0(%R10,%RAX,1),%ZMM4,%ZMM5

  (217) 0x431241 VSUBPD	0xc0(%R9,%RAX,1),%ZMM5,%ZMM6

  (217) 0x431249 VMOVUPD	%ZMM6,0xc0(%R8,%RAX,1)

  (217) 0x431251 VMOVUPD	0xc0(%RDI,%RAX,1),%ZMM7

  (217) 0x431259 VSUBPD	0xc0(%RSI,%RAX,1),%ZMM7,%ZMM8

  (217) 0x431261 VADDPD	%ZMM6,%ZMM8,%ZMM9

  (217) 0x431267 VMOVUPD	%ZMM9,0xc0(%RCX,%RAX,1)

  (217) 0x43126f ADD	$0x100,%RAX

  (217) 0x431275 CMP	%RAX,%R12

  (217) 0x431278 JNE	43117e

(216) 0x43127e MOV	0xac(%RSP),%R11D

(216) 0x431286 MOV	%EDX,%R10D

(216) 0x431289 AND	$-0x8,%R10D

(216) 0x43128d LEA	(%R10,%R11,1),%ESI

(216) 0x431291 ADD	%R10D,%R14D

(216) 0x431294 TEST	$0x7,%DL

(216) 0x431297 JE	4314e0

(216) 0x43129d SUB	%R10D,%EDX

(216) 0x4312a0 LEA	-0x1(%RDX),%R9D

(216) 0x4312a4 CMP	$0x2,%R9D

(216) 0x4312a8 JBE	431365

(216) 0x4312ae MOVSXD	0xac(%RSP),%RCX

(216) 0x4312b6 MOV	0x78(%RSP),%R11

(216) 0x4312bb MOV	0x90(%RSP),%R8

(216) 0x4312c3 MOV	0x70(%RSP),%RBX

(216) 0x4312c8 LEA	(%R11,%RCX,1),%R9

(216) 0x4312cc ADD	%R10,%R9

(216) 0x4312cf LEA	(%R8,%RCX,1),%RDI

(216) 0x4312d3 VMOVUPD	(%R13,%R9,8),%YMM10

(216) 0x4312da LEA	(%RBX,%RCX,1),%RAX

(216) 0x4312de MOV	0x98(%RSP),%R8

(216) 0x4312e6 LEA	0x1(%R10,%RDI,1),%R12

(216) 0x4312eb ADD	%R10,%RAX

(216) 0x4312ee MOV	0x80(%RSP),%RDI

(216) 0x4312f6 VADDPD	(%R8,%RAX,8),%YMM10,%YMM11

(216) 0x4312fc ADD	%RCX,%RDI

(216) 0x4312ff ADD	%R10,%RDI

(216) 0x431302 MOV	0x88(%RSP),%RAX

(216) 0x43130a VSUBPD	(%R13,%RDI,8),%YMM11,%YMM12

(216) 0x431311 ADD	%RCX,%RAX

(216) 0x431314 MOV	0xb0(%RSP),%RBX

(216) 0x43131c ADD	%R10,%RAX

(216) 0x43131f VMOVUPD	%YMM12,(%RBX,%RAX,8)

(216) 0x431324 VMOVUPD	(%R15,%R12,8),%YMM13

(216) 0x43132a VSUBPD	-0x8(%R15,%R12,8),%YMM13,%YMM14

(216) 0x431331 MOV	0xa0(%RSP),%R12

(216) 0x431339 VADDPD	%YMM12,%YMM14,%YMM15

(216) 0x43133e ADD	%R12,%RCX

(216) 0x431341 ADD	%R10,%RCX

(216) 0x431344 MOV	0xb8(%RSP),%R10

(216) 0x43134c VMOVUPD	%YMM15,(%R10,%RCX,8)

(216) 0x431352 MOV	%EDX,%ECX

(216) 0x431354 AND	$-0x4,%ECX

(216) 0x431357 ADD	%ECX,%ESI

(216) 0x431359 ADD	%ECX,%R14D

(216) 0x43135c AND	$0x3,%EDX

(216) 0x43135f JE	4314e0

(216) 0x431365 MOV	0x78(%RSP),%R11

(216) 0x43136a MOVSXD	%ESI,%RAX

(216) 0x43136d LEA	(%R11,%RAX,1),%R8

(216) 0x431371 MOV	0x70(%RSP),%R9

(216) 0x431376 VMOVSD	(%R13,%R8,8),%XMM0

(216) 0x43137d MOV	0x98(%RSP),%RDI

(216) 0x431385 LEA	(%R9,%RAX,1),%RDX

(216) 0x431389 VADDSD	(%RDI,%RDX,8),%XMM0,%XMM1

(216) 0x43138e MOV	0x80(%RSP),%R10

(216) 0x431396 MOV	0x88(%RSP),%R8

(216) 0x43139e LEA	(%R10,%RAX,1),%RBX

(216) 0x4313a2 VSUBSD	(%R13,%RBX,8),%XMM1,%XMM2

(216) 0x4313a9 LEA	0x1(%RSI),%EDX

(216) 0x4313ac MOV	0x90(%RSP),%RBX

(216) 0x4313b4 MOV	0xb0(%RSP),%RCX

(216) 0x4313bc MOVSXD	%EDX,%RDX

(216) 0x4313bf LEA	(%R8,%RAX,1),%R12

(216) 0x4313c3 LEA	(%RBX,%RDX,1),%RDI

(216) 0x4313c7 VMOVSD	%XMM2,(%RCX,%R12,8)

(216) 0x4313cd LEA	(%R15,%RDI,8),%RCX

(216) 0x4313d1 MOV	0xa0(%RSP),%R12

(216) 0x4313d9 VMOVSD	(%RCX),%XMM3

(216) 0x4313dd LEA	(%R12,%RAX,1),%RDI

(216) 0x4313e1 ADD	%RBX,%RAX

(216) 0x4313e4 VSUBSD	(%R15,%RAX,8),%XMM3,%XMM4

(216) 0x4313ea MOV	0xb8(%RSP),%RAX

(216) 0x4313f2 VADDSD	%XMM2,%XMM4,%XMM5

(216) 0x4313f6 VMOVSD	%XMM5,(%RAX,%RDI,8)

(216) 0x4313fb MOV	0xa8(%RSP),%EDI

(216) 0x431402 LEA	0x1(%R14),%EAX

(216) 0x431406 CMP	%EDI,%EAX

(216) 0x431408 JAE	4314e0

(216) 0x43140e LEA	(%RDX,%R11,1),%RDI

(216) 0x431412 VMOVSD	(%R13,%RDI,8),%XMM6

(216) 0x431419 MOV	0x98(%RSP),%RDI

(216) 0x431421 LEA	(%RDX,%R9,1),%RAX

(216) 0x431425 VADDSD	(%RDI,%RAX,8),%XMM6,%XMM7

(216) 0x43142a LEA	(%RDX,%R10,1),%RAX

(216) 0x43142e MOV	0xb0(%RSP),%RDI

(216) 0x431436 VSUBSD	(%R13,%RAX,8),%XMM7,%XMM8

(216) 0x43143d LEA	(%RDX,%R8,1),%RAX

(216) 0x431441 ADD	%R12,%RDX

(216) 0x431444 VMOVSD	%XMM8,(%RDI,%RAX,8)

(216) 0x431449 LEA	0x2(%RSI),%EAX

(216) 0x43144c CLTQ

(216) 0x43144e LEA	(%RBX,%RAX,1),%RDI

(216) 0x431452 LEA	(%R15,%RDI,8),%RDI

(216) 0x431456 VMOVSD	(%RDI),%XMM9

(216) 0x43145a ADD	$0x2,%R14D

(216) 0x43145e VSUBSD	(%RCX),%XMM9,%XMM10

(216) 0x431462 MOV	0xb8(%RSP),%RCX

(216) 0x43146a VADDSD	%XMM8,%XMM10,%XMM11

(216) 0x43146f VMOVSD	%XMM11,(%RCX,%RDX,8)

(216) 0x431474 MOV	0xa8(%RSP),%EDX

(216) 0x43147b CMP	%EDX,%R14D

(216) 0x43147e JAE	4314e0

(216) 0x431480 ADD	%RAX,%R11

(216) 0x431483 VMOVSD	(%R13,%R11,8),%XMM12

(216) 0x43148a MOV	0x98(%RSP),%R14

(216) 0x431492 ADD	%RAX,%R9

(216) 0x431495 VADDSD	(%R14,%R9,8),%XMM12,%XMM13

(216) 0x43149b ADD	%RAX,%R10

(216) 0x43149e ADD	$0x3,%ESI

(216) 0x4314a1 VSUBSD	(%R13,%R10,8),%XMM13,%XMM14

(216) 0x4314a8 MOV	0xb0(%RSP),%R13

(216) 0x4314b0 ADD	%RAX,%R8

(216) 0x4314b3 MOVSXD	%ESI,%RSI

(216) 0x4314b6 VMOVSD	%XMM14,(%R13,%R8,8)

(216) 0x4314bd ADD	%RBX,%RSI

(216) 0x4314c0 VMOVSD	(%R15,%RSI,8),%XMM15

(216) 0x4314c6 MOV	0xb8(%RSP),%R15

(216) 0x4314ce VSUBSD	(%RDI),%XMM15,%XMM0

(216) 0x4314d2 ADD	%RAX,%R12

(216) 0x4314d5 VADDSD	%XMM14,%XMM0,%XMM1

(216) 0x4314da VMOVSD	%XMM1,(%R15,%R12,8)

(216) 0x4314e0 MOV	0xa8(%RSP),%R14D

(216) 0x4314e8 MOV	0x68(%RSP),%RCX

(216) 0x4314ed CMP	%ECX,0x60(%RSP)

(216) 0x4314f1 JLE	431510

(216) 0x4314f3 MOV	0x58(%RSP),%R13D

(216) 0x4314f8 MOV	0x5c(%RSP),%EBX

(216) 0x4314fc MOV	0x64(%RSP),%EDX

(216) 0x431500 MOV	%EBX,0xac(%RSP)

(216) 0x431507 SUB	%R14D,%R13D

(216) 0x43150a JMP	430f78

0x43150f NOP

0x431510 VZEROUPPER

0x431513 LEA	-0x28(%RBP),%RSP

0x431517 POP	%RBX

0x431518 POP	%R12

0x43151a POP	%R13

0x43151c POP	%R14

0x43151e POP	%R15

0x431520 POP	%RBP

0x431521 RET

0x431522 NOPW	(%RAX,%RAX,1)

(216) 0x431528 LEA	0x1(%RCX),%RSI

(216) 0x43152c MOV	%RSI,0x68(%RSP)

(216) 0x431531 JMP	4314e8

0x431533 NOPL	(%RAX,%RAX,1)

(216) 0x431538 MOV	0xac(%RSP),%ESI

(216) 0x43153f XOR	%R10D,%R10D

(216) 0x431542 JMP	43129d

0x431547 INC	%R13D

0x43154a XOR	%EDX,%EDX

0x43154c JMP	430f06

0x431551 NOPW	%CS:(%RAX,%RAX,1)

0x43155c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.41	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.67 to 3.00 cycles (5.22x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.67 to 14.50 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	84
nb uops	94
loop length	303
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.67
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

2% of peak load performance is reached (4.34 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 430e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x28(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x64(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 431547 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x64(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x5c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,0xac(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 430f06 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x86>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.67 to 14.50 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	84
nb uops	94
loop length	303
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.67
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

2% of peak load performance is reached (4.34 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 430e80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x28(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
DEC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x64(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 431547 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 431513 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x693>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x64(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x5c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,0xac(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 430f06 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x86>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.06	0.88
▼Loop 216 - advec_mom.cpp:44-48 - exec–	0.01	0.01
○Loop 217 - advec_mom.cpp:47-48 - exec	3.05	0.88

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code