OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 3.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

--------------------------------------------------------------------------------

208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42e2a0 PUSH	%RBP

0x42e2a1 MOV	%RSP,%RBP

0x42e2a4 PUSH	%R15

0x42e2a6 PUSH	%R14

0x42e2a8 PUSH	%R13

0x42e2aa PUSH	%R12

0x42e2ac PUSH	%RBX

0x42e2ad AND	$-0x40,%RSP

0x42e2b1 SUB	$0x100,%RSP

0x42e2b8 MOV	0x38(%RDI),%EAX

0x42e2bb MOV	0x3c(%RDI),%EDX

0x42e2be MOV	0x30(%RDI),%ESI

0x42e2c1 ADD	$0x2,%EDX

0x42e2c4 INC	%ESI

0x42e2c6 LEA	0x1(%RAX),%R12D

0x42e2ca MOV	%EDX,0x70(%RSP)

0x42e2ce MOV	%ESI,0x6c(%RSP)

0x42e2d2 MOV	0x34(%RDI),%ECX

0x42e2d5 CMP	%EDX,%R12D

0x42e2d8 JGE	42ea73

0x42e2de MOV	%EDX,%R14D

0x42e2e1 LEA	0x2(%RCX),%R15D

0x42e2e5 SUB	%R12D,%R14D

0x42e2e8 CMP	%R15D,%ESI

0x42e2eb JGE	42ea73

0x42e2f1 MOV	%RDI,%RBX

0x42e2f4 MOV	%R15D,%EDI

0x42e2f7 SUB	%ESI,%EDI

0x42e2f9 MOV	%EDI,0x74(%RSP)

0x42e2fd CALL	404630 <omp_get_num_threads@plt>

0x42e302 MOV	%EAX,%R13D

0x42e305 CALL	404520 <omp_get_thread_num@plt>

0x42e30a MOV	%EAX,%R8D

0x42e30d MOV	0x74(%RSP),%EAX

0x42e311 XOR	%EDX,%EDX

0x42e313 IMUL	%R14D,%EAX

0x42e317 DIV	%R13D

0x42e31a MOV	%EAX,%ECX

0x42e31c CMP	%EDX,%R8D

0x42e31f JB	42ea97

0x42e325 IMUL	%ECX,%R8D

0x42e329 LEA	(%R8,%RDX,1),%R13D

0x42e32d LEA	(%RCX,%R13,1),%R9D

0x42e331 MOV	%R9D,0x68(%RSP)

0x42e336 CMP	%R9D,%R13D

0x42e339 JAE	42ea73

0x42e33f MOV	%R13D,%EAX

0x42e342 XOR	%EDX,%EDX

0x42e344 DIVL	0x74(%RSP)

0x42e348 MOV	0x6c(%RSP),%R10D

0x42e34d MOV	(%RBX),%R11

0x42e350 MOV	0x20(%RBX),%RSI

0x42e354 MOV	0x8(%RBX),%R14

0x42e358 MOV	0x28(%RBX),%RDI

0x42e35c MOV	%R11,0x60(%RSP)

0x42e361 MOV	%RSI,0x58(%RSP)

0x42e366 MOV	%R14,0x48(%RSP)

0x42e36b MOV	%RDI,0x40(%RSP)

0x42e370 ADD	%EDX,%R10D

0x42e373 MOV	%R15D,%EDX

0x42e376 MOV	0x10(%RBX),%R15

0x42e37a MOV	0x18(%RBX),%RBX

0x42e37e MOV	%R10D,0xd4(%RSP)

0x42e386 MOV	%RBX,0x38(%RSP)

0x42e38b ADD	%R12D,%EAX

0x42e38e MOV	%R15,0x50(%RSP)

0x42e393 SUB	%R10D,%EDX

0x42e396 MOVSXD	%EAX,%R15

0x42e399 NOPL	(%RAX)

(208) 0x42e3a0 CMP	%EDX,%ECX

(208) 0x42e3a2 MOV	%EDX,%ESI

(208) 0x42e3a4 CMOVBE	%ECX,%ESI

(208) 0x42e3a7 LEA	(%R13,%RSI,1),%R12D

(208) 0x42e3ac MOV	%R12D,0xd0(%RSP)

(208) 0x42e3b4 CMP	%R12D,%R13D

(208) 0x42e3b7 JAE	42ea42

(208) 0x42e3bd MOV	0x50(%RSP),%RAX

(208) 0x42e3c2 MOV	0x58(%RSP),%R8

(208) 0x42e3c7 MOV	(%RAX),%RDX

(208) 0x42e3ca MOV	0x10(%R8),%R9

(208) 0x42e3ce MOV	%RDX,%RBX

(208) 0x42e3d1 IMUL	%R15,%RBX

(208) 0x42e3d5 MOV	0x48(%RSP),%R14

(208) 0x42e3da MOV	(%R8),%R10

(208) 0x42e3dd MOV	0x40(%RSP),%R8

(208) 0x42e3e2 ADD	%RBX,%RDX

(208) 0x42e3e5 MOV	0x10(%R14),%RDI

(208) 0x42e3e9 MOV	%RDX,0xc0(%RSP)

(208) 0x42e3f1 MOV	(%R8),%RDX

(208) 0x42e3f4 MOV	%RDI,0xe0(%RSP)

(208) 0x42e3fc MOV	%RDX,%RDI

(208) 0x42e3ff IMUL	%R15,%RDI

(208) 0x42e403 MOV	0x10(%RAX),%R11

(208) 0x42e407 MOV	0x10(%R8),%RAX

(208) 0x42e40b MOV	0x38(%RSP),%R8

(208) 0x42e410 MOV	0x60(%RSP),%RCX

(208) 0x42e415 MOV	%RAX,0xc8(%RSP)

(208) 0x42e41d MOV	(%R8),%RAX

(208) 0x42e420 MOV	%R9,0xd8(%RSP)

(208) 0x42e428 MOV	(%R14),%R9

(208) 0x42e42b LEA	(%RDX,%RDI,1),%R14

(208) 0x42e42f MOV	0x10(%RCX),%R12

(208) 0x42e433 MOV	%R14,0xe8(%RSP)

(208) 0x42e43b MOV	(%RCX),%RCX

(208) 0x42e43e MOV	0x10(%R8),%R14

(208) 0x42e442 MOV	%RAX,%R8

(208) 0x42e445 IMUL	%R15,%R8

(208) 0x42e449 IMUL	%R15,%RCX

(208) 0x42e44d IMUL	%R15,%R10

(208) 0x42e451 IMUL	%R15,%R9

(208) 0x42e455 LEA	(%RAX,%R8,1),%RDX

(208) 0x42e459 LEA	-0x1(%RSI),%EAX

(208) 0x42e45c MOV	%R12,0xa0(%RSP)

(208) 0x42e464 MOV	%RCX,0x78(%RSP)

(208) 0x42e469 MOV	%R10,0x80(%RSP)

(208) 0x42e471 MOV	%R11,0x88(%RSP)

(208) 0x42e479 MOV	%RBX,0xa8(%RSP)

(208) 0x42e481 MOV	%R9,0xb0(%RSP)

(208) 0x42e489 MOV	%RDI,0xb8(%RSP)

(208) 0x42e491 MOV	%R8,0x98(%RSP)

(208) 0x42e499 MOV	%RDX,0xf0(%RSP)

(208) 0x42e4a1 CMP	$0x6,%EAX

(208) 0x42e4a4 JBE	42ea88

(208) 0x42e4aa MOVSXD	0xd4(%RSP),%RAX

(208) 0x42e4b2 LEA	(%RCX,%RAX,1),%RDX

(208) 0x42e4b6 LEA	(%R12,%RDX,8),%RCX

(208) 0x42e4ba LEA	(%RBX,%RAX,1),%RDX

(208) 0x42e4be LEA	(%R10,%RAX,1),%R12

(208) 0x42e4c2 MOV	0xd8(%RSP),%R10

(208) 0x42e4ca MOV	%R11,%RBX

(208) 0x42e4cd LEA	(%R11,%RDX,8),%R11

(208) 0x42e4d1 MOV	0xe0(%RSP),%RDX

(208) 0x42e4d9 LEA	(%R9,%RAX,1),%R9

(208) 0x42e4dd LEA	(%R10,%R12,8),%R12

(208) 0x42e4e1 MOV	0xc0(%RSP),%R10

(208) 0x42e4e9 LEA	(%RDX,%R9,8),%RDX

(208) 0x42e4ed MOV	0xc8(%RSP),%R9

(208) 0x42e4f5 ADD	%RAX,%R10

(208) 0x42e4f8 ADD	%RAX,%RDI

(208) 0x42e4fb LEA	(%RBX,%R10,8),%RBX

(208) 0x42e4ff LEA	(%R9,%RDI,8),%R10

(208) 0x42e503 MOV	0xe8(%RSP),%RDI

(208) 0x42e50b LEA	(%R8,%RAX,1),%R8

(208) 0x42e50f ADD	%RAX,%RDI

(208) 0x42e512 LEA	(%R9,%RDI,8),%R9

(208) 0x42e516 MOV	0xf0(%RSP),%RDI

(208) 0x42e51e LEA	(%R14,%R8,8),%R8

(208) 0x42e522 ADD	%RDI,%RAX

(208) 0x42e525 LEA	(%R14,%RAX,8),%RDI

(208) 0x42e529 MOV	%ESI,%EAX

(208) 0x42e52b SHR	$0x3,%EAX

(208) 0x42e52e MOV	%RAX,0x90(%RSP)

(208) 0x42e536 SAL	$0x6,%RAX

(208) 0x42e53a MOV	%RAX,0xf8(%RSP)

(208) 0x42e542 XOR	%EAX,%EAX

(208) 0x42e544 TESTB	$0x1,0x90(%RSP)

(208) 0x42e54c JE	42e5b8

(208) 0x42e54e VMOVUPD	(%R12),%ZMM0

(208) 0x42e555 VMOVUPD	(%R10),%ZMM3

(208) 0x42e55b VMULPD	(%RCX),%ZMM0,%ZMM1

(208) 0x42e561 VSUBPD	(%R9),%ZMM3,%ZMM5

(208) 0x42e567 VADDPD	(%R8),%ZMM0,%ZMM6

(208) 0x42e56d CMPQ	$0x40,0xf8(%RSP)

(208) 0x42e576 MOV	$0x40,%EAX

(208) 0x42e57b VSUBPD	(%RBX),%ZMM1,%ZMM2

(208) 0x42e581 VFMADD132PD	(%RDX),%ZMM5,%ZMM1

(208) 0x42e587 VSUBPD	(%RDI),%ZMM6,%ZMM7

(208) 0x42e58d VADDPD	(%R11),%ZMM2,%ZMM4

(208) 0x42e593 VDIVPD	%ZMM7,%ZMM4,%ZMM8

(208) 0x42e599 VDIVPD	%ZMM4,%ZMM1,%ZMM9

(208) 0x42e59f VMOVUPD	%ZMM8,(%RCX)

(208) 0x42e5a5 VMOVUPD	%ZMM9,(%RDX)

(208) 0x42e5ab JE	42e687

(208) 0x42e5b1 NOPL	(%RAX)

  (209) 0x42e5b8 VMOVUPD	(%R12,%RAX,1),%ZMM10

  (209) 0x42e5bf VMOVUPD	(%R10,%RAX,1),%ZMM14

  (209) 0x42e5c6 VMULPD	(%RCX,%RAX,1),%ZMM10,%ZMM11

  (209) 0x42e5cd VSUBPD	(%R9,%RAX,1),%ZMM14,%ZMM15

  (209) 0x42e5d4 VADDPD	(%R8,%RAX,1),%ZMM10,%ZMM0

  (209) 0x42e5db VSUBPD	(%RBX,%RAX,1),%ZMM11,%ZMM12

  (209) 0x42e5e2 VFMADD132PD	(%RDX,%RAX,1),%ZMM15,%ZMM11

  (209) 0x42e5e9 VSUBPD	(%RDI,%RAX,1),%ZMM0,%ZMM1

  (209) 0x42e5f0 VADDPD	(%R11,%RAX,1),%ZMM12,%ZMM13

  (209) 0x42e5f7 VDIVPD	%ZMM13,%ZMM11,%ZMM4

  (209) 0x42e5fd VDIVPD	%ZMM1,%ZMM13,%ZMM2

  (209) 0x42e603 VMOVUPD	%ZMM2,(%RCX,%RAX,1)

  (209) 0x42e60a VMOVUPD	%ZMM4,(%RDX,%RAX,1)

  (209) 0x42e611 VMOVUPD	0x40(%R12,%RAX,1),%ZMM5

  (209) 0x42e619 VMOVUPD	0x40(%R10,%RAX,1),%ZMM8

  (209) 0x42e621 VMULPD	0x40(%RCX,%RAX,1),%ZMM5,%ZMM6

  (209) 0x42e629 VSUBPD	0x40(%R9,%RAX,1),%ZMM8,%ZMM9

  (209) 0x42e631 VADDPD	0x40(%R8,%RAX,1),%ZMM5,%ZMM10

  (209) 0x42e639 VSUBPD	0x40(%RBX,%RAX,1),%ZMM6,%ZMM3

  (209) 0x42e641 VFMADD132PD	0x40(%RDX,%RAX,1),%ZMM9,%ZMM6

  (209) 0x42e649 VSUBPD	0x40(%RDI,%RAX,1),%ZMM10,%ZMM11

  (209) 0x42e651 VADDPD	0x40(%R11,%RAX,1),%ZMM3,%ZMM7

  (209) 0x42e659 VDIVPD	%ZMM11,%ZMM7,%ZMM12

  (209) 0x42e65f VDIVPD	%ZMM7,%ZMM6,%ZMM13

  (209) 0x42e665 VMOVUPD	%ZMM12,0x40(%RCX,%RAX,1)

  (209) 0x42e66d VMOVUPD	%ZMM13,0x40(%RDX,%RAX,1)

  (209) 0x42e675 SUB	$-0x80,%RAX

  (209) 0x42e679 CMP	%RAX,0xf8(%RSP)

  (209) 0x42e681 JNE	42e5b8

(208) 0x42e687 MOV	0xd4(%RSP),%ECX

(208) 0x42e68e MOV	%ESI,%R12D

(208) 0x42e691 AND	$-0x8,%R12D

(208) 0x42e695 ADD	%R12D,%ECX

(208) 0x42e698 ADD	%R12D,%R13D

(208) 0x42e69b TEST	$0x7,%SIL

(208) 0x42e69f JE	42ea3a

(208) 0x42e6a5 SUB	%R12D,%ESI

(208) 0x42e6a8 LEA	-0x1(%RSI),%R11D

(208) 0x42e6ac CMP	$0x2,%R11D

(208) 0x42e6b0 JBE	42e7c8

(208) 0x42e6b6 MOVSXD	0xd4(%RSP),%RDX

(208) 0x42e6be MOV	0x78(%RSP),%RBX

(208) 0x42e6c3 MOV	0xa0(%RSP),%R9

(208) 0x42e6cb LEA	(%RBX,%RDX,1),%R10

(208) 0x42e6cf MOV	0xb0(%RSP),%R8

(208) 0x42e6d7 ADD	%R12,%R10

(208) 0x42e6da LEA	(%R9,%R10,8),%RAX

(208) 0x42e6de LEA	(%R8,%RDX,1),%RDI

(208) 0x42e6e2 MOV	0xe0(%RSP),%R11

(208) 0x42e6ea MOV	0x98(%RSP),%RBX

(208) 0x42e6f2 MOV	0x80(%RSP),%R9

(208) 0x42e6fa ADD	%R12,%RDI

(208) 0x42e6fd LEA	(%R11,%RDI,8),%R10

(208) 0x42e701 LEA	(%RBX,%RDX,1),%R8

(208) 0x42e705 LEA	(%R9,%RDX,1),%R11

(208) 0x42e709 MOV	0xd8(%RSP),%RBX

(208) 0x42e711 ADD	%R12,%R11

(208) 0x42e714 VMOVUPD	(%RBX,%R11,8),%YMM14

(208) 0x42e71a MOV	0xc0(%RSP),%R9

(208) 0x42e722 VMULPD	(%RAX),%YMM14,%YMM15

(208) 0x42e726 MOV	0x88(%RSP),%RBX

(208) 0x42e72e LEA	(%R9,%RDX,1),%R11

(208) 0x42e732 ADD	%R12,%R11

(208) 0x42e735 MOV	0xa8(%RSP),%R9

(208) 0x42e73d VSUBPD	(%RBX,%R11,8),%YMM15,%YMM0

(208) 0x42e743 ADD	%RDX,%R9

(208) 0x42e746 MOV	0xb8(%RSP),%R11

(208) 0x42e74e ADD	%R12,%R9

(208) 0x42e751 VADDPD	(%RBX,%R9,8),%YMM0,%YMM1

(208) 0x42e757 MOV	0xf0(%RSP),%RDI

(208) 0x42e75f LEA	(%R11,%RDX,1),%R9

(208) 0x42e763 MOV	0xc8(%RSP),%RBX

(208) 0x42e76b MOV	0xe8(%RSP),%R11

(208) 0x42e773 ADD	%R12,%R9

(208) 0x42e776 VMOVUPD	(%RBX,%R9,8),%YMM2

(208) 0x42e77c ADD	%RDX,%RDI

(208) 0x42e77f ADD	%R11,%RDX

(208) 0x42e782 ADD	%R12,%RDX

(208) 0x42e785 VSUBPD	(%RBX,%RDX,8),%YMM2,%YMM4

(208) 0x42e78a ADD	%R12,%R8

(208) 0x42e78d VADDPD	(%R14,%R8,8),%YMM14,%YMM5

(208) 0x42e793 VFMADD132PD	(%R10),%YMM4,%YMM15

(208) 0x42e798 ADD	%R12,%RDI

(208) 0x42e79b VSUBPD	(%R14,%RDI,8),%YMM5,%YMM6

(208) 0x42e7a1 MOV	%ESI,%R12D

(208) 0x42e7a4 AND	$-0x4,%R12D

(208) 0x42e7a8 VDIVPD	%YMM6,%YMM1,%YMM3

(208) 0x42e7ac ADD	%R12D,%ECX

(208) 0x42e7af ADD	%R12D,%R13D

(208) 0x42e7b2 AND	$0x3,%ESI

(208) 0x42e7b5 VDIVPD	%YMM1,%YMM15,%YMM7

(208) 0x42e7b9 VMOVUPD	%YMM3,(%RAX)

(208) 0x42e7bd VMOVUPD	%YMM7,(%R10)

(208) 0x42e7c2 JE	42ea3a

(208) 0x42e7c8 MOV	0x80(%RSP),%R9

(208) 0x42e7d0 MOVSXD	%ECX,%RAX

(208) 0x42e7d3 MOV	0xd8(%RSP),%RDI

(208) 0x42e7db MOV	0x78(%RSP),%R10

(208) 0x42e7e0 LEA	(%R9,%RAX,1),%R8

(208) 0x42e7e4 MOV	0xa0(%RSP),%RSI

(208) 0x42e7ec VMOVSD	(%RDI,%R8,8),%XMM8

(208) 0x42e7f2 LEA	(%R10,%RAX,1),%RDX

(208) 0x42e7f6 LEA	(%RSI,%RDX,8),%RSI

(208) 0x42e7fa VMULSD	(%RSI),%XMM8,%XMM9

(208) 0x42e7fe MOV	0xc0(%RSP),%R12

(208) 0x42e806 MOV	0x88(%RSP),%RBX

(208) 0x42e80e LEA	(%R12,%RAX,1),%R11

(208) 0x42e812 MOV	0xa8(%RSP),%RDX

(208) 0x42e81a VSUBSD	(%RBX,%R11,8),%XMM9,%XMM10

(208) 0x42e820 MOV	0xb0(%RSP),%RDI

(208) 0x42e828 LEA	(%RDX,%RAX,1),%R8

(208) 0x42e82c MOV	0xe0(%RSP),%R11

(208) 0x42e834 VADDSD	(%RBX,%R8,8),%XMM10,%XMM11

(208) 0x42e83a LEA	(%RDI,%RAX,1),%RDX

(208) 0x42e83e MOV	0xb8(%RSP),%R8

(208) 0x42e846 LEA	(%R11,%RDX,8),%RDX

(208) 0x42e84a MOV	0xc8(%RSP),%R11

(208) 0x42e852 LEA	(%R8,%RAX,1),%R8

(208) 0x42e856 MOV	0xe8(%RSP),%RDI

(208) 0x42e85e VMOVSD	(%R11,%R8,8),%XMM12

(208) 0x42e864 MOV	0x98(%RSP),%R8

(208) 0x42e86c LEA	(%RDI,%RAX,1),%RDI

(208) 0x42e870 VSUBSD	(%R11,%RDI,8),%XMM12,%XMM13

(208) 0x42e876 LEA	(%R8,%RAX,1),%RDI

(208) 0x42e87a VADDSD	(%R14,%RDI,8),%XMM8,%XMM14

(208) 0x42e880 MOV	0xf0(%RSP),%R8

(208) 0x42e888 VFMADD132SD	(%RDX),%XMM13,%XMM9

(208) 0x42e88d ADD	%R8,%RAX

(208) 0x42e890 VSUBSD	(%R14,%RAX,8),%XMM14,%XMM15

(208) 0x42e896 LEA	0x1(%R13),%EAX

(208) 0x42e89a VDIVSD	%XMM15,%XMM11,%XMM0

(208) 0x42e89f VDIVSD	%XMM11,%XMM9,%XMM1

(208) 0x42e8a4 VMOVSD	%XMM0,(%RSI)

(208) 0x42e8a8 MOV	0xd0(%RSP),%ESI

(208) 0x42e8af VMOVSD	%XMM1,(%RDX)

(208) 0x42e8b3 CMP	%ESI,%EAX

(208) 0x42e8b5 JAE	42ea3a

(208) 0x42e8bb LEA	0x1(%RCX),%EAX

(208) 0x42e8be CLTQ

(208) 0x42e8c0 MOV	0xa0(%RSP),%RDI

(208) 0x42e8c8 LEA	(%R10,%RAX,1),%RDX

(208) 0x42e8cc MOV	0xd8(%RSP),%R8

(208) 0x42e8d4 LEA	(%RDI,%RDX,8),%RSI

(208) 0x42e8d8 LEA	(%R9,%RAX,1),%RDX

(208) 0x42e8dc VMOVSD	(%R8,%RDX,8),%XMM4

(208) 0x42e8e2 LEA	(%R12,%RAX,1),%RDI

(208) 0x42e8e6 VMULSD	(%RSI),%XMM4,%XMM5

(208) 0x42e8ea MOV	0xa8(%RSP),%RDX

(208) 0x42e8f2 LEA	(%RDX,%RAX,1),%R8

(208) 0x42e8f6 VSUBSD	(%RBX,%RDI,8),%XMM5,%XMM2

(208) 0x42e8fb MOV	0xb0(%RSP),%RDI

(208) 0x42e903 VADDSD	(%RBX,%R8,8),%XMM2,%XMM6

(208) 0x42e909 LEA	(%RDI,%RAX,1),%RDX

(208) 0x42e90d MOV	0xe0(%RSP),%R8

(208) 0x42e915 MOV	0xb8(%RSP),%RDI

(208) 0x42e91d LEA	(%R8,%RDX,8),%RDX

(208) 0x42e921 LEA	(%RDI,%RAX,1),%R8

(208) 0x42e925 MOV	0xe8(%RSP),%RDI

(208) 0x42e92d VMOVSD	(%R11,%R8,8),%XMM3

(208) 0x42e933 ADD	%RAX,%RDI

(208) 0x42e936 MOV	0x98(%RSP),%R8

(208) 0x42e93e VSUBSD	(%R11,%RDI,8),%XMM3,%XMM7

(208) 0x42e944 LEA	(%R8,%RAX,1),%RDI

(208) 0x42e948 VADDSD	(%R14,%RDI,8),%XMM4,%XMM8

(208) 0x42e94e MOV	0xf0(%RSP),%RDI

(208) 0x42e956 VFMADD132SD	(%RDX),%XMM7,%XMM5

(208) 0x42e95b ADD	%RDI,%RAX

(208) 0x42e95e VSUBSD	(%R14,%RAX,8),%XMM8,%XMM9

(208) 0x42e964 LEA	0x2(%R13),%EAX

(208) 0x42e968 MOV	0xd0(%RSP),%R13D

(208) 0x42e970 VDIVSD	%XMM9,%XMM6,%XMM10

(208) 0x42e975 VDIVSD	%XMM6,%XMM5,%XMM11

(208) 0x42e979 VMOVSD	%XMM10,(%RSI)

(208) 0x42e97d VMOVSD	%XMM11,(%RDX)

(208) 0x42e981 CMP	%R13D,%EAX

(208) 0x42e984 JAE	42ea3a

(208) 0x42e98a ADD	$0x2,%ECX

(208) 0x42e98d MOVSXD	%ECX,%RCX

(208) 0x42e990 MOV	0xd8(%RSP),%RDX

(208) 0x42e998 MOV	%R10,%RSI

(208) 0x42e99b ADD	%RCX,%R9

(208) 0x42e99e MOV	0xa0(%RSP),%R10

(208) 0x42e9a6 VMOVSD	(%RDX,%R9,8),%XMM12

(208) 0x42e9ac ADD	%RCX,%RSI

(208) 0x42e9af LEA	(%R10,%RSI,8),%RAX

(208) 0x42e9b3 VMULSD	(%RAX),%XMM12,%XMM13

(208) 0x42e9b7 MOV	0xb8(%RSP),%RSI

(208) 0x42e9bf ADD	%RCX,%R12

(208) 0x42e9c2 MOV	0xa8(%RSP),%RDI

(208) 0x42e9ca MOV	0xe8(%RSP),%R9

(208) 0x42e9d2 VSUBSD	(%RBX,%R12,8),%XMM13,%XMM14

(208) 0x42e9d8 ADD	%RCX,%RSI

(208) 0x42e9db VMOVSD	(%R11,%RSI,8),%XMM0

(208) 0x42e9e1 MOV	0xb0(%RSP),%R13

(208) 0x42e9e9 ADD	%RCX,%RDI

(208) 0x42e9ec ADD	%RCX,%R9

(208) 0x42e9ef VADDSD	(%RBX,%RDI,8),%XMM14,%XMM15

(208) 0x42e9f4 VSUBSD	(%R11,%R9,8),%XMM0,%XMM1

(208) 0x42e9fa MOV	0xe0(%RSP),%RBX

(208) 0x42ea02 ADD	%RCX,%R13

(208) 0x42ea05 ADD	%RCX,%R8

(208) 0x42ea08 VADDSD	(%R14,%R8,8),%XMM12,%XMM4

(208) 0x42ea0e LEA	(%RBX,%R13,8),%R10

(208) 0x42ea12 MOV	0xf0(%RSP),%R11

(208) 0x42ea1a VFMADD132SD	(%R10),%XMM1,%XMM13

(208) 0x42ea1f ADD	%RCX,%R11

(208) 0x42ea22 VSUBSD	(%R14,%R11,8),%XMM4,%XMM5

(208) 0x42ea28 VDIVSD	%XMM15,%XMM13,%XMM6

(208) 0x42ea2d VDIVSD	%XMM5,%XMM15,%XMM2

(208) 0x42ea31 VMOVSD	%XMM2,(%RAX)

(208) 0x42ea35 VMOVSD	%XMM6,(%R10)

(208) 0x42ea3a MOV	0xd0(%RSP),%R13D

(208) 0x42ea42 INC	%R15

(208) 0x42ea45 CMP	%R15D,0x70(%RSP)

(208) 0x42ea4a JLE	42ea70

(208) 0x42ea4c MOV	0x68(%RSP),%ECX

(208) 0x42ea50 MOV	0x6c(%RSP),%R14D

(208) 0x42ea55 MOV	0x74(%RSP),%EDX

(208) 0x42ea59 MOV	%R14D,0xd4(%RSP)

(208) 0x42ea61 SUB	%R13D,%ECX

(208) 0x42ea64 JMP	42e3a0

0x42ea69 NOPL	(%RAX)

0x42ea70 VZEROUPPER

0x42ea73 LEA	-0x28(%RBP),%RSP

0x42ea77 POP	%RBX

0x42ea78 POP	%R12

0x42ea7a POP	%R13

0x42ea7c POP	%R14

0x42ea7e POP	%R15

0x42ea80 POP	%RBP

0x42ea81 RET

0x42ea82 NOPW	(%RAX,%RAX,1)

(208) 0x42ea88 MOV	0xd4(%RSP),%ECX

(208) 0x42ea8f XOR	%R12D,%R12D

(208) 0x42ea92 JMP	42e6a5

0x42ea97 INC	%ECX

0x42ea99 XOR	%EDX,%EDX

0x42ea9b JMP	42e325

Coverage (%)	Name	Source Location	Module
○97.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.41	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.50 to 3.00 cycles (5.17x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	83
nb uops	93
loop length	296
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67
cycles	6.10	11.93	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x34(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42ea97 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x74(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x6c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,0xd4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42e325 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x85>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	83
nb uops	93
loop length	296
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67
cycles	6.10	11.93	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x34(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42ea97 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42ea73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x74(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x6c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10D,0xd4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42e325 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x85>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.59	1.03
▼Loop 208 - advec_cell.cpp:210-216 - exec–	0.00	0.01
○Loop 209 - advec_cell.cpp:211-216 - exec	3.59	1.03

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code