OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:146-150 [...]	Coverage (incl. loops): 1.28% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 146 - 150

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42dd60 PUSH	%RBP

0x42dd61 MOV	%RSP,%RBP

0x42dd64 PUSH	%R15

0x42dd66 PUSH	%R14

0x42dd68 PUSH	%R13

0x42dd6a PUSH	%R12

0x42dd6c PUSH	%RBX

0x42dd6d AND	$-0x40,%RSP

0x42dd71 ADD	$-0x80,%RSP

0x42dd75 MOV	0x28(%RDI),%EAX

0x42dd78 MOV	0x2c(%RDI),%EDX

0x42dd7b MOV	0x20(%RDI),%EBX

0x42dd7e ADD	$0x4,%EDX

0x42dd81 LEA	-0x1(%RBX),%ECX

0x42dd84 LEA	-0x1(%RAX),%R12D

0x42dd88 MOV	%EDX,0x3c(%RSP)

0x42dd8c MOV	%ECX,0x38(%RSP)

0x42dd90 MOV	0x24(%RDI),%ESI

0x42dd93 CMP	%EDX,%R12D

0x42dd96 JGE	42e26b

0x42dd9c MOV	%EDX,%EBX

0x42dd9e LEA	0x4(%RSI),%R15D

0x42dda2 SUB	%R12D,%EBX

0x42dda5 CMP	%R15D,%ECX

0x42dda8 JGE	42e26b

0x42ddae MOV	%RDI,%R14

0x42ddb1 MOV	%R15D,%EDI

0x42ddb4 SUB	%ECX,%EDI

0x42ddb6 MOV	%EDI,0x68(%RSP)

0x42ddba CALL	404630 <omp_get_num_threads@plt>

0x42ddbf MOV	%EAX,%R13D

0x42ddc2 CALL	404520 <omp_get_thread_num@plt>

0x42ddc7 MOV	%EAX,%R8D

0x42ddca MOV	0x68(%RSP),%EAX

0x42ddce XOR	%EDX,%EDX

0x42ddd0 IMUL	%EBX,%EAX

0x42ddd3 DIV	%R13D

0x42ddd6 MOV	%EAX,%EDI

0x42ddd8 CMP	%EDX,%R8D

0x42dddb JB	42e28c

0x42dde1 IMUL	%EDI,%R8D

0x42dde5 LEA	(%R8,%RDX,1),%R13D

0x42dde9 LEA	(%RDI,%R13,1),%R9D

0x42dded MOV	%R9D,0x34(%RSP)

0x42ddf2 CMP	%R9D,%R13D

0x42ddf5 JAE	42e26b

0x42ddfb XOR	%EDX,%EDX

0x42ddfd MOV	%R13D,%EAX

0x42de00 DIVL	0x68(%RSP)

0x42de04 MOV	0x38(%RSP),%R10D

0x42de09 MOV	(%R14),%R11

0x42de0c MOV	0x10(%R14),%RBX

0x42de10 MOV	%R11,0x28(%RSP)

0x42de15 MOV	%RBX,0x18(%RSP)

0x42de1a MOV	%R15D,%ECX

0x42de1d MOV	0x8(%R14),%R15

0x42de21 MOV	0x18(%R14),%R14

0x42de25 MOV	%R15,0x20(%RSP)

0x42de2a MOV	%R14,0x10(%RSP)

0x42de2f ADD	%EDX,%R10D

0x42de32 SUB	%R10D,%ECX

0x42de35 ADD	%R12D,%EAX

0x42de38 CMP	%ECX,%EDI

0x42de3a CMOVBE	%EDI,%ECX

0x42de3d MOV	%R10D,0x6c(%RSP)

0x42de42 LEA	(%R13,%RCX,1),%R15D

0x42de47 MOVSXD	%EAX,%RDX

0x42de4a CMP	%R15D,%R13D

0x42de4d JAE	42e24f

0x42de53 NOPL	(%RAX,%RAX,1)

  (205) 0x42de58 MOV	0x18(%RSP),%RAX

  (205) 0x42de5d MOV	0x20(%RSP),%R8

  (205) 0x42de62 MOV	0x28(%RSP),%RSI

  (205) 0x42de67 MOV	0x10(%RAX),%R11

  (205) 0x42de6b MOV	(%R8),%R9

  (205) 0x42de6e LEA	0x1(%RDX),%R12

  (205) 0x42de72 MOV	(%RSI),%RDI

  (205) 0x42de75 MOV	%R11,0x70(%RSP)

  (205) 0x42de7a MOV	0x10(%RSI),%R14

  (205) 0x42de7e MOV	(%RAX),%R11

  (205) 0x42de81 MOV	0x10(%RSP),%RSI

  (205) 0x42de86 MOV	%R12,0x40(%RSP)

  (205) 0x42de8b IMUL	%R9,%R12

  (205) 0x42de8f IMUL	%RDX,%RDI

  (205) 0x42de93 IMUL	%RDX,%R11

  (205) 0x42de97 IMUL	(%RSI),%RDX

  (205) 0x42de9b MOV	0x10(%R8),%RBX

  (205) 0x42de9f MOV	%R12,%R10

  (205) 0x42dea2 MOV	0x10(%RSI),%R8

  (205) 0x42dea6 MOV	%RDX,0x60(%RSP)

  (205) 0x42deab SUB	%R9,%R10

  (205) 0x42deae LEA	-0x1(%RCX),%EDX

  (205) 0x42deb1 MOV	%RDI,0x48(%RSP)

  (205) 0x42deb6 MOV	%R10,0x50(%RSP)

  (205) 0x42debb MOV	%R11,0x58(%RSP)

  (205) 0x42dec0 MOV	%R8,0x78(%RSP)

  (205) 0x42dec5 CMP	$0x6,%EDX

  (205) 0x42dec8 JBE	42e280

  (205) 0x42dece MOVSXD	0x6c(%RSP),%RAX

  (205) 0x42ded3 MOV	0x70(%RSP),%RSI

  (205) 0x42ded8 LEA	(%RDI,%RAX,1),%RDI

  (205) 0x42dedc LEA	(%R10,%RAX,1),%R8

  (205) 0x42dee0 LEA	(%R11,%RAX,1),%R11

  (205) 0x42dee4 MOV	0x60(%RSP),%R10

  (205) 0x42dee9 LEA	(%R14,%RDI,8),%RDX

  (205) 0x42deed LEA	(%RSI,%R11,8),%RDI

  (205) 0x42def1 MOV	0x78(%RSP),%R11

  (205) 0x42def6 LEA	(%R12,%RAX,1),%R9

  (205) 0x42defa ADD	%R10,%RAX

  (205) 0x42defd LEA	(%R11,%RAX,8),%RSI

  (205) 0x42df01 MOV	%ECX,%R11D

  (205) 0x42df04 SHR	$0x3,%R11D

  (205) 0x42df08 SAL	$0x6,%R11

  (205) 0x42df0c LEA	-0x40(%R11),%R10

  (205) 0x42df10 SHR	$0x6,%R10

  (205) 0x42df14 INC	%R10

  (205) 0x42df17 LEA	(%RBX,%R9,8),%R9

  (205) 0x42df1b LEA	(%RBX,%R8,8),%R8

  (205) 0x42df1f XOR	%EAX,%EAX

  (205) 0x42df21 AND	$0x3,%R10D

  (205) 0x42df25 JE	42dfc5

  (205) 0x42df2b CMP	$0x1,%R10

  (205) 0x42df2f JE	42df8e

  (205) 0x42df31 CMP	$0x2,%R10

  (205) 0x42df35 JE	42df60

  (205) 0x42df37 VMOVUPD	(%RDX),%ZMM0

  (205) 0x42df3d MOV	$0x40,%EAX

  (205) 0x42df42 VADDPD	(%R9),%ZMM0,%ZMM1

  (205) 0x42df48 VSUBPD	(%R8),%ZMM1,%ZMM2

  (205) 0x42df4e VMOVUPD	%ZMM2,(%RDI)

  (205) 0x42df54 VMOVUPD	(%RDX),%ZMM3

  (205) 0x42df5a VMOVUPD	%ZMM3,(%RSI)

  (205) 0x42df60 VMOVUPD	(%RDX,%RAX,1),%ZMM4

  (205) 0x42df67 VADDPD	(%R9,%RAX,1),%ZMM4,%ZMM5

  (205) 0x42df6e VSUBPD	(%R8,%RAX,1),%ZMM5,%ZMM6

  (205) 0x42df75 VMOVUPD	%ZMM6,(%RDI,%RAX,1)

  (205) 0x42df7c VMOVUPD	(%RDX,%RAX,1),%ZMM7

  (205) 0x42df83 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

  (205) 0x42df8a ADD	$0x40,%RAX

  (205) 0x42df8e VMOVUPD	(%RDX,%RAX,1),%ZMM8

  (205) 0x42df95 VADDPD	(%R9,%RAX,1),%ZMM8,%ZMM9

  (205) 0x42df9c VSUBPD	(%R8,%RAX,1),%ZMM9,%ZMM10

  (205) 0x42dfa3 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

  (205) 0x42dfaa VMOVUPD	(%RDX,%RAX,1),%ZMM11

  (205) 0x42dfb1 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

  (205) 0x42dfb8 ADD	$0x40,%RAX

  (205) 0x42dfbc CMP	%RAX,%R11

  (205) 0x42dfbf JE	42e08e

    (206) 0x42dfc5 VMOVUPD	(%RDX,%RAX,1),%ZMM12

    (206) 0x42dfcc VADDPD	(%R9,%RAX,1),%ZMM12,%ZMM13

    (206) 0x42dfd3 VSUBPD	(%R8,%RAX,1),%ZMM13,%ZMM14

    (206) 0x42dfda VMOVUPD	%ZMM14,(%RDI,%RAX,1)

    (206) 0x42dfe1 VMOVUPD	(%RDX,%RAX,1),%ZMM15

    (206) 0x42dfe8 VMOVUPD	%ZMM15,(%RSI,%RAX,1)

    (206) 0x42dfef VMOVUPD	0x40(%RDX,%RAX,1),%ZMM0

    (206) 0x42dff7 VADDPD	0x40(%R9,%RAX,1),%ZMM0,%ZMM1

    (206) 0x42dfff VSUBPD	0x40(%R8,%RAX,1),%ZMM1,%ZMM2

    (206) 0x42e007 VMOVUPD	%ZMM2,0x40(%RDI,%RAX,1)

    (206) 0x42e00f VMOVUPD	0x40(%RDX,%RAX,1),%ZMM3

    (206) 0x42e017 VMOVUPD	%ZMM3,0x40(%RSI,%RAX,1)

    (206) 0x42e01f VMOVUPD	0x80(%RDX,%RAX,1),%ZMM4

    (206) 0x42e027 VADDPD	0x80(%R9,%RAX,1),%ZMM4,%ZMM5

    (206) 0x42e02f VSUBPD	0x80(%R8,%RAX,1),%ZMM5,%ZMM6

    (206) 0x42e037 VMOVUPD	%ZMM6,0x80(%RDI,%RAX,1)

    (206) 0x42e03f VMOVUPD	0x80(%RDX,%RAX,1),%ZMM7

    (206) 0x42e047 VMOVUPD	%ZMM7,0x80(%RSI,%RAX,1)

    (206) 0x42e04f VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM8

    (206) 0x42e057 VADDPD	0xc0(%R9,%RAX,1),%ZMM8,%ZMM9

    (206) 0x42e05f VSUBPD	0xc0(%R8,%RAX,1),%ZMM9,%ZMM10

    (206) 0x42e067 VMOVUPD	%ZMM10,0xc0(%RDI,%RAX,1)

    (206) 0x42e06f VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM11

    (206) 0x42e077 VMOVUPD	%ZMM11,0xc0(%RSI,%RAX,1)

    (206) 0x42e07f ADD	$0x100,%RAX

    (206) 0x42e085 CMP	%RAX,%R11

    (206) 0x42e088 JNE	42dfc5

  (205) 0x42e08e MOV	0x6c(%RSP),%ESI

  (205) 0x42e092 MOV	%ECX,%R10D

  (205) 0x42e095 AND	$-0x8,%R10D

  (205) 0x42e099 ADD	%R10D,%ESI

  (205) 0x42e09c ADD	%R10D,%R13D

  (205) 0x42e09f TEST	$0x7,%CL

  (205) 0x42e0a2 JE	42e219

  (205) 0x42e0a8 SUB	%R10D,%ECX

  (205) 0x42e0ab LEA	-0x1(%RCX),%EDX

  (205) 0x42e0ae CMP	$0x2,%EDX

  (205) 0x42e0b1 JBE	42e12f

  (205) 0x42e0b3 MOVSXD	0x6c(%RSP),%R11

  (205) 0x42e0b8 MOV	0x48(%RSP),%R9

  (205) 0x42e0bd LEA	(%R12,%R11,1),%RDI

  (205) 0x42e0c1 ADD	%R11,%R9

  (205) 0x42e0c4 ADD	%R10,%R9

  (205) 0x42e0c7 LEA	(%R14,%R9,8),%R8

  (205) 0x42e0cb VMOVUPD	(%R8),%YMM12

  (205) 0x42e0d0 ADD	%R10,%RDI

  (205) 0x42e0d3 MOV	0x50(%RSP),%RAX

  (205) 0x42e0d8 VADDPD	(%RBX,%RDI,8),%YMM12,%YMM13

  (205) 0x42e0dd ADD	%R11,%RAX

  (205) 0x42e0e0 ADD	%R10,%RAX

  (205) 0x42e0e3 MOV	0x58(%RSP),%RDX

  (205) 0x42e0e8 VSUBPD	(%RBX,%RAX,8),%YMM13,%YMM14

  (205) 0x42e0ed ADD	%R11,%RDX

  (205) 0x42e0f0 MOV	0x70(%RSP),%R9

  (205) 0x42e0f5 ADD	%R10,%RDX

  (205) 0x42e0f8 VMOVUPD	%YMM14,(%R9,%RDX,8)

  (205) 0x42e0fe VMOVUPD	(%R8),%YMM15

  (205) 0x42e103 MOV	0x60(%RSP),%R8

  (205) 0x42e108 ADD	%R8,%R11

  (205) 0x42e10b ADD	%R10,%R11

  (205) 0x42e10e MOV	0x78(%RSP),%R10

  (205) 0x42e113 VMOVUPD	%YMM15,(%R10,%R11,8)

  (205) 0x42e119 MOV	%ECX,%R11D

  (205) 0x42e11c AND	$-0x4,%R11D

  (205) 0x42e120 ADD	%R11D,%ESI

  (205) 0x42e123 ADD	%R11D,%R13D

  (205) 0x42e126 AND	$0x3,%ECX

  (205) 0x42e129 JE	42e219

  (205) 0x42e12f MOVSXD	%ESI,%RAX

  (205) 0x42e132 MOV	0x48(%RSP),%R9

  (205) 0x42e137 LEA	(%R12,%RAX,1),%RDI

  (205) 0x42e13b VMOVSD	(%RBX,%RDI,8),%XMM0

  (205) 0x42e140 LEA	(%R9,%RAX,1),%RCX

  (205) 0x42e144 LEA	(%R14,%RCX,8),%RDX

  (205) 0x42e148 VADDSD	(%RDX),%XMM0,%XMM1

  (205) 0x42e14c MOV	0x50(%RSP),%R10

  (205) 0x42e151 MOV	0x58(%RSP),%R8

  (205) 0x42e156 LEA	(%R10,%RAX,1),%RCX

  (205) 0x42e15a VSUBSD	(%RBX,%RCX,8),%XMM1,%XMM2

  (205) 0x42e15f MOV	0x70(%RSP),%RDI

  (205) 0x42e164 LEA	(%R8,%RAX,1),%R11

  (205) 0x42e168 VMOVSD	%XMM2,(%RDI,%R11,8)

  (205) 0x42e16e MOV	0x60(%RSP),%R11

  (205) 0x42e173 VMOVSD	(%RDX),%XMM3

  (205) 0x42e177 MOV	0x78(%RSP),%RDX

  (205) 0x42e17c ADD	%R11,%RAX

  (205) 0x42e17f VMOVSD	%XMM3,(%RDX,%RAX,8)

  (205) 0x42e184 LEA	0x1(%R13),%EAX

  (205) 0x42e188 CMP	%R15D,%EAX

  (205) 0x42e18b JAE	42e219

  (205) 0x42e191 LEA	0x1(%RSI),%EAX

  (205) 0x42e194 CLTQ

  (205) 0x42e196 LEA	(%R12,%RAX,1),%RDI

  (205) 0x42e19a VMOVSD	(%RBX,%RDI,8),%XMM4

  (205) 0x42e19f LEA	(%R9,%RAX,1),%RCX

  (205) 0x42e1a3 LEA	(%R14,%RCX,8),%RDX

  (205) 0x42e1a7 VADDSD	(%RDX),%XMM4,%XMM5

  (205) 0x42e1ab LEA	(%R10,%RAX,1),%RDI

  (205) 0x42e1af LEA	(%R8,%RAX,1),%RCX

  (205) 0x42e1b3 VSUBSD	(%RBX,%RDI,8),%XMM5,%XMM6

  (205) 0x42e1b8 MOV	0x70(%RSP),%RDI

  (205) 0x42e1bd ADD	%R11,%RAX

  (205) 0x42e1c0 VMOVSD	%XMM6,(%RDI,%RCX,8)

  (205) 0x42e1c5 VMOVSD	(%RDX),%XMM7

  (205) 0x42e1c9 MOV	%R11,%RCX

  (205) 0x42e1cc MOV	0x78(%RSP),%R11

  (205) 0x42e1d1 ADD	$0x2,%R13D

  (205) 0x42e1d5 VMOVSD	%XMM7,(%R11,%RAX,8)

  (205) 0x42e1db CMP	%R15D,%R13D

  (205) 0x42e1de JAE	42e219

  (205) 0x42e1e0 ADD	$0x2,%ESI

  (205) 0x42e1e3 MOVSXD	%ESI,%R13

  (205) 0x42e1e6 ADD	%R13,%R12

  (205) 0x42e1e9 VMOVSD	(%RBX,%R12,8),%XMM8

  (205) 0x42e1ef ADD	%R13,%R9

  (205) 0x42e1f2 LEA	(%R14,%R9,8),%RSI

  (205) 0x42e1f6 VADDSD	(%RSI),%XMM8,%XMM9

  (205) 0x42e1fa ADD	%R13,%R10

  (205) 0x42e1fd ADD	%R13,%R8

  (205) 0x42e200 VSUBSD	(%RBX,%R10,8),%XMM9,%XMM10

  (205) 0x42e206 ADD	%R13,%RCX

  (205) 0x42e209 VMOVSD	%XMM10,(%RDI,%R8,8)

  (205) 0x42e20f VMOVSD	(%RSI),%XMM11

  (205) 0x42e213 VMOVSD	%XMM11,(%R11,%RCX,8)

  (205) 0x42e219 MOV	0x40(%RSP),%RDX

  (205) 0x42e21e MOV	%R15D,%R13D

  (205) 0x42e221 CMP	%EDX,0x3c(%RSP)

  (205) 0x42e225 JLE	42e268

  (205) 0x42e227 MOV	0x34(%RSP),%EDI

  (205) 0x42e22b MOV	0x68(%RSP),%ECX

  (205) 0x42e22f SUB	%R13D,%EDI

  (205) 0x42e232 CMP	%ECX,%EDI

  (205) 0x42e234 MOV	0x38(%RSP),%R15D

  (205) 0x42e239 CMOVBE	%EDI,%ECX

  (205) 0x42e23c MOV	%R15D,0x6c(%RSP)

  (205) 0x42e241 LEA	(%R13,%RCX,1),%R15D

  (205) 0x42e246 CMP	%R15D,%R13D

  (205) 0x42e249 JB	42de58

(207) 0x42e24f LEA	0x1(%RDX),%R12

(207) 0x42e253 MOV	%R12,0x40(%RSP)

(207) 0x42e258 MOV	0x40(%RSP),%RDX

(207) 0x42e25d CMP	%EDX,0x3c(%RSP)

(207) 0x42e261 JG	42e227

0x42e263 NOPL	(%RAX,%RAX,1)

0x42e268 VZEROUPPER

0x42e26b LEA	-0x28(%RBP),%RSP

0x42e26f POP	%RBX

0x42e270 POP	%R12

0x42e272 POP	%R13

0x42e274 POP	%R14

0x42e276 POP	%R15

0x42e278 POP	%RBP

0x42e279 RET

0x42e27a NOPW	(%RAX,%RAX,1)

  (205) 0x42e280 MOV	0x6c(%RSP),%ESI

  (205) 0x42e284 XOR	%R10D,%R10D

  (205) 0x42e287 JMP	42e0a8

0x42e28c INC	%EDI

0x42e28e XOR	%EDX,%EDX

0x42e290 JMP	42dde1

0x42e295 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.54	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.46	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.00 to 3.00 cycles (5.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:150
DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	85
nb uops	96
loop length	297
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00
cycles	7.20	12.33	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	12.33
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

1% of peak load performance is reached (3.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 12.33 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 42dd60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42e28c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x52c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVL 0x68(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVBE %EDI,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R10D,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R13,%RCX,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42e24f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4ef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42dde1 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:150
DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	85
nb uops	96
loop length	297
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00
cycles	7.20	12.33	6.00	6.00	8.50	7.27	7.20	8.50	8.50	8.50	7.33	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	12.33
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

1% of peak load performance is reached (3.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42dd60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42e28c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x52c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42e26b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVL 0x68(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x38(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SUB %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVBE %EDI,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R10D,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R13,%RCX,1),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CMP %R15D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42e24f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4ef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42dde1 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.28	0.37
▼Loop 207 - advec_cell.cpp:148-150 - exec–	0.00	0.00
▼Loop 205 - advec_cell.cpp:148-150 - exec–	0.00	0.01
○Loop 206 - advec_cell.cpp:149-150 - exec	1.28	0.37

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code