OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.48% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42d570 PUSH	%RBP

0x42d571 MOV	%RSP,%RBP

0x42d574 PUSH	%R15

0x42d576 PUSH	%R14

0x42d578 PUSH	%R13

0x42d57a PUSH	%R12

0x42d57c PUSH	%RBX

0x42d57d MOV	%RDI,%RBX

0x42d580 AND	$-0x40,%RSP

0x42d584 SUB	$0xc0,%RSP

0x42d58b MOV	0x30(%RDI),%EAX

0x42d58e MOV	0x34(%RDI),%EDX

0x42d591 MOV	0x28(%RDI),%ESI

0x42d594 ADD	$0x4,%EDX

0x42d597 DEC	%ESI

0x42d599 LEA	-0x1(%RAX),%R12D

0x42d59d MOV	%EDX,0x5c(%RSP)

0x42d5a1 MOV	%ESI,0x58(%RSP)

0x42d5a5 MOV	0x2c(%RDI),%EDI

0x42d5a8 CMP	%EDX,%R12D

0x42d5ab JGE	42dd23

0x42d5b1 MOV	%EDX,%R14D

0x42d5b4 LEA	0x4(%RDI),%R15D

0x42d5b8 SUB	%R12D,%R14D

0x42d5bb CMP	%R15D,%ESI

0x42d5be JGE	42dd23

0x42d5c4 MOV	%R15D,%ECX

0x42d5c7 SUB	%ESI,%ECX

0x42d5c9 MOV	%ECX,0x98(%RSP)

0x42d5d0 CALL	404630 <omp_get_num_threads@plt>

0x42d5d5 MOV	%EAX,%R13D

0x42d5d8 CALL	404520 <omp_get_thread_num@plt>

0x42d5dd MOV	%EAX,%R8D

0x42d5e0 MOV	0x98(%RSP),%EAX

0x42d5e7 XOR	%EDX,%EDX

0x42d5e9 IMUL	%R14D,%EAX

0x42d5ed DIV	%R13D

0x42d5f0 MOV	%EAX,%ECX

0x42d5f2 CMP	%EDX,%R8D

0x42d5f5 JB	42dd57

0x42d5fb IMUL	%ECX,%R8D

0x42d5ff LEA	(%R8,%RDX,1),%R14D

0x42d603 LEA	(%RCX,%R14,1),%R9D

0x42d607 MOV	%R9D,0x54(%RSP)

0x42d60c CMP	%R9D,%R14D

0x42d60f JAE	42dd23

0x42d615 MOV	%R14D,%EAX

0x42d618 XOR	%EDX,%EDX

0x42d61a DIVL	0x98(%RSP)

0x42d621 MOV	0x58(%RSP),%R10D

0x42d626 MOV	(%RBX),%RDI

0x42d629 MOV	0x8(%RBX),%R13

0x42d62d MOV	0x18(%RBX),%R8

0x42d631 MOV	%RDI,0x48(%RSP)

0x42d636 MOV	%R13,0x38(%RSP)

0x42d63b MOV	%R8,0x30(%RSP)

0x42d640 MOV	%R15D,%ESI

0x42d643 MOV	0x10(%RBX),%R15

0x42d647 MOV	0x20(%RBX),%RBX

0x42d64b MOV	%R15,0x40(%RSP)

0x42d650 MOV	%RBX,0x28(%RSP)

0x42d655 LEA	(%RDX,%R10,1),%R11D

0x42d659 MOV	%R11D,0xa8(%RSP)

0x42d661 ADD	%R12D,%EAX

0x42d664 SUB	%R11D,%ESI

0x42d667 MOVSXD	%EAX,%RDX

0x42d66a NOPW	(%RAX,%RAX,1)

(203) 0x42d670 CMP	%ESI,%ECX

(203) 0x42d672 CMOVBE	%ECX,%ESI

(203) 0x42d675 LEA	(%R14,%RSI,1),%R12D

(203) 0x42d679 MOV	%R12D,0x9c(%RSP)

(203) 0x42d681 CMP	%R12D,%R14D

(203) 0x42d684 JAE	42dd38

(203) 0x42d68a MOV	0x40(%RSP),%R9

(203) 0x42d68f MOV	0x48(%RSP),%RCX

(203) 0x42d694 MOV	(%R9),%RAX

(203) 0x42d697 MOV	0x38(%RSP),%R10

(203) 0x42d69c MOV	0x30(%RSP),%R8

(203) 0x42d6a1 MOV	0x10(%RCX),%R11

(203) 0x42d6a5 MOV	(%RCX),%RDI

(203) 0x42d6a8 LEA	0x1(%RDX),%RCX

(203) 0x42d6ac MOV	0x10(%R8),%R12

(203) 0x42d6b0 MOV	%RCX,0x60(%RSP)

(203) 0x42d6b5 MOV	0x10(%R9),%R13

(203) 0x42d6b9 IMUL	%RAX,%RCX

(203) 0x42d6bd MOV	0x28(%RSP),%R9

(203) 0x42d6c2 MOV	0x10(%R10),%R15

(203) 0x42d6c6 MOV	(%R8),%R8

(203) 0x42d6c9 MOV	(%R10),%R10

(203) 0x42d6cc IMUL	%RDX,%RDI

(203) 0x42d6d0 IMUL	%RDX,%R10

(203) 0x42d6d4 IMUL	%RDX,%R8

(203) 0x42d6d8 IMUL	(%R9),%RDX

(203) 0x42d6dc MOV	%RCX,%RBX

(203) 0x42d6df SUB	%RAX,%RBX

(203) 0x42d6e2 MOV	0x10(%R9),%RAX

(203) 0x42d6e6 MOV	%R12,0xb0(%RSP)

(203) 0x42d6ee MOV	%RDX,0x90(%RSP)

(203) 0x42d6f6 MOV	%RDX,%R12

(203) 0x42d6f9 LEA	-0x1(%RSI),%EDX

(203) 0x42d6fc MOV	%R11,0x88(%RSP)

(203) 0x42d704 MOV	%RDI,0xa0(%RSP)

(203) 0x42d70c MOV	%RCX,0x68(%RSP)

(203) 0x42d711 MOV	%RBX,0x70(%RSP)

(203) 0x42d716 MOV	%R10,0x78(%RSP)

(203) 0x42d71b MOV	%R8,0x80(%RSP)

(203) 0x42d723 MOV	%RAX,0xb8(%RSP)

(203) 0x42d72b CMP	$0x6,%EDX

(203) 0x42d72e JBE	42dd48

(203) 0x42d734 MOVSXD	0xa8(%RSP),%RAX

(203) 0x42d73c LEA	(%RDI,%RAX,1),%RDI

(203) 0x42d740 LEA	(%RCX,%RAX,1),%R9

(203) 0x42d744 LEA	(%RBX,%RAX,1),%RBX

(203) 0x42d748 LEA	(%R8,%RAX,1),%R8

(203) 0x42d74c LEA	(%R11,%RDI,8),%R11

(203) 0x42d750 LEA	0x1(%R10,%RAX,1),%RDI

(203) 0x42d755 ADD	%R12,%RAX

(203) 0x42d758 MOV	0xb8(%RSP),%R12

(203) 0x42d760 SAL	$0x3,%RDI

(203) 0x42d764 LEA	(%R13,%R9,8),%RDX

(203) 0x42d769 LEA	(%R15,%RDI,1),%R10

(203) 0x42d76d LEA	-0x8(%R15,%RDI,1),%R9

(203) 0x42d772 LEA	(%R12,%RAX,8),%RDI

(203) 0x42d776 MOV	%ESI,%R12D

(203) 0x42d779 LEA	(%R13,%RBX,8),%RCX

(203) 0x42d77e SHR	$0x3,%R12D

(203) 0x42d782 MOV	0xb0(%RSP),%RBX

(203) 0x42d78a SAL	$0x6,%R12

(203) 0x42d78e LEA	(%RBX,%R8,8),%R8

(203) 0x42d792 LEA	-0x40(%R12),%RBX

(203) 0x42d797 SHR	$0x6,%RBX

(203) 0x42d79b INC	%RBX

(203) 0x42d79e XOR	%EAX,%EAX

(203) 0x42d7a0 AND	$0x3,%EBX

(203) 0x42d7a3 JE	42d8a7

(203) 0x42d7a9 CMP	$0x1,%RBX

(203) 0x42d7ad JE	42d84f

(203) 0x42d7b3 CMP	$0x2,%RBX

(203) 0x42d7b7 JE	42d800

(203) 0x42d7b9 VMOVUPD	(%R11),%ZMM0

(203) 0x42d7bf VMOVUPD	(%RCX),%ZMM3

(203) 0x42d7c5 VADDPD	(%RDX),%ZMM0,%ZMM1

(203) 0x42d7cb VADDPD	(%R9),%ZMM3,%ZMM4

(203) 0x42d7d1 MOV	$0x40,%EAX

(203) 0x42d7d6 VADDPD	(%R10),%ZMM1,%ZMM2

(203) 0x42d7dc VSUBPD	%ZMM4,%ZMM2,%ZMM5

(203) 0x42d7e2 VMOVUPD	%ZMM5,(%R8)

(203) 0x42d7e8 VMOVUPD	(%RCX),%ZMM6

(203) 0x42d7ee VSUBPD	(%RDX),%ZMM6,%ZMM7

(203) 0x42d7f4 VADDPD	%ZMM5,%ZMM7,%ZMM8

(203) 0x42d7fa VMOVUPD	%ZMM8,(%RDI)

(203) 0x42d800 VMOVUPD	(%R11,%RAX,1),%ZMM9

(203) 0x42d807 VMOVUPD	(%RCX,%RAX,1),%ZMM12

(203) 0x42d80e VADDPD	(%RDX,%RAX,1),%ZMM9,%ZMM10

(203) 0x42d815 VADDPD	(%R9,%RAX,1),%ZMM12,%ZMM13

(203) 0x42d81c VADDPD	(%R10,%RAX,1),%ZMM10,%ZMM11

(203) 0x42d823 VSUBPD	%ZMM13,%ZMM11,%ZMM14

(203) 0x42d829 VMOVUPD	%ZMM14,(%R8,%RAX,1)

(203) 0x42d830 VMOVUPD	(%RCX,%RAX,1),%ZMM15

(203) 0x42d837 VSUBPD	(%RDX,%RAX,1),%ZMM15,%ZMM0

(203) 0x42d83e VADDPD	%ZMM14,%ZMM0,%ZMM1

(203) 0x42d844 VMOVUPD	%ZMM1,(%RDI,%RAX,1)

(203) 0x42d84b ADD	$0x40,%RAX

(203) 0x42d84f VMOVUPD	(%R11,%RAX,1),%ZMM2

(203) 0x42d856 VMOVUPD	(%RCX,%RAX,1),%ZMM5

(203) 0x42d85d VADDPD	(%RDX,%RAX,1),%ZMM2,%ZMM3

(203) 0x42d864 VADDPD	(%R9,%RAX,1),%ZMM5,%ZMM6

(203) 0x42d86b VADDPD	(%R10,%RAX,1),%ZMM3,%ZMM4

(203) 0x42d872 VSUBPD	%ZMM6,%ZMM4,%ZMM7

(203) 0x42d878 VMOVUPD	%ZMM7,(%R8,%RAX,1)

(203) 0x42d87f VMOVUPD	(%RCX,%RAX,1),%ZMM8

(203) 0x42d886 VSUBPD	(%RDX,%RAX,1),%ZMM8,%ZMM9

(203) 0x42d88d VADDPD	%ZMM7,%ZMM9,%ZMM10

(203) 0x42d893 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(203) 0x42d89a ADD	$0x40,%RAX

(203) 0x42d89e CMP	%RAX,%R12

(203) 0x42d8a1 JE	42d9fd

  (204) 0x42d8a7 VMOVUPD	(%R11,%RAX,1),%ZMM11

  (204) 0x42d8ae VMOVUPD	(%RCX,%RAX,1),%ZMM14

  (204) 0x42d8b5 VADDPD	(%RDX,%RAX,1),%ZMM11,%ZMM12

  (204) 0x42d8bc VADDPD	(%R9,%RAX,1),%ZMM14,%ZMM15

  (204) 0x42d8c3 VADDPD	(%R10,%RAX,1),%ZMM12,%ZMM13

  (204) 0x42d8ca VSUBPD	%ZMM15,%ZMM13,%ZMM0

  (204) 0x42d8d0 VMOVUPD	%ZMM0,(%R8,%RAX,1)

  (204) 0x42d8d7 VMOVUPD	(%RCX,%RAX,1),%ZMM1

  (204) 0x42d8de VSUBPD	(%RDX,%RAX,1),%ZMM1,%ZMM2

  (204) 0x42d8e5 VADDPD	%ZMM0,%ZMM2,%ZMM3

  (204) 0x42d8eb VMOVUPD	%ZMM3,(%RDI,%RAX,1)

  (204) 0x42d8f2 VMOVUPD	0x40(%R11,%RAX,1),%ZMM4

  (204) 0x42d8fa VMOVUPD	0x40(%RCX,%RAX,1),%ZMM7

  (204) 0x42d902 VADDPD	0x40(%RDX,%RAX,1),%ZMM4,%ZMM5

  (204) 0x42d90a VADDPD	0x40(%R9,%RAX,1),%ZMM7,%ZMM8

  (204) 0x42d912 VADDPD	0x40(%R10,%RAX,1),%ZMM5,%ZMM6

  (204) 0x42d91a VSUBPD	%ZMM8,%ZMM6,%ZMM9

  (204) 0x42d920 VMOVUPD	%ZMM9,0x40(%R8,%RAX,1)

  (204) 0x42d928 VMOVUPD	0x40(%RCX,%RAX,1),%ZMM10

  (204) 0x42d930 VSUBPD	0x40(%RDX,%RAX,1),%ZMM10,%ZMM11

  (204) 0x42d938 VADDPD	%ZMM9,%ZMM11,%ZMM12

  (204) 0x42d93e VMOVUPD	%ZMM12,0x40(%RDI,%RAX,1)

  (204) 0x42d946 VMOVUPD	0x80(%R11,%RAX,1),%ZMM13

  (204) 0x42d94e VMOVUPD	0x80(%RCX,%RAX,1),%ZMM0

  (204) 0x42d956 VADDPD	0x80(%RDX,%RAX,1),%ZMM13,%ZMM14

  (204) 0x42d95e VADDPD	0x80(%R9,%RAX,1),%ZMM0,%ZMM1

  (204) 0x42d966 VADDPD	0x80(%R10,%RAX,1),%ZMM14,%ZMM15

  (204) 0x42d96e VSUBPD	%ZMM1,%ZMM15,%ZMM2

  (204) 0x42d974 VMOVUPD	%ZMM2,0x80(%R8,%RAX,1)

  (204) 0x42d97c VMOVUPD	0x80(%RCX,%RAX,1),%ZMM3

  (204) 0x42d984 VSUBPD	0x80(%RDX,%RAX,1),%ZMM3,%ZMM4

  (204) 0x42d98c VADDPD	%ZMM2,%ZMM4,%ZMM5

  (204) 0x42d992 VMOVUPD	%ZMM5,0x80(%RDI,%RAX,1)

  (204) 0x42d99a VMOVUPD	0xc0(%R11,%RAX,1),%ZMM6

  (204) 0x42d9a2 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM9

  (204) 0x42d9aa VADDPD	0xc0(%RDX,%RAX,1),%ZMM6,%ZMM7

  (204) 0x42d9b2 VADDPD	0xc0(%R9,%RAX,1),%ZMM9,%ZMM10

  (204) 0x42d9ba VADDPD	0xc0(%R10,%RAX,1),%ZMM7,%ZMM8

  (204) 0x42d9c2 VSUBPD	%ZMM10,%ZMM8,%ZMM11

  (204) 0x42d9c8 VMOVUPD	%ZMM11,0xc0(%R8,%RAX,1)

  (204) 0x42d9d0 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM12

  (204) 0x42d9d8 VSUBPD	0xc0(%RDX,%RAX,1),%ZMM12,%ZMM13

  (204) 0x42d9e0 VADDPD	%ZMM11,%ZMM13,%ZMM14

  (204) 0x42d9e6 VMOVUPD	%ZMM14,0xc0(%RDI,%RAX,1)

  (204) 0x42d9ee ADD	$0x100,%RAX

  (204) 0x42d9f4 CMP	%RAX,%R12

  (204) 0x42d9f7 JNE	42d8a7

(203) 0x42d9fd MOV	0xa8(%RSP),%EDX

(203) 0x42da04 MOV	%ESI,%R11D

(203) 0x42da07 AND	$-0x8,%R11D

(203) 0x42da0b LEA	(%R11,%RDX,1),%ECX

(203) 0x42da0f ADD	%R11D,%R14D

(203) 0x42da12 TEST	$0x7,%SIL

(203) 0x42da16 JE	42dce3

(203) 0x42da1c SUB	%R11D,%ESI

(203) 0x42da1f LEA	-0x1(%RSI),%R10D

(203) 0x42da23 CMP	$0x2,%R10D

(203) 0x42da27 JBE	42daf6

(203) 0x42da2d MOVSXD	0xa8(%RSP),%R12

(203) 0x42da35 MOV	0x68(%RSP),%R9

(203) 0x42da3a MOV	0x70(%RSP),%RDI

(203) 0x42da3f LEA	(%R9,%R12,1),%R8

(203) 0x42da43 ADD	%R11,%R8

(203) 0x42da46 LEA	(%RDI,%R12,1),%RBX

(203) 0x42da4a MOV	0x78(%RSP),%R10

(203) 0x42da4f MOV	0xa0(%RSP),%RDI

(203) 0x42da57 LEA	(%R13,%R8,8),%RAX

(203) 0x42da5c ADD	%R11,%RBX

(203) 0x42da5f VMOVUPD	(%RAX),%YMM15

(203) 0x42da63 LEA	(%R10,%R12,1),%R9

(203) 0x42da67 LEA	(%R13,%RBX,8),%RDX

(203) 0x42da6c LEA	(%RDI,%R12,1),%R10

(203) 0x42da70 MOV	0x88(%RSP),%RBX

(203) 0x42da78 ADD	%R11,%R10

(203) 0x42da7b LEA	0x1(%R11,%R9,1),%R8

(203) 0x42da80 VADDPD	(%RBX,%R10,8),%YMM15,%YMM0

(203) 0x42da86 VMOVUPD	(%R15,%R8,8),%YMM1

(203) 0x42da8c MOV	0x80(%RSP),%R9

(203) 0x42da94 VSUBPD	-0x8(%R15,%R8,8),%YMM0,%YMM2

(203) 0x42da9b VSUBPD	(%RDX),%YMM1,%YMM3

(203) 0x42da9f LEA	(%R9,%R12,1),%R8

(203) 0x42daa3 MOV	0xb0(%RSP),%RDI

(203) 0x42daab VADDPD	%YMM3,%YMM2,%YMM4

(203) 0x42daaf ADD	%R11,%R8

(203) 0x42dab2 VMOVUPD	%YMM4,(%RDI,%R8,8)

(203) 0x42dab8 VMOVUPD	(%RDX),%YMM5

(203) 0x42dabc VSUBPD	(%RAX),%YMM5,%YMM6

(203) 0x42dac0 MOV	0x90(%RSP),%RAX

(203) 0x42dac8 VADDPD	%YMM4,%YMM6,%YMM7

(203) 0x42dacc ADD	%RAX,%R12

(203) 0x42dacf ADD	%R11,%R12

(203) 0x42dad2 MOV	0xb8(%RSP),%R11

(203) 0x42dada VMOVUPD	%YMM7,(%R11,%R12,8)

(203) 0x42dae0 MOV	%ESI,%R12D

(203) 0x42dae3 AND	$-0x4,%R12D

(203) 0x42dae7 ADD	%R12D,%ECX

(203) 0x42daea ADD	%R12D,%R14D

(203) 0x42daed AND	$0x3,%ESI

(203) 0x42daf0 JE	42dce3

(203) 0x42daf6 MOV	0x78(%RSP),%RBX

(203) 0x42dafb MOV	0x68(%RSP),%R11

(203) 0x42db00 MOV	0x70(%RSP),%R12

(203) 0x42db05 LEA	0x1(%RCX),%EAX

(203) 0x42db08 MOVSXD	%ECX,%RDX

(203) 0x42db0b CLTQ

(203) 0x42db0d LEA	(%R11,%RDX,1),%RSI

(203) 0x42db11 LEA	(%R12,%RDX,1),%R10

(203) 0x42db15 LEA	(%RBX,%RAX,1),%R9

(203) 0x42db19 LEA	(%R13,%RSI,8),%RDI

(203) 0x42db1e LEA	(%R13,%R10,8),%R8

(203) 0x42db23 LEA	(%R15,%R9,8),%RSI

(203) 0x42db27 MOV	0xa0(%RSP),%R10

(203) 0x42db2f MOV	%RSI,0xa8(%RSP)

(203) 0x42db37 MOV	0x88(%RSP),%RSI

(203) 0x42db3f LEA	(%R10,%RDX,1),%R9

(203) 0x42db43 VMOVSD	(%RSI,%R9,8),%XMM8

(203) 0x42db49 MOV	0xa8(%RSP),%RSI

(203) 0x42db51 VADDSD	(%RDI),%XMM8,%XMM9

(203) 0x42db55 VMOVSD	(%RSI),%XMM11

(203) 0x42db59 LEA	(%RBX,%RDX,1),%R9

(203) 0x42db5d VSUBSD	(%R15,%R9,8),%XMM9,%XMM10

(203) 0x42db63 VSUBSD	(%R8),%XMM11,%XMM12

(203) 0x42db68 MOV	0x80(%RSP),%R9

(203) 0x42db70 MOV	0xb0(%RSP),%RSI

(203) 0x42db78 VADDSD	%XMM12,%XMM10,%XMM13

(203) 0x42db7d ADD	%RDX,%R9

(203) 0x42db80 VMOVSD	%XMM13,(%RSI,%R9,8)

(203) 0x42db86 VMOVSD	(%R8),%XMM14

(203) 0x42db8b MOV	0x90(%RSP),%R9

(203) 0x42db93 VSUBSD	(%RDI),%XMM14,%XMM15

(203) 0x42db97 MOV	0xb8(%RSP),%RDI

(203) 0x42db9f ADD	%R9,%RDX

(203) 0x42dba2 VADDSD	%XMM13,%XMM15,%XMM0

(203) 0x42dba7 MOV	0x9c(%RSP),%R8D

(203) 0x42dbaf VMOVSD	%XMM0,(%RDI,%RDX,8)

(203) 0x42dbb4 LEA	0x1(%R14),%EDX

(203) 0x42dbb8 CMP	%R8D,%EDX

(203) 0x42dbbb JAE	42dce3

(203) 0x42dbc1 LEA	(%RAX,%R11,1),%RSI

(203) 0x42dbc5 LEA	0x2(%RCX),%EDX

(203) 0x42dbc8 LEA	(%R13,%RSI,8),%RDI

(203) 0x42dbcd MOVSXD	%EDX,%RSI

(203) 0x42dbd0 MOV	0x88(%RSP),%RDX

(203) 0x42dbd8 ADD	%RAX,%R10

(203) 0x42dbdb VMOVSD	(%RDX,%R10,8),%XMM2

(203) 0x42dbe1 MOV	0xa8(%RSP),%R10

(203) 0x42dbe9 VADDSD	(%RDI),%XMM2,%XMM1

(203) 0x42dbed LEA	(%RAX,%R12,1),%R9

(203) 0x42dbf1 VMOVSD	(%R10),%XMM4

(203) 0x42dbf6 LEA	(%R13,%R9,8),%R8

(203) 0x42dbfb LEA	(%RBX,%RSI,1),%R9

(203) 0x42dbff LEA	(%R15,%R9,8),%R9

(203) 0x42dc03 VADDSD	(%R8),%XMM4,%XMM5

(203) 0x42dc08 VADDSD	(%R9),%XMM1,%XMM3

(203) 0x42dc0d MOV	0x80(%RSP),%R10

(203) 0x42dc15 MOV	%RSI,0x78(%RSP)

(203) 0x42dc1a VSUBSD	%XMM5,%XMM3,%XMM6

(203) 0x42dc1e MOV	0xb0(%RSP),%RDX

(203) 0x42dc26 MOV	%R10,%RSI

(203) 0x42dc29 ADD	%RAX,%RSI

(203) 0x42dc2c VMOVSD	%XMM6,(%RDX,%RSI,8)

(203) 0x42dc31 VMOVSD	(%R8),%XMM7

(203) 0x42dc36 MOV	0x90(%RSP),%RSI

(203) 0x42dc3e VSUBSD	(%RDI),%XMM7,%XMM8

(203) 0x42dc42 MOV	0xb8(%RSP),%R8

(203) 0x42dc4a ADD	%RSI,%RAX

(203) 0x42dc4d VADDSD	%XMM6,%XMM8,%XMM9

(203) 0x42dc51 ADD	$0x2,%R14D

(203) 0x42dc55 VMOVSD	%XMM9,(%R8,%RAX,8)

(203) 0x42dc5b MOV	0x9c(%RSP),%EAX

(203) 0x42dc62 CMP	%EAX,%R14D

(203) 0x42dc65 JAE	42dce3

(203) 0x42dc67 MOV	%R11,%R14

(203) 0x42dc6a MOV	0xa0(%RSP),%RDI

(203) 0x42dc72 MOV	0x78(%RSP),%R11

(203) 0x42dc77 MOV	0x88(%RSP),%RSI

(203) 0x42dc7f ADD	%R11,%RDI

(203) 0x42dc82 VMOVSD	(%RSI,%RDI,8),%XMM10

(203) 0x42dc87 ADD	%R11,%R14

(203) 0x42dc8a LEA	(%R13,%R14,8),%RAX

(203) 0x42dc8f ADD	%R11,%R12

(203) 0x42dc92 VADDSD	(%RAX),%XMM10,%XMM11

(203) 0x42dc96 LEA	(%R13,%R12,8),%R13

(203) 0x42dc9b ADD	$0x3,%ECX

(203) 0x42dc9e VMOVSD	(%R13),%XMM13

(203) 0x42dca4 MOVSXD	%ECX,%RCX

(203) 0x42dca7 ADD	%RBX,%RCX

(203) 0x42dcaa VADDSD	(%R15,%RCX,8),%XMM11,%XMM12

(203) 0x42dcb0 VADDSD	(%R9),%XMM13,%XMM14

(203) 0x42dcb5 ADD	%R11,%R10

(203) 0x42dcb8 VSUBSD	%XMM14,%XMM12,%XMM15

(203) 0x42dcbd VMOVSD	%XMM15,(%RDX,%R10,8)

(203) 0x42dcc3 VMOVSD	(%R13),%XMM0

(203) 0x42dcc9 MOV	0x90(%RSP),%RDX

(203) 0x42dcd1 VSUBSD	(%RAX),%XMM0,%XMM2

(203) 0x42dcd5 ADD	%R11,%RDX

(203) 0x42dcd8 VADDSD	%XMM15,%XMM2,%XMM1

(203) 0x42dcdd VMOVSD	%XMM1,(%R8,%RDX,8)

(203) 0x42dce3 MOV	0x9c(%RSP),%R14D

(203) 0x42dceb MOV	0x60(%RSP),%RDX

(203) 0x42dcf0 CMP	%EDX,0x5c(%RSP)

(203) 0x42dcf4 JLE	42dd20

(203) 0x42dcf6 MOV	0x54(%RSP),%ECX

(203) 0x42dcfa MOV	0x58(%RSP),%R15D

(203) 0x42dcff MOV	0x98(%RSP),%ESI

(203) 0x42dd06 MOV	%R15D,0xa8(%RSP)

(203) 0x42dd0e SUB	%R14D,%ECX

(203) 0x42dd11 JMP	42d670

0x42dd16 NOPW	%CS:(%RAX,%RAX,1)

0x42dd20 VZEROUPPER

0x42dd23 LEA	-0x28(%RBP),%RSP

0x42dd27 POP	%RBX

0x42dd28 POP	%R12

0x42dd2a POP	%R13

0x42dd2c POP	%R14

0x42dd2e POP	%R15

0x42dd30 POP	%RBP

0x42dd31 RET

0x42dd32 NOPW	(%RAX,%RAX,1)

(203) 0x42dd38 LEA	0x1(%RDX),%RSI

(203) 0x42dd3c MOV	%RSI,0x60(%RSP)

(203) 0x42dd41 JMP	42dceb

0x42dd43 NOPL	(%RAX,%RAX,1)

(203) 0x42dd48 MOV	0xa8(%RSP),%ECX

(203) 0x42dd4f XOR	%R11D,%R11D

(203) 0x42dd52 JMP	42da1c

0x42dd57 INC	%ECX

0x42dd59 XOR	%EDX,%EDX

0x42dd5b JMP	42d5fb

Coverage (%)	Name	Source Location	Module
○97.57	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.43	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.33 to 3.00 cycles (5.11x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.33 to 14.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	92
loop length	304
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.33
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42d570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x98(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42dd57 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x98(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x58(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R11D,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42d5fb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.33 to 14.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	92
loop length	304
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.33
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42d570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x98(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42dd57 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42dd23 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x98(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x58(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R11D,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42d5fb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.48	0.43
▼Loop 203 - advec_cell.cpp:136-140 - exec–	0.00	0.01
○Loop 204 - advec_cell.cpp:139-140 - exec	1.48	0.43

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code