OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42ce00 PUSH	%RBP

0x42ce01 MOV	%RSP,%RBP

0x42ce04 PUSH	%R15

0x42ce06 PUSH	%R14

0x42ce08 PUSH	%R13

0x42ce0a PUSH	%R12

0x42ce0c PUSH	%RBX

0x42ce0d MOV	%RDI,%RBX

0x42ce10 AND	$-0x40,%RSP

0x42ce14 SUB	$0xc0,%RSP

0x42ce1b MOV	0x38(%RDI),%EAX

0x42ce1e MOV	0x3c(%RDI),%EDX

0x42ce21 MOV	0x30(%RDI),%ESI

0x42ce24 ADD	$0x2,%EDX

0x42ce27 INC	%ESI

0x42ce29 LEA	0x1(%RAX),%R12D

0x42ce2d MOV	%EDX,0x48(%RSP)

0x42ce31 MOV	%ESI,0x44(%RSP)

0x42ce35 MOV	0x34(%RDI),%EDI

0x42ce38 CMP	%EDX,%R12D

0x42ce3b JGE	42d543

0x42ce41 MOV	%EDX,%R14D

0x42ce44 LEA	0x2(%RDI),%R15D

0x42ce48 SUB	%R12D,%R14D

0x42ce4b CMP	%R15D,%ESI

0x42ce4e JGE	42d543

0x42ce54 MOV	%R15D,%ECX

0x42ce57 SUB	%ESI,%ECX

0x42ce59 MOV	%ECX,0x4c(%RSP)

0x42ce5d CALL	404630 <omp_get_num_threads@plt>

0x42ce62 MOV	%EAX,%R13D

0x42ce65 CALL	404520 <omp_get_thread_num@plt>

0x42ce6a MOV	%EAX,%R8D

0x42ce6d MOV	0x4c(%RSP),%EAX

0x42ce71 XOR	%EDX,%EDX

0x42ce73 IMUL	%R14D,%EAX

0x42ce77 DIV	%R13D

0x42ce7a MOV	%EAX,%ECX

0x42ce7c CMP	%EDX,%R8D

0x42ce7f JB	42d567

0x42ce85 IMUL	%ECX,%R8D

0x42ce89 LEA	(%R8,%RDX,1),%R13D

0x42ce8d LEA	(%RCX,%R13,1),%R9D

0x42ce91 MOV	%R9D,0x40(%RSP)

0x42ce96 CMP	%R9D,%R13D

0x42ce99 JAE	42d543

0x42ce9f MOV	%R13D,%EAX

0x42cea2 XOR	%EDX,%EDX

0x42cea4 DIVL	0x4c(%RSP)

0x42cea8 MOV	0x44(%RSP),%R10D

0x42cead MOV	(%RBX),%R11

0x42ceb0 MOV	0x20(%RBX),%RSI

0x42ceb4 MOV	0x10(%RBX),%RDI

0x42ceb8 MOV	0x28(%RBX),%R14

0x42cebc MOV	%R11,0x38(%RSP)

0x42cec1 MOV	%RSI,0x30(%RSP)

0x42cec6 MOV	%RDI,0x28(%RSP)

0x42cecb MOV	%R15D,%R8D

0x42cece MOV	0x8(%RBX),%R15

0x42ced2 MOV	0x18(%RBX),%RBX

0x42ced6 MOV	%R14,0x18(%RSP)

0x42cedb MOV	%RBX,0x10(%RSP)

0x42cee0 MOV	%R15,0x20(%RSP)

0x42cee5 ADD	%EDX,%R10D

0x42cee8 MOV	%R10D,0x84(%RSP)

0x42cef0 ADD	%R12D,%EAX

0x42cef3 SUB	%R10D,%R8D

0x42cef6 MOVSXD	%EAX,%R15

0x42cef9 NOPL	(%RAX)

(201) 0x42cf00 CMP	%R8D,%ECX

(201) 0x42cf03 MOV	%R8D,%ESI

(201) 0x42cf06 CMOVBE	%ECX,%ESI

(201) 0x42cf09 LEA	(%R13,%RSI,1),%R12D

(201) 0x42cf0e MOV	%R12D,0x80(%RSP)

(201) 0x42cf16 CMP	%R12D,%R13D

(201) 0x42cf19 JAE	42d515

(201) 0x42cf1f MOV	0x38(%RSP),%RCX

(201) 0x42cf24 MOV	0x30(%RSP),%R8

(201) 0x42cf29 MOV	0x28(%RSP),%RDX

(201) 0x42cf2e MOV	0x10(%R8),%R9

(201) 0x42cf32 MOV	0x10(%RCX),%R12

(201) 0x42cf36 MOV	(%RCX),%RBX

(201) 0x42cf39 MOV	(%R8),%RDI

(201) 0x42cf3c MOV	0x20(%RSP),%R10

(201) 0x42cf41 MOV	0x18(%RSP),%RCX

(201) 0x42cf46 MOV	0x10(%RSP),%R8

(201) 0x42cf4b MOV	0x10(%RDX),%RAX

(201) 0x42cf4f MOV	0x10(%R10),%R14

(201) 0x42cf53 MOV	(%RDX),%R11

(201) 0x42cf56 MOV	%R9,0x88(%RSP)

(201) 0x42cf5e MOV	0x10(%R8),%RDX

(201) 0x42cf62 MOV	(%R10),%R10

(201) 0x42cf65 MOV	(%RCX),%R9

(201) 0x42cf68 MOV	(%R8),%R8

(201) 0x42cf6b IMUL	%R15,%RBX

(201) 0x42cf6f IMUL	%R15,%RDI

(201) 0x42cf73 IMUL	%R15,%R11

(201) 0x42cf77 IMUL	%R15,%R10

(201) 0x42cf7b IMUL	%R15,%R9

(201) 0x42cf7f IMUL	%R15,%R8

(201) 0x42cf83 MOV	%R14,0x90(%RSP)

(201) 0x42cf8b MOV	0x10(%RCX),%R14

(201) 0x42cf8f MOV	%RAX,0xb0(%RSP)

(201) 0x42cf97 LEA	-0x1(%RSI),%EAX

(201) 0x42cf9a MOV	%R12,0x68(%RSP)

(201) 0x42cf9f MOV	%RBX,0x98(%RSP)

(201) 0x42cfa7 MOV	%RDI,0x70(%RSP)

(201) 0x42cfac MOV	%R11,0x50(%RSP)

(201) 0x42cfb1 MOV	%R10,0x78(%RSP)

(201) 0x42cfb6 MOV	%R14,0xa8(%RSP)

(201) 0x42cfbe MOV	%R9,0x58(%RSP)

(201) 0x42cfc3 MOV	%RDX,0xb8(%RSP)

(201) 0x42cfcb MOV	%R8,0x60(%RSP)

(201) 0x42cfd0 CMP	$0x6,%EAX

(201) 0x42cfd3 JBE	42d558

(201) 0x42cfd9 MOVSXD	0x84(%RSP),%RAX

(201) 0x42cfe1 LEA	(%RDI,%RAX,1),%RDX

(201) 0x42cfe5 MOV	0x88(%RSP),%RDI

(201) 0x42cfed LEA	(%RBX,%RAX,1),%RBX

(201) 0x42cff1 LEA	(%R12,%RBX,8),%RCX

(201) 0x42cff5 MOV	0xb0(%RSP),%RBX

(201) 0x42cffd LEA	(%RDI,%RDX,8),%R12

(201) 0x42d001 LEA	(%R11,%RAX,1),%RDX

(201) 0x42d005 MOV	0x90(%RSP),%RDI

(201) 0x42d00d SAL	$0x3,%RDX

(201) 0x42d011 LEA	(%R10,%RAX,1),%R10

(201) 0x42d015 LEA	(%RBX,%RDX,1),%R11

(201) 0x42d019 LEA	0x8(%RBX,%RDX,1),%RBX

(201) 0x42d01e LEA	(%RDI,%R10,8),%RDX

(201) 0x42d022 LEA	(%R9,%RAX,1),%RDI

(201) 0x42d026 SAL	$0x3,%RDI

(201) 0x42d02a ADD	%R8,%RAX

(201) 0x42d02d LEA	(%R14,%RDI,1),%R10

(201) 0x42d031 LEA	0x8(%R14,%RDI,1),%R9

(201) 0x42d036 MOV	0xb8(%RSP),%RDI

(201) 0x42d03e SAL	$0x3,%RAX

(201) 0x42d042 LEA	(%RDI,%RAX,1),%R8

(201) 0x42d046 LEA	0x8(%RDI,%RAX,1),%RDI

(201) 0x42d04b MOV	%ESI,%EAX

(201) 0x42d04d SHR	$0x3,%EAX

(201) 0x42d050 MOV	%RAX,%R14

(201) 0x42d053 SAL	$0x6,%RAX

(201) 0x42d057 MOV	%RAX,0xa0(%RSP)

(201) 0x42d05f XOR	%EAX,%EAX

(201) 0x42d061 AND	$0x1,%R14D

(201) 0x42d065 JE	42d0ca

(201) 0x42d067 VMOVUPD	(%R12),%ZMM0

(201) 0x42d06e VMOVUPD	(%R10),%ZMM3

(201) 0x42d074 VMULPD	(%RCX),%ZMM0,%ZMM1

(201) 0x42d07a VSUBPD	(%R9),%ZMM3,%ZMM5

(201) 0x42d080 VADDPD	(%R8),%ZMM0,%ZMM6

(201) 0x42d086 CMPQ	$0x40,0xa0(%RSP)

(201) 0x42d08f MOV	$0x40,%EAX

(201) 0x42d094 VSUBPD	(%RBX),%ZMM1,%ZMM2

(201) 0x42d09a VFMADD132PD	(%RDX),%ZMM5,%ZMM1

(201) 0x42d0a0 VSUBPD	(%RDI),%ZMM6,%ZMM7

(201) 0x42d0a6 VADDPD	(%R11),%ZMM2,%ZMM4

(201) 0x42d0ac VDIVPD	%ZMM7,%ZMM4,%ZMM8

(201) 0x42d0b2 VDIVPD	%ZMM4,%ZMM1,%ZMM9

(201) 0x42d0b8 VMOVUPD	%ZMM8,(%RCX)

(201) 0x42d0be VMOVUPD	%ZMM9,(%RDX)

(201) 0x42d0c4 JE	42d1a9

(201) 0x42d0ca MOV	0xb8(%RSP),%R14

  (202) 0x42d0d2 VMOVUPD	(%R12,%RAX,1),%ZMM10

  (202) 0x42d0d9 VMOVUPD	(%R10,%RAX,1),%ZMM14

  (202) 0x42d0e0 VMULPD	(%RCX,%RAX,1),%ZMM10,%ZMM11

  (202) 0x42d0e7 VSUBPD	(%R9,%RAX,1),%ZMM14,%ZMM15

  (202) 0x42d0ee VADDPD	(%R8,%RAX,1),%ZMM10,%ZMM0

  (202) 0x42d0f5 VSUBPD	(%RBX,%RAX,1),%ZMM11,%ZMM12

  (202) 0x42d0fc VFMADD132PD	(%RDX,%RAX,1),%ZMM15,%ZMM11

  (202) 0x42d103 VSUBPD	(%RDI,%RAX,1),%ZMM0,%ZMM1

  (202) 0x42d10a VADDPD	(%R11,%RAX,1),%ZMM12,%ZMM13

  (202) 0x42d111 VDIVPD	%ZMM13,%ZMM11,%ZMM4

  (202) 0x42d117 VDIVPD	%ZMM1,%ZMM13,%ZMM2

  (202) 0x42d11d VMOVUPD	%ZMM2,(%RCX,%RAX,1)

  (202) 0x42d124 VMOVUPD	%ZMM4,(%RDX,%RAX,1)

  (202) 0x42d12b VMOVUPD	0x40(%R12,%RAX,1),%ZMM5

  (202) 0x42d133 VMOVUPD	0x40(%R10,%RAX,1),%ZMM8

  (202) 0x42d13b VMULPD	0x40(%RCX,%RAX,1),%ZMM5,%ZMM6

  (202) 0x42d143 VSUBPD	0x40(%R9,%RAX,1),%ZMM8,%ZMM9

  (202) 0x42d14b VADDPD	0x40(%R8,%RAX,1),%ZMM5,%ZMM10

  (202) 0x42d153 VSUBPD	0x40(%RBX,%RAX,1),%ZMM6,%ZMM3

  (202) 0x42d15b VFMADD132PD	0x40(%RDX,%RAX,1),%ZMM9,%ZMM6

  (202) 0x42d163 VSUBPD	0x40(%RDI,%RAX,1),%ZMM10,%ZMM11

  (202) 0x42d16b VADDPD	0x40(%R11,%RAX,1),%ZMM3,%ZMM7

  (202) 0x42d173 VDIVPD	%ZMM11,%ZMM7,%ZMM12

  (202) 0x42d179 VDIVPD	%ZMM7,%ZMM6,%ZMM13

  (202) 0x42d17f VMOVUPD	%ZMM12,0x40(%RCX,%RAX,1)

  (202) 0x42d187 VMOVUPD	%ZMM13,0x40(%RDX,%RAX,1)

  (202) 0x42d18f SUB	$-0x80,%RAX

  (202) 0x42d193 CMP	%RAX,0xa0(%RSP)

  (202) 0x42d19b JNE	42d0d2

(201) 0x42d1a1 MOV	%R14,0xb8(%RSP)

(201) 0x42d1a9 MOV	0x84(%RSP),%ECX

(201) 0x42d1b0 MOV	%ESI,%R12D

(201) 0x42d1b3 AND	$-0x8,%R12D

(201) 0x42d1b7 LEA	(%R12,%RCX,1),%ECX

(201) 0x42d1bb ADD	%R12D,%R13D

(201) 0x42d1be TEST	$0x7,%SIL

(201) 0x42d1c2 JE	42d50d

(201) 0x42d1c8 SUB	%R12D,%ESI

(201) 0x42d1cb LEA	-0x1(%RSI),%R11D

(201) 0x42d1cf CMP	$0x2,%R11D

(201) 0x42d1d3 JBE	42d2c4

(201) 0x42d1d9 MOVSXD	0x84(%RSP),%RDX

(201) 0x42d1e1 MOV	0x98(%RSP),%RBX

(201) 0x42d1e9 MOV	0x78(%RSP),%RDI

(201) 0x42d1ee LEA	(%RBX,%RDX,1),%R10

(201) 0x42d1f2 LEA	(%RDI,%RDX,1),%RAX

(201) 0x42d1f6 MOV	0x68(%RSP),%R9

(201) 0x42d1fb MOV	0x90(%RSP),%RBX

(201) 0x42d203 ADD	%R12,%R10

(201) 0x42d206 ADD	%R12,%RAX

(201) 0x42d209 LEA	(%R9,%R10,8),%R14

(201) 0x42d20d MOV	0x50(%RSP),%R8

(201) 0x42d212 LEA	(%RBX,%RAX,8),%R10

(201) 0x42d216 MOV	0x58(%RSP),%R9

(201) 0x42d21b MOV	0x60(%RSP),%RDI

(201) 0x42d220 MOV	0x70(%RSP),%RAX

(201) 0x42d225 LEA	(%R8,%RDX,1),%R11

(201) 0x42d229 LEA	(%R9,%RDX,1),%R8

(201) 0x42d22d LEA	(%RDI,%RDX,1),%R9

(201) 0x42d231 ADD	%RAX,%RDX

(201) 0x42d234 ADD	%R12,%R11

(201) 0x42d237 ADD	%R12,%R8

(201) 0x42d23a ADD	%R12,%R9

(201) 0x42d23d ADD	%R12,%RDX

(201) 0x42d240 MOV	0x88(%RSP),%R12

(201) 0x42d248 MOV	0xb8(%RSP),%RBX

(201) 0x42d250 VMOVUPD	(%R12,%RDX,8),%YMM14

(201) 0x42d256 MOV	0xb0(%RSP),%RDX

(201) 0x42d25e VMULPD	(%R14),%YMM14,%YMM15

(201) 0x42d263 VADDPD	(%RBX,%R9,8),%YMM14,%YMM5

(201) 0x42d269 VSUBPD	0x8(%RBX,%R9,8),%YMM5,%YMM6

(201) 0x42d270 VADDPD	(%RDX,%R11,8),%YMM15,%YMM0

(201) 0x42d276 VSUBPD	0x8(%RDX,%R11,8),%YMM0,%YMM2

(201) 0x42d27d MOV	0xa8(%RSP),%R11

(201) 0x42d285 VMOVUPD	0x8(%R11,%R8,8),%YMM4

(201) 0x42d28c VMOVUPD	(%R11,%R8,8),%YMM1

(201) 0x42d292 VFMSUB132PD	(%R10),%YMM4,%YMM15

(201) 0x42d297 VDIVPD	%YMM6,%YMM2,%YMM3

(201) 0x42d29b VADDPD	%YMM15,%YMM1,%YMM7

(201) 0x42d2a0 VDIVPD	%YMM2,%YMM7,%YMM8

(201) 0x42d2a4 VMOVUPD	%YMM3,(%R14)

(201) 0x42d2a9 MOV	%ESI,%R14D

(201) 0x42d2ac AND	$-0x4,%R14D

(201) 0x42d2b0 ADD	%R14D,%ECX

(201) 0x42d2b3 ADD	%R14D,%R13D

(201) 0x42d2b6 AND	$0x3,%ESI

(201) 0x42d2b9 VMOVUPD	%YMM8,(%R10)

(201) 0x42d2be JE	42d50d

(201) 0x42d2c4 MOV	0x70(%RSP),%R9

(201) 0x42d2c9 MOVSXD	%ECX,%RDX

(201) 0x42d2cc MOV	0x98(%RSP),%RSI

(201) 0x42d2d4 MOV	0x88(%RSP),%RAX

(201) 0x42d2dc ADD	%RDX,%R9

(201) 0x42d2df MOV	0x68(%RSP),%R8

(201) 0x42d2e4 VMOVSD	(%RAX,%R9,8),%XMM9

(201) 0x42d2ea LEA	(%RSI,%RDX,1),%R10

(201) 0x42d2ee LEA	(%R8,%R10,8),%RDI

(201) 0x42d2f2 VMULSD	(%RDI),%XMM9,%XMM10

(201) 0x42d2f6 MOV	0x50(%RSP),%RBX

(201) 0x42d2fb LEA	0x1(%RCX),%EAX

(201) 0x42d2fe MOV	0xb0(%RSP),%R11

(201) 0x42d306 CLTQ

(201) 0x42d308 LEA	(%RBX,%RDX,1),%R14

(201) 0x42d30c LEA	(%RAX,%RBX,1),%R12

(201) 0x42d310 VADDSD	(%R11,%R14,8),%XMM10,%XMM11

(201) 0x42d316 LEA	(%R11,%R12,8),%R10

(201) 0x42d31a MOV	0x58(%RSP),%R11

(201) 0x42d31f MOV	0xa8(%RSP),%R9

(201) 0x42d327 LEA	(%R11,%RDX,1),%R12

(201) 0x42d32b LEA	(%R11,%RAX,1),%R14

(201) 0x42d32f MOV	0x78(%RSP),%RSI

(201) 0x42d334 VMOVSD	(%R9,%R12,8),%XMM13

(201) 0x42d33a MOV	0x90(%RSP),%R8

(201) 0x42d342 MOV	0x60(%RSP),%R12

(201) 0x42d347 LEA	(%R9,%R14,8),%R9

(201) 0x42d34b VMOVSD	(%R9),%XMM14

(201) 0x42d350 MOV	0xb8(%RSP),%R14

(201) 0x42d358 ADD	%RDX,%RSI

(201) 0x42d35b LEA	(%R8,%RSI,8),%RSI

(201) 0x42d35f ADD	%R12,%RDX

(201) 0x42d362 VADDSD	(%R14,%RDX,8),%XMM9,%XMM15

(201) 0x42d368 VFMSUB132SD	(%RSI),%XMM14,%XMM10

(201) 0x42d36d LEA	(%R12,%RAX,1),%R8

(201) 0x42d371 LEA	(%R14,%R8,8),%R8

(201) 0x42d375 VSUBSD	(%R10),%XMM11,%XMM12

(201) 0x42d37a VSUBSD	(%R8),%XMM15,%XMM0

(201) 0x42d37f VADDSD	%XMM13,%XMM10,%XMM1

(201) 0x42d384 LEA	0x1(%R13),%EDX

(201) 0x42d388 VDIVSD	%XMM0,%XMM12,%XMM2

(201) 0x42d38c VDIVSD	%XMM12,%XMM1,%XMM4

(201) 0x42d391 VMOVSD	%XMM2,(%RDI)

(201) 0x42d395 MOV	0x80(%RSP),%EDI

(201) 0x42d39c VMOVSD	%XMM4,(%RSI)

(201) 0x42d3a0 CMP	%EDI,%EDX

(201) 0x42d3a2 JAE	42d50d

(201) 0x42d3a8 MOV	0x98(%RSP),%RSI

(201) 0x42d3b0 MOV	0x68(%RSP),%RDX

(201) 0x42d3b5 LEA	(%RAX,%RSI,1),%R14

(201) 0x42d3b9 MOV	0x70(%RSP),%RDI

(201) 0x42d3be LEA	(%RDX,%R14,8),%RSI

(201) 0x42d3c2 MOV	0x88(%RSP),%RDX

(201) 0x42d3ca LEA	(%RAX,%RDI,1),%R14

(201) 0x42d3ce VMOVSD	(%RDX,%R14,8),%XMM5

(201) 0x42d3d4 LEA	0x2(%RCX),%EDI

(201) 0x42d3d7 VMULSD	(%RSI),%XMM5,%XMM6

(201) 0x42d3db MOVSXD	%EDI,%RDX

(201) 0x42d3de MOV	0xb0(%RSP),%R14

(201) 0x42d3e6 LEA	(%RBX,%RDX,1),%RDI

(201) 0x42d3ea LEA	(%R14,%RDI,8),%RDI

(201) 0x42d3ee VSUBSD	(%RDI),%XMM6,%XMM3

(201) 0x42d3f2 MOV	0x90(%RSP),%R14

(201) 0x42d3fa VMOVSD	(%R9),%XMM8

(201) 0x42d3ff VADDSD	(%R10),%XMM3,%XMM7

(201) 0x42d404 MOV	0x78(%RSP),%R10

(201) 0x42d409 VADDSD	(%R8),%XMM5,%XMM10

(201) 0x42d40e ADD	%R10,%RAX

(201) 0x42d411 LEA	(%R14,%RAX,8),%RAX

(201) 0x42d415 MOV	0xa8(%RSP),%R14

(201) 0x42d41d LEA	(%R11,%RDX,1),%R10

(201) 0x42d421 LEA	(%R14,%R10,8),%R10

(201) 0x42d425 VSUBSD	(%R10),%XMM8,%XMM9

(201) 0x42d42a MOV	0xb8(%RSP),%R14

(201) 0x42d432 LEA	(%R12,%RDX,1),%R9

(201) 0x42d436 VFMADD132SD	(%RAX),%XMM9,%XMM6

(201) 0x42d43b LEA	(%R14,%R9,8),%R9

(201) 0x42d43f VSUBSD	(%R9),%XMM10,%XMM11

(201) 0x42d444 MOV	0x80(%RSP),%R8D

(201) 0x42d44c LEA	0x2(%R13),%R13D

(201) 0x42d450 VDIVSD	%XMM11,%XMM7,%XMM12

(201) 0x42d455 VDIVSD	%XMM7,%XMM6,%XMM13

(201) 0x42d459 VMOVSD	%XMM12,(%RSI)

(201) 0x42d45d VMOVSD	%XMM13,(%RAX)

(201) 0x42d461 CMP	%R8D,%R13D

(201) 0x42d464 JAE	42d50d

(201) 0x42d46a MOV	0x70(%RSP),%R14

(201) 0x42d46f MOV	0x88(%RSP),%R13

(201) 0x42d477 MOV	0x98(%RSP),%RSI

(201) 0x42d47f MOV	0x68(%RSP),%RAX

(201) 0x42d484 ADD	%RDX,%R14

(201) 0x42d487 VMOVSD	(%R13,%R14,8),%XMM14

(201) 0x42d48e ADD	%RDX,%RSI

(201) 0x42d491 LEA	(%RAX,%RSI,8),%R8

(201) 0x42d495 VMULSD	(%R8),%XMM14,%XMM15

(201) 0x42d49a ADD	$0x3,%ECX

(201) 0x42d49d MOVSXD	%ECX,%RCX

(201) 0x42d4a0 MOV	0xb0(%RSP),%RSI

(201) 0x42d4a8 ADD	%RCX,%RBX

(201) 0x42d4ab VSUBSD	(%RSI,%RBX,8),%XMM15,%XMM0

(201) 0x42d4b0 VMOVSD	(%R10),%XMM1

(201) 0x42d4b5 MOV	0xa8(%RSP),%R10

(201) 0x42d4bd VADDSD	(%RDI),%XMM0,%XMM2

(201) 0x42d4c1 ADD	%RCX,%R11

(201) 0x42d4c4 MOV	0x78(%RSP),%RDI

(201) 0x42d4c9 VSUBSD	(%R10,%R11,8),%XMM1,%XMM4

(201) 0x42d4cf MOV	0x90(%RSP),%RAX

(201) 0x42d4d7 ADD	%RDX,%RDI

(201) 0x42d4da VADDSD	(%R9),%XMM14,%XMM5

(201) 0x42d4df LEA	(%RAX,%RDI,8),%R13

(201) 0x42d4e3 VFMADD132SD	(%R13),%XMM4,%XMM15

(201) 0x42d4e9 MOV	0xb8(%RSP),%R9

(201) 0x42d4f1 ADD	%RCX,%R12

(201) 0x42d4f4 VSUBSD	(%R9,%R12,8),%XMM5,%XMM6

(201) 0x42d4fa VDIVSD	%XMM2,%XMM15,%XMM7

(201) 0x42d4fe VDIVSD	%XMM6,%XMM2,%XMM3

(201) 0x42d502 VMOVSD	%XMM3,(%R8)

(201) 0x42d507 VMOVSD	%XMM7,(%R13)

(201) 0x42d50d MOV	0x80(%RSP),%R13D

(201) 0x42d515 INC	%R15

(201) 0x42d518 CMP	%R15D,0x48(%RSP)

(201) 0x42d51d JLE	42d540

(201) 0x42d51f MOV	0x40(%RSP),%ECX

(201) 0x42d523 MOV	0x44(%RSP),%R14D

(201) 0x42d528 MOV	0x4c(%RSP),%R8D

(201) 0x42d52d MOV	%R14D,0x84(%RSP)

(201) 0x42d535 SUB	%R13D,%ECX

(201) 0x42d538 JMP	42cf00

0x42d53d NOPL	(%RAX)

0x42d540 VZEROUPPER

0x42d543 LEA	-0x28(%RBP),%RSP

0x42d547 POP	%RBX

0x42d548 POP	%R12

0x42d54a POP	%R13

0x42d54c POP	%R14

0x42d54e POP	%R15

0x42d550 POP	%RBP

0x42d551 RET

0x42d552 NOPW	(%RAX,%RAX,1)

(201) 0x42d558 MOV	0x84(%RSP),%ECX

(201) 0x42d55f XOR	%R12D,%R12D

(201) 0x42d562 JMP	42d1c8

0x42d567 INC	%ECX

0x42d569 XOR	%EDX,%EDX

0x42d56b JMP	42ce85

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.50 to 3.00 cycles (5.17x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	83
nb uops	93
loop length	292
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67
cycles	6.10	11.93	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42ce00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x34(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x4c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42d567 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x767>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x4c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x44(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42ce85 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x85>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.50 to 14.33 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	83
nb uops	93
loop length	292
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67
cycles	6.10	11.93	6.67	6.67	9.50	6.07	5.90	9.50	9.50	9.50	5.93	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.50
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

2% of peak load performance is reached (4.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42ce00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x34(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x4c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42d567 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x767>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42d543 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x743>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x4c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x44(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42ce85 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x85>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.55	1.02
▼Loop 201 - advec_cell.cpp:119-125 - exec–	0.00	0.00
○Loop 202 - advec_cell.cpp:120-125 - exec	3.55	1.02

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code