OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:54-58 [...]	Coverage (incl. loops): 1.26% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 54 - 58

--------------------------------------------------------------------------------

54: #pragma omp parallel for simd collapse(2)

55:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

56:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

57:           pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

58:           post_vol(i, j) = volume(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c8e0 PUSH	%RBP

0x42c8e1 MOV	%RSP,%RBP

0x42c8e4 PUSH	%R15

0x42c8e6 PUSH	%R14

0x42c8e8 PUSH	%R13

0x42c8ea PUSH	%R12

0x42c8ec PUSH	%RBX

0x42c8ed AND	$-0x40,%RSP

0x42c8f1 ADD	$-0x80,%RSP

0x42c8f5 MOV	0x28(%RDI),%EAX

0x42c8f8 MOV	0x2c(%RDI),%EDX

0x42c8fb MOV	0x20(%RDI),%EBX

0x42c8fe ADD	$0x4,%EDX

0x42c901 LEA	-0x1(%RBX),%ECX

0x42c904 LEA	-0x1(%RAX),%R12D

0x42c908 MOV	%EDX,0x44(%RSP)

0x42c90c MOV	%ECX,0x40(%RSP)

0x42c910 MOV	0x24(%RDI),%ESI

0x42c913 CMP	%EDX,%R12D

0x42c916 JGE	42cdcb

0x42c91c MOV	%EDX,%EBX

0x42c91e LEA	0x4(%RSI),%R15D

0x42c922 SUB	%R12D,%EBX

0x42c925 CMP	%R15D,%ECX

0x42c928 JGE	42cdcb

0x42c92e MOV	%RDI,%R14

0x42c931 MOV	%R15D,%EDI

0x42c934 SUB	%ECX,%EDI

0x42c936 MOV	%EDI,0x68(%RSP)

0x42c93a CALL	404630 <omp_get_num_threads@plt>

0x42c93f MOV	%EAX,%R13D

0x42c942 CALL	404520 <omp_get_thread_num@plt>

0x42c947 MOV	%EAX,%R8D

0x42c94a MOV	0x68(%RSP),%EAX

0x42c94e XOR	%EDX,%EDX

0x42c950 IMUL	%EBX,%EAX

0x42c953 DIV	%R13D

0x42c956 MOV	%EAX,%ESI

0x42c958 CMP	%EDX,%R8D

0x42c95b JB	42cdeb

0x42c961 IMUL	%ESI,%R8D

0x42c965 LEA	(%R8,%RDX,1),%R13D

0x42c969 LEA	(%RSI,%R13,1),%R9D

0x42c96d MOV	%R9D,0x3c(%RSP)

0x42c972 CMP	%R9D,%R13D

0x42c975 JAE	42cdcb

0x42c97b MOV	%R13D,%EAX

0x42c97e XOR	%EDX,%EDX

0x42c980 DIVL	0x68(%RSP)

0x42c984 MOV	0x40(%RSP),%R10D

0x42c989 MOV	(%R14),%R11

0x42c98c MOV	0x10(%R14),%RBX

0x42c990 MOV	%R11,0x30(%RSP)

0x42c995 MOV	%RBX,0x20(%RSP)

0x42c99a MOV	%R15D,%ECX

0x42c99d MOV	0x8(%R14),%R15

0x42c9a1 MOV	0x18(%R14),%R14

0x42c9a5 MOV	%R15,0x28(%RSP)

0x42c9aa MOV	%R14,0x18(%RSP)

0x42c9af ADD	%EDX,%R10D

0x42c9b2 MOV	%R10D,0x6c(%RSP)

0x42c9b7 ADD	%R12D,%EAX

0x42c9ba SUB	%R10D,%ECX

0x42c9bd MOVSXD	%EAX,%R12

(199) 0x42c9c0 CMP	%ECX,%ESI

(199) 0x42c9c2 CMOVBE	%ESI,%ECX

(199) 0x42c9c5 LEA	(%R13,%RCX,1),%R15D

(199) 0x42c9ca CMP	%R15D,%R13D

(199) 0x42c9cd JAE	42cda1

(199) 0x42c9d3 MOV	0x30(%RSP),%RDI

(199) 0x42c9d8 MOV	0x20(%RSP),%RAX

(199) 0x42c9dd MOV	0x18(%RSP),%R11

(199) 0x42c9e2 MOV	0x10(%RDI),%RSI

(199) 0x42c9e6 MOV	(%RDI),%R8

(199) 0x42c9e9 MOV	(%RAX),%R10

(199) 0x42c9ec MOV	0x10(%R11),%RDI

(199) 0x42c9f0 MOV	(%R11),%R11

(199) 0x42c9f3 MOV	0x28(%RSP),%R9

(199) 0x42c9f8 IMUL	%R12,%R8

(199) 0x42c9fc IMUL	%R12,%R10

(199) 0x42ca00 IMUL	%R12,%R11

(199) 0x42ca04 MOV	(%R9),%R14

(199) 0x42ca07 MOV	0x10(%RAX),%RDX

(199) 0x42ca0b MOV	0x10(%R9),%RBX

(199) 0x42ca0f LEA	-0x1(%RCX),%R9D

(199) 0x42ca13 MOV	%RSI,0x60(%RSP)

(199) 0x42ca18 MOV	%R8,0x48(%RSP)

(199) 0x42ca1d IMUL	%R12,%R14

(199) 0x42ca21 MOV	%RDX,0x70(%RSP)

(199) 0x42ca26 MOV	%R10,0x50(%RSP)

(199) 0x42ca2b MOV	%RDI,0x78(%RSP)

(199) 0x42ca30 MOV	%R11,0x58(%RSP)

(199) 0x42ca35 CMP	$0x6,%R9D

(199) 0x42ca39 JBE	42cde0

(199) 0x42ca3f MOVSXD	0x6c(%RSP),%RAX

(199) 0x42ca44 MOV	0x70(%RSP),%RDI

(199) 0x42ca49 LEA	(%R8,%RAX,1),%R8

(199) 0x42ca4d LEA	(%R10,%RAX,1),%R10

(199) 0x42ca51 LEA	(%RSI,%R8,8),%RDX

(199) 0x42ca55 LEA	0x1(%R14,%RAX,1),%RSI

(199) 0x42ca5a ADD	%R11,%RAX

(199) 0x42ca5d MOV	0x78(%RSP),%R11

(199) 0x42ca62 SAL	$0x3,%RSI

(199) 0x42ca66 LEA	(%RBX,%RSI,1),%R9

(199) 0x42ca6a LEA	-0x8(%RBX,%RSI,1),%R8

(199) 0x42ca6f LEA	(%R11,%RAX,8),%RSI

(199) 0x42ca73 MOV	%ECX,%R11D

(199) 0x42ca76 SHR	$0x3,%R11D

(199) 0x42ca7a SAL	$0x6,%R11

(199) 0x42ca7e LEA	(%RDI,%R10,8),%RDI

(199) 0x42ca82 LEA	-0x40(%R11),%R10

(199) 0x42ca86 SHR	$0x6,%R10

(199) 0x42ca8a INC	%R10

(199) 0x42ca8d XOR	%EAX,%EAX

(199) 0x42ca8f AND	$0x3,%R10D

(199) 0x42ca93 JE	42cb33

(199) 0x42ca99 CMP	$0x1,%R10

(199) 0x42ca9d JE	42cafc

(199) 0x42ca9f CMP	$0x2,%R10

(199) 0x42caa3 JE	42cace

(199) 0x42caa5 VMOVUPD	(%RDX),%ZMM0

(199) 0x42caab MOV	$0x40,%EAX

(199) 0x42cab0 VADDPD	(%R9),%ZMM0,%ZMM1

(199) 0x42cab6 VSUBPD	(%R8),%ZMM1,%ZMM2

(199) 0x42cabc VMOVUPD	%ZMM2,(%RDI)

(199) 0x42cac2 VMOVUPD	(%RDX),%ZMM3

(199) 0x42cac8 VMOVUPD	%ZMM3,(%RSI)

(199) 0x42cace VMOVUPD	(%RDX,%RAX,1),%ZMM4

(199) 0x42cad5 VADDPD	(%R9,%RAX,1),%ZMM4,%ZMM5

(199) 0x42cadc VSUBPD	(%R8,%RAX,1),%ZMM5,%ZMM6

(199) 0x42cae3 VMOVUPD	%ZMM6,(%RDI,%RAX,1)

(199) 0x42caea VMOVUPD	(%RDX,%RAX,1),%ZMM7

(199) 0x42caf1 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(199) 0x42caf8 ADD	$0x40,%RAX

(199) 0x42cafc VMOVUPD	(%RDX,%RAX,1),%ZMM8

(199) 0x42cb03 VADDPD	(%R9,%RAX,1),%ZMM8,%ZMM9

(199) 0x42cb0a VSUBPD	(%R8,%RAX,1),%ZMM9,%ZMM10

(199) 0x42cb11 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(199) 0x42cb18 VMOVUPD	(%RDX,%RAX,1),%ZMM11

(199) 0x42cb1f VMOVUPD	%ZMM11,(%RSI,%RAX,1)

(199) 0x42cb26 ADD	$0x40,%RAX

(199) 0x42cb2a CMP	%RAX,%R11

(199) 0x42cb2d JE	42cbfc

  (200) 0x42cb33 VMOVUPD	(%RDX,%RAX,1),%ZMM12

  (200) 0x42cb3a VADDPD	(%R9,%RAX,1),%ZMM12,%ZMM13

  (200) 0x42cb41 VSUBPD	(%R8,%RAX,1),%ZMM13,%ZMM14

  (200) 0x42cb48 VMOVUPD	%ZMM14,(%RDI,%RAX,1)

  (200) 0x42cb4f VMOVUPD	(%RDX,%RAX,1),%ZMM15

  (200) 0x42cb56 VMOVUPD	%ZMM15,(%RSI,%RAX,1)

  (200) 0x42cb5d VMOVUPD	0x40(%RDX,%RAX,1),%ZMM0

  (200) 0x42cb65 VADDPD	0x40(%R9,%RAX,1),%ZMM0,%ZMM1

  (200) 0x42cb6d VSUBPD	0x40(%R8,%RAX,1),%ZMM1,%ZMM2

  (200) 0x42cb75 VMOVUPD	%ZMM2,0x40(%RDI,%RAX,1)

  (200) 0x42cb7d VMOVUPD	0x40(%RDX,%RAX,1),%ZMM3

  (200) 0x42cb85 VMOVUPD	%ZMM3,0x40(%RSI,%RAX,1)

  (200) 0x42cb8d VMOVUPD	0x80(%RDX,%RAX,1),%ZMM4

  (200) 0x42cb95 VADDPD	0x80(%R9,%RAX,1),%ZMM4,%ZMM5

  (200) 0x42cb9d VSUBPD	0x80(%R8,%RAX,1),%ZMM5,%ZMM6

  (200) 0x42cba5 VMOVUPD	%ZMM6,0x80(%RDI,%RAX,1)

  (200) 0x42cbad VMOVUPD	0x80(%RDX,%RAX,1),%ZMM7

  (200) 0x42cbb5 VMOVUPD	%ZMM7,0x80(%RSI,%RAX,1)

  (200) 0x42cbbd VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM8

  (200) 0x42cbc5 VADDPD	0xc0(%R9,%RAX,1),%ZMM8,%ZMM9

  (200) 0x42cbcd VSUBPD	0xc0(%R8,%RAX,1),%ZMM9,%ZMM10

  (200) 0x42cbd5 VMOVUPD	%ZMM10,0xc0(%RDI,%RAX,1)

  (200) 0x42cbdd VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM11

  (200) 0x42cbe5 VMOVUPD	%ZMM11,0xc0(%RSI,%RAX,1)

  (200) 0x42cbed ADD	$0x100,%RAX

  (200) 0x42cbf3 CMP	%RAX,%R11

  (200) 0x42cbf6 JNE	42cb33

(199) 0x42cbfc MOV	0x6c(%RSP),%EAX

(199) 0x42cc00 MOV	%ECX,%EDX

(199) 0x42cc02 AND	$-0x8,%EDX

(199) 0x42cc05 ADD	%EDX,%EAX

(199) 0x42cc07 ADD	%EDX,%R13D

(199) 0x42cc0a TEST	$0x7,%CL

(199) 0x42cc0d JE	42cd9e

(199) 0x42cc13 SUB	%EDX,%ECX

(199) 0x42cc15 LEA	-0x1(%RCX),%R9D

(199) 0x42cc19 CMP	$0x2,%R9D

(199) 0x42cc1d JBE	42cc96

(199) 0x42cc1f MOVSXD	0x6c(%RSP),%RSI

(199) 0x42cc24 MOV	0x48(%RSP),%RDI

(199) 0x42cc29 LEA	(%R14,%RSI,1),%R10

(199) 0x42cc2d LEA	0x1(%RDX,%R10,1),%R9

(199) 0x42cc32 VMOVUPD	(%RBX,%R9,8),%YMM12

(199) 0x42cc38 ADD	%RSI,%RDI

(199) 0x42cc3b VSUBPD	-0x8(%RBX,%R9,8),%YMM12,%YMM13

(199) 0x42cc42 MOV	0x60(%RSP),%R8

(199) 0x42cc47 ADD	%RDX,%RDI

(199) 0x42cc4a LEA	(%R8,%RDI,8),%R11

(199) 0x42cc4e MOV	0x50(%RSP),%RDI

(199) 0x42cc53 VADDPD	(%R11),%YMM13,%YMM14

(199) 0x42cc58 ADD	%RSI,%RDI

(199) 0x42cc5b MOV	0x70(%RSP),%R8

(199) 0x42cc60 ADD	%RDX,%RDI

(199) 0x42cc63 VMOVUPD	%YMM14,(%R8,%RDI,8)

(199) 0x42cc69 VMOVUPD	(%R11),%YMM15

(199) 0x42cc6e MOV	0x58(%RSP),%R11

(199) 0x42cc73 ADD	%R11,%RSI

(199) 0x42cc76 ADD	%RDX,%RSI

(199) 0x42cc79 MOV	0x78(%RSP),%RDX

(199) 0x42cc7e VMOVUPD	%YMM15,(%RDX,%RSI,8)

(199) 0x42cc83 MOV	%ECX,%ESI

(199) 0x42cc85 AND	$-0x4,%ESI

(199) 0x42cc88 ADD	%ESI,%EAX

(199) 0x42cc8a ADD	%ESI,%R13D

(199) 0x42cc8d AND	$0x3,%ECX

(199) 0x42cc90 JE	42cd9e

(199) 0x42cc96 LEA	0x1(%RAX),%R8D

(199) 0x42cc9a MOV	0x48(%RSP),%R10

(199) 0x42cc9f MOVSXD	%EAX,%RCX

(199) 0x42cca2 MOV	0x60(%RSP),%RDI

(199) 0x42cca7 MOVSXD	%R8D,%RDX

(199) 0x42ccaa LEA	(%R10,%RCX,1),%R9

(199) 0x42ccae LEA	(%R14,%RDX,1),%R11

(199) 0x42ccb2 LEA	(%RDI,%R9,8),%RSI

(199) 0x42ccb6 LEA	(%RBX,%R11,8),%RDI

(199) 0x42ccba VMOVSD	(%RDI),%XMM0

(199) 0x42ccbe LEA	(%R14,%RCX,1),%R9

(199) 0x42ccc2 VSUBSD	(%RBX,%R9,8),%XMM0,%XMM1

(199) 0x42ccc8 MOV	0x50(%RSP),%R11

(199) 0x42cccd MOV	0x70(%RSP),%R9

(199) 0x42ccd2 VADDSD	(%RSI),%XMM1,%XMM2

(199) 0x42ccd6 LEA	(%R11,%RCX,1),%R8

(199) 0x42ccda VMOVSD	%XMM2,(%R9,%R8,8)

(199) 0x42cce0 VMOVSD	(%RSI),%XMM3

(199) 0x42cce4 MOV	0x58(%RSP),%RSI

(199) 0x42cce9 MOV	0x78(%RSP),%R8

(199) 0x42ccee ADD	%RSI,%RCX

(199) 0x42ccf1 VMOVSD	%XMM3,(%R8,%RCX,8)

(199) 0x42ccf7 LEA	0x1(%R13),%ECX

(199) 0x42ccfb CMP	%R15D,%ECX

(199) 0x42ccfe JAE	42cd9e

(199) 0x42cd04 MOV	0x60(%RSP),%R9

(199) 0x42cd09 LEA	0x2(%RAX),%R8D

(199) 0x42cd0d LEA	(%RDX,%R10,1),%RSI

(199) 0x42cd11 MOVSXD	%R8D,%RCX

(199) 0x42cd14 LEA	(%R9,%RSI,8),%RSI

(199) 0x42cd18 LEA	(%R14,%RCX,1),%R9

(199) 0x42cd1c LEA	(%RBX,%R9,8),%R8

(199) 0x42cd20 VMOVSD	(%R8),%XMM4

(199) 0x42cd25 LEA	(%R11,%RDX,1),%R9

(199) 0x42cd29 VADDSD	(%RSI),%XMM4,%XMM5

(199) 0x42cd2d ADD	$0x2,%R13D

(199) 0x42cd31 VSUBSD	(%RDI),%XMM5,%XMM6

(199) 0x42cd35 MOV	0x70(%RSP),%RDI

(199) 0x42cd3a VMOVSD	%XMM6,(%RDI,%R9,8)

(199) 0x42cd40 MOV	0x58(%RSP),%RDI

(199) 0x42cd45 VMOVSD	(%RSI),%XMM7

(199) 0x42cd49 MOV	0x78(%RSP),%RSI

(199) 0x42cd4e ADD	%RDI,%RDX

(199) 0x42cd51 VMOVSD	%XMM7,(%RSI,%RDX,8)

(199) 0x42cd56 CMP	%R15D,%R13D

(199) 0x42cd59 JAE	42cd9e

(199) 0x42cd5b ADD	$0x3,%EAX

(199) 0x42cd5e CLTQ

(199) 0x42cd60 ADD	%R14,%RAX

(199) 0x42cd63 MOV	0x60(%RSP),%R13

(199) 0x42cd68 VMOVSD	(%RBX,%RAX,8),%XMM8

(199) 0x42cd6d ADD	%RCX,%R10

(199) 0x42cd70 LEA	(%R13,%R10,8),%RDX

(199) 0x42cd75 VADDSD	(%RDX),%XMM8,%XMM9

(199) 0x42cd79 MOV	0x70(%RSP),%RBX

(199) 0x42cd7e ADD	%RCX,%R11

(199) 0x42cd81 VSUBSD	(%R8),%XMM9,%XMM10

(199) 0x42cd86 MOV	0x78(%RSP),%R14

(199) 0x42cd8b ADD	%RCX,%RDI

(199) 0x42cd8e VMOVSD	%XMM10,(%RBX,%R11,8)

(199) 0x42cd94 VMOVSD	(%RDX),%XMM11

(199) 0x42cd98 VMOVSD	%XMM11,(%R14,%RDI,8)

(199) 0x42cd9e MOV	%R15D,%R13D

(199) 0x42cda1 INC	%R12

(199) 0x42cda4 CMP	%R12D,0x44(%RSP)

(199) 0x42cda9 JLE	42cdc8

(199) 0x42cdab MOV	0x3c(%RSP),%ESI

(199) 0x42cdaf MOV	0x40(%RSP),%R15D

(199) 0x42cdb4 MOV	0x68(%RSP),%ECX

(199) 0x42cdb8 MOV	%R15D,0x6c(%RSP)

(199) 0x42cdbd SUB	%R13D,%ESI

(199) 0x42cdc0 JMP	42c9c0

0x42cdc5 NOPL	(%RAX)

0x42cdc8 VZEROUPPER

0x42cdcb LEA	-0x28(%RBP),%RSP

0x42cdcf POP	%RBX

0x42cdd0 POP	%R12

0x42cdd2 POP	%R13

0x42cdd4 POP	%R14

0x42cdd6 POP	%R15

0x42cdd8 POP	%RBP

0x42cdd9 RET

0x42cdda NOPW	(%RAX,%RAX,1)

(199) 0x42cde0 MOV	0x6c(%RSP),%EAX

(199) 0x42cde4 XOR	%EDX,%EDX

(199) 0x42cde6 JMP	42cc13

0x42cdeb INC	%ESI

0x42cded XOR	%EDX,%EDX

0x42cdef JMP	42c961

0x42cdf4 NOPW	%CS:(%RAX,%RAX,1)

0x42cdff NOP

Coverage (%)	Name	Source Location	Module
○97.49	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.51	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	272
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42c8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42cdeb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x68(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x40(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42c961 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	272
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42c8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42cdeb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x50b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42cdcb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x68(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x40(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42c961 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.26	0.36
▼Loop 199 - advec_cell.cpp:56-58 - exec–	0.00	0.00
○Loop 200 - advec_cell.cpp:57-58 - exec	1.26	0.36

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code