OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage (incl. loops): 1.52% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c110 PUSH	%RBP

0x42c111 MOV	%RSP,%RBP

0x42c114 PUSH	%R15

0x42c116 PUSH	%R14

0x42c118 PUSH	%R13

0x42c11a PUSH	%R12

0x42c11c PUSH	%RBX

0x42c11d AND	$-0x40,%RSP

0x42c121 SUB	$0xc0,%RSP

0x42c128 MOV	0x30(%RDI),%EAX

0x42c12b MOV	0x34(%RDI),%EDX

0x42c12e MOV	0x28(%RDI),%ESI

0x42c131 ADD	$0x4,%EDX

0x42c134 DEC	%ESI

0x42c136 LEA	-0x1(%RAX),%R12D

0x42c13a MOV	%EDX,0x5c(%RSP)

0x42c13e MOV	%ESI,0x58(%RSP)

0x42c142 MOV	0x2c(%RDI),%ECX

0x42c145 CMP	%EDX,%R12D

0x42c148 JGE	42c8a3

0x42c14e MOV	%EDX,%R14D

0x42c151 LEA	0x4(%RCX),%R15D

0x42c155 SUB	%R12D,%R14D

0x42c158 CMP	%R15D,%ESI

0x42c15b JGE	42c8a3

0x42c161 MOV	%RDI,%RBX

0x42c164 MOV	%R15D,%EDI

0x42c167 SUB	%ESI,%EDI

0x42c169 MOV	%EDI,0xa0(%RSP)

0x42c170 CALL	404630 <omp_get_num_threads@plt>

0x42c175 MOV	%EAX,%R13D

0x42c178 CALL	404520 <omp_get_thread_num@plt>

0x42c17d MOV	%EAX,%R8D

0x42c180 MOV	0xa0(%RSP),%EAX

0x42c187 XOR	%EDX,%EDX

0x42c189 IMUL	%R14D,%EAX

0x42c18d DIV	%R13D

0x42c190 MOV	%EAX,%ECX

0x42c192 CMP	%EDX,%R8D

0x42c195 JB	42c8d7

0x42c19b IMUL	%ECX,%R8D

0x42c19f LEA	(%R8,%RDX,1),%R14D

0x42c1a3 LEA	(%RCX,%R14,1),%R9D

0x42c1a7 MOV	%R9D,0x54(%RSP)

0x42c1ac CMP	%R9D,%R14D

0x42c1af JAE	42c8a3

0x42c1b5 MOV	%R14D,%EAX

0x42c1b8 XOR	%EDX,%EDX

0x42c1ba DIVL	0xa0(%RSP)

0x42c1c1 MOV	(%RBX),%R11

0x42c1c4 MOV	0x10(%RBX),%RDI

0x42c1c8 MOV	0x18(%RBX),%R13

0x42c1cc MOV	0x58(%RSP),%R10D

0x42c1d1 MOV	%R11,0x48(%RSP)

0x42c1d6 MOV	%RDI,0x38(%RSP)

0x42c1db MOV	%R13,0x30(%RSP)

0x42c1e0 MOV	%R15D,%ESI

0x42c1e3 MOV	0x8(%RBX),%R15

0x42c1e7 MOV	0x20(%RBX),%RBX

0x42c1eb MOV	%R15,0x40(%RSP)

0x42c1f0 MOV	%RBX,0x28(%RSP)

0x42c1f5 ADD	%R10D,%EDX

0x42c1f8 ADD	%R12D,%EAX

0x42c1fb MOV	%EDX,0xa8(%RSP)

0x42c202 SUB	%EDX,%ESI

0x42c204 MOVSXD	%EAX,%RDX

0x42c207 NOPW	(%RAX,%RAX,1)

(197) 0x42c210 CMP	%ESI,%ECX

(197) 0x42c212 CMOVBE	%ECX,%ESI

(197) 0x42c215 LEA	(%R14,%RSI,1),%R12D

(197) 0x42c219 MOV	%R12D,0xa4(%RSP)

(197) 0x42c221 CMP	%R12D,%R14D

(197) 0x42c224 JAE	42c8b8

(197) 0x42c22a MOV	0x40(%RSP),%R8

(197) 0x42c22f MOV	0x38(%RSP),%R9

(197) 0x42c234 MOV	0x30(%RSP),%R12

(197) 0x42c239 MOV	(%R9),%RAX

(197) 0x42c23c MOV	0x48(%RSP),%RCX

(197) 0x42c241 MOV	(%R8),%R10

(197) 0x42c244 MOV	0x10(%R8),%R15

(197) 0x42c248 MOV	0x10(%R12),%R8

(197) 0x42c24d LEA	0x1(%RDX),%RDI

(197) 0x42c251 MOV	0x10(%RCX),%R11

(197) 0x42c255 MOV	%RDI,0x60(%RSP)

(197) 0x42c25a MOV	%R8,0xb0(%RSP)

(197) 0x42c262 IMUL	%RAX,%RDI

(197) 0x42c266 MOV	(%R12),%R8

(197) 0x42c26a MOV	(%RCX),%RCX

(197) 0x42c26d MOV	0x10(%R9),%R13

(197) 0x42c271 MOV	0x28(%RSP),%R9

(197) 0x42c276 IMUL	%RDX,%RCX

(197) 0x42c27a IMUL	%RDX,%R10

(197) 0x42c27e IMUL	%RDX,%R8

(197) 0x42c282 IMUL	(%R9),%RDX

(197) 0x42c286 MOV	%RDI,%RBX

(197) 0x42c289 SUB	%RAX,%RBX

(197) 0x42c28c MOV	0x10(%R9),%RAX

(197) 0x42c290 MOV	%RDX,0x90(%RSP)

(197) 0x42c298 MOV	%RDX,%R12

(197) 0x42c29b LEA	-0x1(%RSI),%EDX

(197) 0x42c29e MOV	%R11,0x98(%RSP)

(197) 0x42c2a6 MOV	%RCX,0x68(%RSP)

(197) 0x42c2ab MOV	%R10,0x70(%RSP)

(197) 0x42c2b0 MOV	%RDI,0x78(%RSP)

(197) 0x42c2b5 MOV	%RBX,0x80(%RSP)

(197) 0x42c2bd MOV	%R8,0x88(%RSP)

(197) 0x42c2c5 MOV	%RAX,0xb8(%RSP)

(197) 0x42c2cd CMP	$0x6,%EDX

(197) 0x42c2d0 JBE	42c8c8

(197) 0x42c2d6 MOVSXD	0xa8(%RSP),%RAX

(197) 0x42c2de LEA	0x1(%R10,%RAX,1),%R10

(197) 0x42c2e3 SAL	$0x3,%R10

(197) 0x42c2e7 ADD	%RAX,%RDI

(197) 0x42c2ea LEA	(%RCX,%RAX,1),%R9

(197) 0x42c2ee LEA	(%R8,%RAX,1),%R8

(197) 0x42c2f2 LEA	(%R15,%R10,1),%RDX

(197) 0x42c2f6 LEA	-0x8(%R15,%R10,1),%RCX

(197) 0x42c2fb LEA	(%R13,%RDI,8),%R10

(197) 0x42c300 LEA	(%RBX,%RAX,1),%RDI

(197) 0x42c304 ADD	%R12,%RAX

(197) 0x42c307 MOV	0xb8(%RSP),%R12

(197) 0x42c30f LEA	(%R11,%R9,8),%R11

(197) 0x42c313 LEA	(%R13,%RDI,8),%R9

(197) 0x42c318 LEA	(%R12,%RAX,8),%RDI

(197) 0x42c31c MOV	%ESI,%R12D

(197) 0x42c31f MOV	0xb0(%RSP),%RBX

(197) 0x42c327 SHR	$0x3,%R12D

(197) 0x42c32b SAL	$0x6,%R12

(197) 0x42c32f LEA	(%RBX,%R8,8),%R8

(197) 0x42c333 LEA	-0x40(%R12),%RBX

(197) 0x42c338 SHR	$0x6,%RBX

(197) 0x42c33c INC	%RBX

(197) 0x42c33f XOR	%EAX,%EAX

(197) 0x42c341 AND	$0x3,%EBX

(197) 0x42c344 JE	42c448

(197) 0x42c34a CMP	$0x1,%RBX

(197) 0x42c34e JE	42c3f0

(197) 0x42c354 CMP	$0x2,%RBX

(197) 0x42c358 JE	42c3a1

(197) 0x42c35a VMOVUPD	(%R11),%ZMM0

(197) 0x42c360 VMOVUPD	(%RCX),%ZMM3

(197) 0x42c366 VADDPD	(%RDX),%ZMM0,%ZMM1

(197) 0x42c36c VADDPD	(%R9),%ZMM3,%ZMM4

(197) 0x42c372 MOV	$0x40,%EAX

(197) 0x42c377 VADDPD	(%R10),%ZMM1,%ZMM2

(197) 0x42c37d VSUBPD	%ZMM4,%ZMM2,%ZMM5

(197) 0x42c383 VMOVUPD	%ZMM5,(%R8)

(197) 0x42c389 VMOVUPD	(%RCX),%ZMM6

(197) 0x42c38f VSUBPD	(%RDX),%ZMM6,%ZMM7

(197) 0x42c395 VADDPD	%ZMM5,%ZMM7,%ZMM8

(197) 0x42c39b VMOVUPD	%ZMM8,(%RDI)

(197) 0x42c3a1 VMOVUPD	(%R11,%RAX,1),%ZMM9

(197) 0x42c3a8 VMOVUPD	(%RCX,%RAX,1),%ZMM12

(197) 0x42c3af VADDPD	(%RDX,%RAX,1),%ZMM9,%ZMM10

(197) 0x42c3b6 VADDPD	(%R9,%RAX,1),%ZMM12,%ZMM13

(197) 0x42c3bd VADDPD	(%R10,%RAX,1),%ZMM10,%ZMM11

(197) 0x42c3c4 VSUBPD	%ZMM13,%ZMM11,%ZMM14

(197) 0x42c3ca VMOVUPD	%ZMM14,(%R8,%RAX,1)

(197) 0x42c3d1 VMOVUPD	(%RCX,%RAX,1),%ZMM15

(197) 0x42c3d8 VSUBPD	(%RDX,%RAX,1),%ZMM15,%ZMM0

(197) 0x42c3df VADDPD	%ZMM14,%ZMM0,%ZMM1

(197) 0x42c3e5 VMOVUPD	%ZMM1,(%RDI,%RAX,1)

(197) 0x42c3ec ADD	$0x40,%RAX

(197) 0x42c3f0 VMOVUPD	(%R11,%RAX,1),%ZMM2

(197) 0x42c3f7 VMOVUPD	(%RCX,%RAX,1),%ZMM5

(197) 0x42c3fe VADDPD	(%RDX,%RAX,1),%ZMM2,%ZMM3

(197) 0x42c405 VADDPD	(%R9,%RAX,1),%ZMM5,%ZMM6

(197) 0x42c40c VADDPD	(%R10,%RAX,1),%ZMM3,%ZMM4

(197) 0x42c413 VSUBPD	%ZMM6,%ZMM4,%ZMM7

(197) 0x42c419 VMOVUPD	%ZMM7,(%R8,%RAX,1)

(197) 0x42c420 VMOVUPD	(%RCX,%RAX,1),%ZMM8

(197) 0x42c427 VSUBPD	(%RDX,%RAX,1),%ZMM8,%ZMM9

(197) 0x42c42e VADDPD	%ZMM7,%ZMM9,%ZMM10

(197) 0x42c434 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(197) 0x42c43b ADD	$0x40,%RAX

(197) 0x42c43f CMP	%RAX,%R12

(197) 0x42c442 JE	42c59e

  (198) 0x42c448 VMOVUPD	(%R11,%RAX,1),%ZMM11

  (198) 0x42c44f VMOVUPD	(%RCX,%RAX,1),%ZMM14

  (198) 0x42c456 VADDPD	(%RDX,%RAX,1),%ZMM11,%ZMM12

  (198) 0x42c45d VADDPD	(%R9,%RAX,1),%ZMM14,%ZMM15

  (198) 0x42c464 VADDPD	(%R10,%RAX,1),%ZMM12,%ZMM13

  (198) 0x42c46b VSUBPD	%ZMM15,%ZMM13,%ZMM0

  (198) 0x42c471 VMOVUPD	%ZMM0,(%R8,%RAX,1)

  (198) 0x42c478 VMOVUPD	(%RCX,%RAX,1),%ZMM1

  (198) 0x42c47f VSUBPD	(%RDX,%RAX,1),%ZMM1,%ZMM2

  (198) 0x42c486 VADDPD	%ZMM0,%ZMM2,%ZMM3

  (198) 0x42c48c VMOVUPD	%ZMM3,(%RDI,%RAX,1)

  (198) 0x42c493 VMOVUPD	0x40(%R11,%RAX,1),%ZMM4

  (198) 0x42c49b VMOVUPD	0x40(%RCX,%RAX,1),%ZMM7

  (198) 0x42c4a3 VADDPD	0x40(%RDX,%RAX,1),%ZMM4,%ZMM5

  (198) 0x42c4ab VADDPD	0x40(%R9,%RAX,1),%ZMM7,%ZMM8

  (198) 0x42c4b3 VADDPD	0x40(%R10,%RAX,1),%ZMM5,%ZMM6

  (198) 0x42c4bb VSUBPD	%ZMM8,%ZMM6,%ZMM9

  (198) 0x42c4c1 VMOVUPD	%ZMM9,0x40(%R8,%RAX,1)

  (198) 0x42c4c9 VMOVUPD	0x40(%RCX,%RAX,1),%ZMM10

  (198) 0x42c4d1 VSUBPD	0x40(%RDX,%RAX,1),%ZMM10,%ZMM11

  (198) 0x42c4d9 VADDPD	%ZMM9,%ZMM11,%ZMM12

  (198) 0x42c4df VMOVUPD	%ZMM12,0x40(%RDI,%RAX,1)

  (198) 0x42c4e7 VMOVUPD	0x80(%R11,%RAX,1),%ZMM13

  (198) 0x42c4ef VMOVUPD	0x80(%RCX,%RAX,1),%ZMM0

  (198) 0x42c4f7 VADDPD	0x80(%RDX,%RAX,1),%ZMM13,%ZMM14

  (198) 0x42c4ff VADDPD	0x80(%R9,%RAX,1),%ZMM0,%ZMM1

  (198) 0x42c507 VADDPD	0x80(%R10,%RAX,1),%ZMM14,%ZMM15

  (198) 0x42c50f VSUBPD	%ZMM1,%ZMM15,%ZMM2

  (198) 0x42c515 VMOVUPD	%ZMM2,0x80(%R8,%RAX,1)

  (198) 0x42c51d VMOVUPD	0x80(%RCX,%RAX,1),%ZMM3

  (198) 0x42c525 VSUBPD	0x80(%RDX,%RAX,1),%ZMM3,%ZMM4

  (198) 0x42c52d VADDPD	%ZMM2,%ZMM4,%ZMM5

  (198) 0x42c533 VMOVUPD	%ZMM5,0x80(%RDI,%RAX,1)

  (198) 0x42c53b VMOVUPD	0xc0(%R11,%RAX,1),%ZMM6

  (198) 0x42c543 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM9

  (198) 0x42c54b VADDPD	0xc0(%RDX,%RAX,1),%ZMM6,%ZMM7

  (198) 0x42c553 VADDPD	0xc0(%R9,%RAX,1),%ZMM9,%ZMM10

  (198) 0x42c55b VADDPD	0xc0(%R10,%RAX,1),%ZMM7,%ZMM8

  (198) 0x42c563 VSUBPD	%ZMM10,%ZMM8,%ZMM11

  (198) 0x42c569 VMOVUPD	%ZMM11,0xc0(%R8,%RAX,1)

  (198) 0x42c571 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM12

  (198) 0x42c579 VSUBPD	0xc0(%RDX,%RAX,1),%ZMM12,%ZMM13

  (198) 0x42c581 VADDPD	%ZMM11,%ZMM13,%ZMM14

  (198) 0x42c587 VMOVUPD	%ZMM14,0xc0(%RDI,%RAX,1)

  (198) 0x42c58f ADD	$0x100,%RAX

  (198) 0x42c595 CMP	%RAX,%R12

  (198) 0x42c598 JNE	42c448

(197) 0x42c59e MOV	0xa8(%RSP),%EDX

(197) 0x42c5a5 MOV	%ESI,%R11D

(197) 0x42c5a8 AND	$-0x8,%R11D

(197) 0x42c5ac LEA	(%R11,%RDX,1),%ECX

(197) 0x42c5b0 ADD	%R11D,%R14D

(197) 0x42c5b3 TEST	$0x7,%SIL

(197) 0x42c5b7 JE	42c86d

(197) 0x42c5bd SUB	%R11D,%ESI

(197) 0x42c5c0 LEA	-0x1(%RSI),%R10D

(197) 0x42c5c4 CMP	$0x2,%R10D

(197) 0x42c5c8 JBE	42c69b

(197) 0x42c5ce MOVSXD	0xa8(%RSP),%R12

(197) 0x42c5d6 MOV	0x70(%RSP),%R9

(197) 0x42c5db MOV	0x68(%RSP),%RBX

(197) 0x42c5e0 LEA	(%R9,%R12,1),%R8

(197) 0x42c5e4 MOV	0x78(%RSP),%R9

(197) 0x42c5e9 LEA	0x1(%R11,%R8,1),%RDI

(197) 0x42c5ee LEA	(%R9,%R12,1),%R8

(197) 0x42c5f2 SAL	$0x3,%RDI

(197) 0x42c5f6 ADD	%R11,%R8

(197) 0x42c5f9 VMOVUPD	(%R13,%R8,8),%YMM15

(197) 0x42c600 LEA	(%R15,%RDI,1),%RAX

(197) 0x42c604 LEA	-0x8(%R15,%RDI,1),%RDX

(197) 0x42c609 LEA	(%RBX,%R12,1),%R10

(197) 0x42c60d MOV	0x98(%RSP),%RDI

(197) 0x42c615 ADD	%R11,%R10

(197) 0x42c618 MOV	0x80(%RSP),%RBX

(197) 0x42c620 VADDPD	(%RDI,%R10,8),%YMM15,%YMM0

(197) 0x42c626 VMOVUPD	(%RAX),%YMM1

(197) 0x42c62a LEA	(%RBX,%R12,1),%R10

(197) 0x42c62e ADD	%R11,%R10

(197) 0x42c631 VSUBPD	(%R13,%R10,8),%YMM0,%YMM2

(197) 0x42c638 VSUBPD	(%RDX),%YMM1,%YMM3

(197) 0x42c63c MOV	0x88(%RSP),%R9

(197) 0x42c644 MOV	0xb0(%RSP),%RDI

(197) 0x42c64c VADDPD	%YMM3,%YMM2,%YMM4

(197) 0x42c650 LEA	(%R9,%R12,1),%R8

(197) 0x42c654 ADD	%R11,%R8

(197) 0x42c657 VMOVUPD	%YMM4,(%RDI,%R8,8)

(197) 0x42c65d VMOVUPD	(%RDX),%YMM5

(197) 0x42c661 VSUBPD	(%RAX),%YMM5,%YMM6

(197) 0x42c665 MOV	0x90(%RSP),%RAX

(197) 0x42c66d VADDPD	%YMM4,%YMM6,%YMM7

(197) 0x42c671 ADD	%RAX,%R12

(197) 0x42c674 ADD	%R11,%R12

(197) 0x42c677 MOV	0xb8(%RSP),%R11

(197) 0x42c67f VMOVUPD	%YMM7,(%R11,%R12,8)

(197) 0x42c685 MOV	%ESI,%R12D

(197) 0x42c688 AND	$-0x4,%R12D

(197) 0x42c68c ADD	%R12D,%ECX

(197) 0x42c68f ADD	%R12D,%R14D

(197) 0x42c692 AND	$0x3,%ESI

(197) 0x42c695 JE	42c86d

(197) 0x42c69b MOV	0x70(%RSP),%RBX

(197) 0x42c6a0 LEA	0x1(%RCX),%ESI

(197) 0x42c6a3 MOVSXD	%ECX,%RAX

(197) 0x42c6a6 MOVSXD	%ESI,%RDX

(197) 0x42c6a9 MOV	0x68(%RSP),%R11

(197) 0x42c6ae LEA	(%RBX,%RAX,1),%R9

(197) 0x42c6b2 MOV	0x98(%RSP),%R12

(197) 0x42c6ba LEA	(%RBX,%RDX,1),%R10

(197) 0x42c6be LEA	(%R15,%R9,8),%RDI

(197) 0x42c6c2 LEA	(%R15,%R10,8),%RSI

(197) 0x42c6c6 LEA	(%R11,%RAX,1),%R9

(197) 0x42c6ca MOV	0x78(%RSP),%R10

(197) 0x42c6cf VMOVSD	(%R12,%R9,8),%XMM8

(197) 0x42c6d5 LEA	(%R10,%RAX,1),%R8

(197) 0x42c6d9 VADDSD	(%R13,%R8,8),%XMM8,%XMM9

(197) 0x42c6e0 MOV	0x80(%RSP),%R12

(197) 0x42c6e8 VMOVSD	(%RSI),%XMM11

(197) 0x42c6ec LEA	(%R12,%RAX,1),%R9

(197) 0x42c6f0 VSUBSD	(%R13,%R9,8),%XMM9,%XMM10

(197) 0x42c6f7 VSUBSD	(%RDI),%XMM11,%XMM12

(197) 0x42c6fb MOV	0x88(%RSP),%R8

(197) 0x42c703 MOV	0xb0(%RSP),%R9

(197) 0x42c70b VADDSD	%XMM12,%XMM10,%XMM13

(197) 0x42c710 LEA	(%R8,%RAX,1),%R8

(197) 0x42c714 VMOVSD	%XMM13,(%R9,%R8,8)

(197) 0x42c71a VMOVSD	(%RDI),%XMM14

(197) 0x42c71e MOV	0x90(%RSP),%R8

(197) 0x42c726 VSUBSD	(%RSI),%XMM14,%XMM15

(197) 0x42c72a MOV	0xb8(%RSP),%RDI

(197) 0x42c732 ADD	%R8,%RAX

(197) 0x42c735 VADDSD	%XMM13,%XMM15,%XMM0

(197) 0x42c73a MOV	0xa4(%RSP),%R9D

(197) 0x42c742 VMOVSD	%XMM0,(%RDI,%RAX,8)

(197) 0x42c747 LEA	0x1(%R14),%EAX

(197) 0x42c74b CMP	%R9D,%EAX

(197) 0x42c74e JAE	42c86d

(197) 0x42c754 LEA	0x2(%RCX),%EAX

(197) 0x42c757 CLTQ

(197) 0x42c759 LEA	(%RBX,%RAX,1),%R8

(197) 0x42c75d LEA	(%R15,%R8,8),%RDI

(197) 0x42c761 MOV	%R11,%R9

(197) 0x42c764 LEA	(%RDX,%R11,1),%R8

(197) 0x42c768 MOV	0x98(%RSP),%R11

(197) 0x42c770 MOV	%RDI,0xa8(%RSP)

(197) 0x42c778 VMOVSD	(%R11,%R8,8),%XMM2

(197) 0x42c77e MOV	%R12,%R11

(197) 0x42c781 VADDSD	(%RDI),%XMM2,%XMM1

(197) 0x42c785 LEA	(%R12,%RDX,1),%R12

(197) 0x42c789 VMOVSD	(%R13,%R12,8),%XMM4

(197) 0x42c790 LEA	(%R10,%RDX,1),%RDI

(197) 0x42c794 VADDSD	(%R13,%RDI,8),%XMM1,%XMM3

(197) 0x42c79b VADDSD	(%RSI),%XMM4,%XMM5

(197) 0x42c79f MOV	0x88(%RSP),%R12

(197) 0x42c7a7 MOV	0xb0(%RSP),%RDI

(197) 0x42c7af VSUBSD	%XMM5,%XMM3,%XMM6

(197) 0x42c7b3 LEA	(%R12,%RDX,1),%R8

(197) 0x42c7b7 ADD	$0x2,%R14D

(197) 0x42c7bb VMOVSD	%XMM6,(%RDI,%R8,8)

(197) 0x42c7c1 VMOVSD	(%RSI),%XMM7

(197) 0x42c7c5 MOV	0xa8(%RSP),%RSI

(197) 0x42c7cd MOV	0x90(%RSP),%R8

(197) 0x42c7d5 VSUBSD	(%RSI),%XMM7,%XMM8

(197) 0x42c7d9 MOV	0xb8(%RSP),%RSI

(197) 0x42c7e1 ADD	%R8,%RDX

(197) 0x42c7e4 VADDSD	%XMM6,%XMM8,%XMM9

(197) 0x42c7e8 VMOVSD	%XMM9,(%RSI,%RDX,8)

(197) 0x42c7ed MOV	0xa4(%RSP),%EDX

(197) 0x42c7f4 CMP	%EDX,%R14D

(197) 0x42c7f7 JAE	42c86d

(197) 0x42c7f9 ADD	$0x3,%ECX

(197) 0x42c7fc MOVSXD	%ECX,%R14

(197) 0x42c7ff MOV	0x98(%RSP),%RCX

(197) 0x42c807 ADD	%RAX,%R9

(197) 0x42c80a VMOVSD	(%RCX,%R9,8),%XMM10

(197) 0x42c810 ADD	%RBX,%R14

(197) 0x42c813 LEA	(%R15,%R14,8),%R15

(197) 0x42c817 VADDSD	(%R15),%XMM10,%XMM11

(197) 0x42c81c ADD	%RAX,%R10

(197) 0x42c81f ADD	%RAX,%R11

(197) 0x42c822 VADDSD	(%R13,%R10,8),%XMM11,%XMM12

(197) 0x42c829 VMOVSD	(%R13,%R11,8),%XMM13

(197) 0x42c830 MOV	0xa8(%RSP),%R13

(197) 0x42c838 ADD	%RAX,%R12

(197) 0x42c83b VADDSD	(%R13),%XMM13,%XMM14

(197) 0x42c841 MOV	0xb8(%RSP),%RBX

(197) 0x42c849 ADD	%RAX,%R8

(197) 0x42c84c VSUBSD	%XMM14,%XMM12,%XMM15

(197) 0x42c851 VMOVSD	%XMM15,(%RDI,%R12,8)

(197) 0x42c857 VMOVSD	(%R13),%XMM0

(197) 0x42c85d VSUBSD	(%R15),%XMM0,%XMM2

(197) 0x42c862 VADDSD	%XMM15,%XMM2,%XMM1

(197) 0x42c867 VMOVSD	%XMM1,(%RBX,%R8,8)

(197) 0x42c86d MOV	0xa4(%RSP),%R14D

(197) 0x42c875 MOV	0x60(%RSP),%RDX

(197) 0x42c87a CMP	%EDX,0x5c(%RSP)

(197) 0x42c87e JLE	42c8a0

(197) 0x42c880 MOV	0x54(%RSP),%ECX

(197) 0x42c884 MOV	0x58(%RSP),%EAX

(197) 0x42c888 MOV	0xa0(%RSP),%ESI

(197) 0x42c88f MOV	%EAX,0xa8(%RSP)

(197) 0x42c896 SUB	%R14D,%ECX

(197) 0x42c899 JMP	42c210

0x42c89e XCHG	%AX,%AX

0x42c8a0 VZEROUPPER

0x42c8a3 LEA	-0x28(%RBP),%RSP

0x42c8a7 POP	%RBX

0x42c8a8 POP	%R12

0x42c8aa POP	%R13

0x42c8ac POP	%R14

0x42c8ae POP	%R15

0x42c8b0 POP	%RBP

0x42c8b1 RET

0x42c8b2 NOPW	(%RAX,%RAX,1)

(197) 0x42c8b8 LEA	0x1(%RDX),%RSI

(197) 0x42c8bc MOV	%RSI,0x60(%RSP)

(197) 0x42c8c1 JMP	42c875

0x42c8c3 NOPL	(%RAX,%RAX,1)

(197) 0x42c8c8 MOV	0xa8(%RSP),%ECX

(197) 0x42c8cf XOR	%R11D,%R11D

(197) 0x42c8d2 JMP	42c5bd

0x42c8d7 INC	%ECX

0x42c8d9 XOR	%EDX,%EDX

0x42c8db JMP	42c19b

Coverage (%)	Name	Source Location	Module
○97.54	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.46	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.33 to 3.00 cycles (5.11x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.33 to 14.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	92
loop length	296
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.33
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.33

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42c110

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xa0(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42c8d7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0xa0(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42c19b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.33 to 14.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	92
loop length	296
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33
cycles	6.10	11.93	6.33	6.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.33
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	15.33

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

2% of peak load performance is reached (4.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 42c110

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xa0(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 42c8d7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R14,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 42c8a3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0xa0(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42c19b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.52	0.44
▼Loop 197 - advec_cell.cpp:44-48 - exec–	0.00	0.01
○Loop 198 - advec_cell.cpp:47-48 - exec	1.52	0.44

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code