OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage (incl. loops): 2.61% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x46d570 PUSH	%RBP

0x46d571 MOV	%RSP,%RBP

0x46d574 PUSH	%R15

0x46d576 PUSH	%R14

0x46d578 PUSH	%R13

0x46d57a PUSH	%R12

0x46d57c PUSH	%RBX

0x46d57d MOV	%RDI,%RBX

0x46d580 SUB	$0x88,%RSP

0x46d587 MOV	0x40(%RDI),%EAX

0x46d58a MOV	0x44(%RDI),%ECX

0x46d58d MOV	0x38(%RDI),%EDI

0x46d590 ADD	$0x2,%ECX

0x46d593 INC	%EDI

0x46d595 LEA	0x1(%RAX),%R12D

0x46d599 MOV	%ECX,-0x7c(%RBP)

0x46d59c MOV	%EDI,-0x80(%RBP)

0x46d59f MOV	0x3c(%RBX),%EDX

0x46d5a2 CMP	%ECX,%R12D

0x46d5a5 JGE	46d980

0x46d5ab MOV	%ECX,%R14D

0x46d5ae LEA	0x2(%RDX),%R15D

0x46d5b2 SUB	%R12D,%R14D

0x46d5b5 CMP	%R15D,%EDI

0x46d5b8 JGE	46d980

0x46d5be MOV	%R15D,%ESI

0x46d5c1 SUB	%EDI,%ESI

0x46d5c3 MOV	%ESI,-0x58(%RBP)

0x46d5c6 CALL	404630 <omp_get_num_threads@plt>

0x46d5cb MOV	%EAX,%R13D

0x46d5ce CALL	404520 <omp_get_thread_num@plt>

0x46d5d3 MOV	%EAX,%ESI

0x46d5d5 MOV	-0x58(%RBP),%EAX

0x46d5d8 XOR	%EDX,%EDX

0x46d5da IMUL	%R14D,%EAX

0x46d5de DIV	%R13D

0x46d5e1 MOV	%EAX,%ECX

0x46d5e3 CMP	%EDX,%ESI

0x46d5e5 JB	46d9e1

0x46d5eb IMUL	%ECX,%ESI

0x46d5ee ADD	%EDX,%ESI

0x46d5f0 LEA	(%RCX,%RSI,1),%R8D

0x46d5f4 MOV	%R8D,-0x84(%RBP)

0x46d5fb CMP	%R8D,%ESI

0x46d5fe JAE	46d980

0x46d604 MOV	%ESI,%EAX

0x46d606 XOR	%EDX,%EDX

0x46d608 DIVL	-0x58(%RBP)

0x46d60b MOV	0x30(%RBX),%R11

0x46d60f MOV	-0x80(%RBP),%R9D

0x46d613 MOV	0x28(%RBX),%R10

0x46d617 MOV	(%RBX),%RDI

0x46d61a MOV	0x18(%RBX),%R14

0x46d61e MOV	%R11,-0x98(%RBP)

0x46d625 MOV	0x10(%RBX),%R11

0x46d629 MOV	%R10,-0x90(%RBP)

0x46d630 MOV	%RDI,-0xa0(%RBP)

0x46d637 MOV	%R14,-0xb0(%RBP)

0x46d63e VMOVQ	0x16aa(%RIP),%XMM9

0x46d646 VMOVSD	0x1e8a(%RIP),%XMM10

0x46d64e VMOVQ	0x2daa(%RIP),%XMM12

0x46d656 VMOVSD	0xf72(%RIP),%XMM11

0x46d65e VXORPD	%XMM7,%XMM7,%XMM7

0x46d662 LEA	(%RDX,%R9,1),%R9D

0x46d666 MOV	%R15D,%EDX

0x46d669 MOV	0x8(%RBX),%R15

0x46d66d MOV	0x20(%RBX),%RBX

0x46d671 ADD	%R12D,%EAX

0x46d674 MOV	%RBX,-0x68(%RBP)

0x46d678 MOV	%R15,-0xa8(%RBP)

0x46d67f SUB	%R9D,%EDX

0x46d682 MOVSXD	%EAX,%R15

0x46d685 NOPL	(%RAX)

(728) 0x46d688 CMP	%EDX,%ECX

(728) 0x46d68a CMOVBE	%ECX,%EDX

(728) 0x46d68d LEA	(%RSI,%RDX,1),%R12D

(728) 0x46d691 MOV	%R12D,-0x54(%RBP)

(728) 0x46d695 CMP	%R12D,%ESI

(728) 0x46d698 JAE	46d9b0

(728) 0x46d69e MOV	-0xa0(%RBP),%RDI

(728) 0x46d6a5 MOV	-0x98(%RBP),%R13

(728) 0x46d6ac MOV	0x8(%RDI),%R14

(728) 0x46d6b0 MOV	-0xb0(%RBP),%RDI

(728) 0x46d6b7 MOV	0x10(%R13),%RAX

(728) 0x46d6bb MOV	-0x90(%RBP),%RSI

(728) 0x46d6c2 MOV	-0xa8(%RBP),%RBX

(728) 0x46d6c9 MOV	%R14,-0x70(%RBP)

(728) 0x46d6cd MOV	0x10(%RDI),%R14

(728) 0x46d6d1 MOV	0x10(%RSI),%R8

(728) 0x46d6d5 MOV	%RAX,-0x78(%RBP)

(728) 0x46d6d9 MOV	(%RSI),%RSI

(728) 0x46d6dc MOV	0x8(%RBX),%RAX

(728) 0x46d6e0 MOV	(%RDI),%RBX

(728) 0x46d6e3 LEA	0x2(%R15),%EDI

(728) 0x46d6e7 MOV	%R14,-0x50(%RBP)

(728) 0x46d6eb MOVSXD	%EDI,%R14

(728) 0x46d6ee MOV	(%R13),%R12

(728) 0x46d6f2 MOV	%RSI,-0x48(%RBP)

(728) 0x46d6f6 LEA	(%RAX,%R15,8),%R13

(728) 0x46d6fa LEA	(%RAX,%R14,8),%R14

(728) 0x46d6fe MOVSXD	%R9D,%RAX

(728) 0x46d701 LEA	-0x1(%RDX),%R9D

(728) 0x46d705 LEA	0x1(%RAX),%RDX

(728) 0x46d709 IMUL	%R15,%RSI

(728) 0x46d70d LEA	(%R9,%RDX,1),%RDI

(728) 0x46d711 LEA	0x1(%R15),%R10

(728) 0x46d715 MOV	%RDI,-0x40(%RBP)

(728) 0x46d719 MOV	-0x48(%RBP),%RDI

(728) 0x46d71d MOV	%R10,%RCX

(728) 0x46d720 IMUL	%R12,%RCX

(728) 0x46d724 LEA	(%R8,%RSI,8),%R9

(728) 0x46d728 ADD	%RDI,%RSI

(728) 0x46d72b LEA	(%R8,%RSI,8),%R8

(728) 0x46d72f MOV	-0x78(%RBP),%RSI

(728) 0x46d733 MOV	%R13,-0x38(%RBP)

(728) 0x46d737 LEA	(%RSI,%RCX,8),%RDI

(728) 0x46d73b SUB	%R12,%RCX

(728) 0x46d73e MOV	%RBX,%R12

(728) 0x46d741 IMUL	%R15,%R12

(728) 0x46d745 LEA	(,%RBX,8),%R13

(728) 0x46d74d MOV	-0x50(%RBP),%RBX

(728) 0x46d751 LEA	(%RSI,%RCX,8),%RSI

(728) 0x46d755 LEA	(%RBX,%R12,8),%RCX

(728) 0x46d759 MOV	%R10,%R12

(728) 0x46d75c IMUL	%R13,%R12

(728) 0x46d760 MOV	%R10,-0x60(%RBP)

(728) 0x46d764 MOV	%RBX,%R10

(728) 0x46d767 ADD	%RBX,%R12

(728) 0x46d76a LEA	-0x1(%R15),%EBX

(728) 0x46d76e MOVSXD	%EBX,%RBX

(728) 0x46d771 IMUL	%R13,%RBX

(728) 0x46d775 MOV	-0x68(%RBP),%R13

(728) 0x46d779 MOV	%R15,-0x50(%RBP)

(728) 0x46d77d MOV	(%R13),%R13

(728) 0x46d781 ADD	%R10,%RBX

(728) 0x46d784 MOV	-0x68(%RBP),%R10

(728) 0x46d788 IMUL	%R15,%R13

(728) 0x46d78c MOV	0x10(%R10),%R10

(728) 0x46d790 MOV	%RBX,-0x48(%RBP)

(728) 0x46d794 LEA	(%R10,%R13,8),%R13

(728) 0x46d798 VMOVSD	0x1e70(%RIP),%XMM6

(728) 0x46d7a0 VMOVSD	0xe30(%RIP),%XMM8

(728) 0x46d7a8 MOV	-0x70(%RBP),%R10

(728) 0x46d7ac MOV	%R14,%R15

(728) 0x46d7af JMP	46d84e

0x46d7b4 NOPL	(%RAX)

  (729) 0x46d7b8 VCOMISD	%XMM13,%XMM7

  (729) 0x46d7bd VANDPD	%XMM9,%XMM13,%XMM15

  (729) 0x46d7c2 VMAXSD	%XMM8,%XMM15,%XMM4

  (729) 0x46d7c7 VMOVAPD	%XMM10,%XMM0

  (729) 0x46d7cb JA	46d998

  (729) 0x46d7d1 VANDPD	%XMM9,%XMM1,%XMM1

  (729) 0x46d7d6 VMAXSD	%XMM8,%XMM1,%XMM2

  (729) 0x46d7db MOV	-0x50(%RBP),%R14

  (729) 0x46d7df MOV	0x10(%R11),%RBX

  (729) 0x46d7e3 VMULSD	%XMM0,%XMM2,%XMM15

  (729) 0x46d7e7 IMUL	(%R11),%R14

  (729) 0x46d7eb ADD	%RAX,%R14

  (729) 0x46d7ee VMULSD	%XMM15,%XMM15,%XMM13

  (729) 0x46d7f3 VFMADD231SD	%XMM4,%XMM4,%XMM13

  (729) 0x46d7f8 VSQRTSD	%XMM13,%XMM13,%XMM13

  (729) 0x46d7fd VMULSD	%XMM5,%XMM13,%XMM5

  (729) 0x46d801 VMULSD	%XMM14,%XMM13,%XMM14

  (729) 0x46d806 VMOVSD	(%RBX,%R14,8),%XMM13

  (729) 0x46d80c VDIVSD	%XMM15,%XMM5,%XMM0

  (729) 0x46d811 VADDSD	%XMM13,%XMM13,%XMM5

  (729) 0x46d816 VDIVSD	%XMM4,%XMM14,%XMM4

  (729) 0x46d81a VANDPD	%XMM9,%XMM0,%XMM1

  (729) 0x46d81f VANDPD	%XMM9,%XMM4,%XMM2

  (729) 0x46d824 VMINSD	%XMM2,%XMM1,%XMM15

  (729) 0x46d828 VMULSD	%XMM3,%XMM15,%XMM3

  (729) 0x46d82c VMULSD	%XMM3,%XMM3,%XMM0

  (729) 0x46d830 VMULSD	%XMM0,%XMM5,%XMM1

  (729) 0x46d834 MOV	-0x40(%RBP),%R14

  (729) 0x46d838 VMOVSD	%XMM1,(%R13,%RAX,8)

  (729) 0x46d83f MOV	%RDX,%RAX

  (729) 0x46d842 CMP	%R14,%RDX

  (729) 0x46d845 JE	46d9c0

  (729) 0x46d84b INC	%RDX

  (729) 0x46d84e VMOVSD	0x8(%R8,%RAX,8),%XMM0

  (729) 0x46d855 VMOVSD	(%R9,%RAX,8),%XMM3

  (729) 0x46d85b VMOVSD	(%R8,%RAX,8),%XMM2

  (729) 0x46d861 VMOVSD	0x8(%R9,%RAX,8),%XMM15

  (729) 0x46d868 VADDSD	%XMM3,%XMM2,%XMM4

  (729) 0x46d86c VADDSD	%XMM15,%XMM0,%XMM1

  (729) 0x46d871 VMOVSD	0x8(%RDI,%RAX,8),%XMM14

  (729) 0x46d877 VMOVSD	0x8(%RSI,%RAX,8),%XMM5

  (729) 0x46d87d VMOVSD	(%RDI,%RAX,8),%XMM17

  (729) 0x46d884 VMOVSD	(%RSI,%RAX,8),%XMM13

  (729) 0x46d889 VADDSD	%XMM0,%XMM2,%XMM16

  (729) 0x46d88f VADDSD	%XMM15,%XMM3,%XMM15

  (729) 0x46d894 VSUBSD	%XMM4,%XMM1,%XMM0

  (729) 0x46d898 VADDSD	%XMM14,%XMM5,%XMM2

  (729) 0x46d89d VADDSD	%XMM13,%XMM5,%XMM4

  (729) 0x46d8a2 VADDSD	%XMM17,%XMM13,%XMM13

  (729) 0x46d8a8 VADDSD	%XMM17,%XMM14,%XMM1

  (729) 0x46d8ae VSUBSD	%XMM15,%XMM16,%XMM19

  (729) 0x46d8b4 VSUBSD	%XMM13,%XMM2,%XMM2

  (729) 0x46d8b9 VSUBSD	%XMM4,%XMM1,%XMM4

  (729) 0x46d8bd VMULSD	%XMM6,%XMM19,%XMM20

  (729) 0x46d8c3 VMULSD	%XMM6,%XMM2,%XMM1

  (729) 0x46d8c7 MOV	-0x38(%RBP),%R14

  (729) 0x46d8cb VMOVSD	(%R10,%RAX,8),%XMM14

  (729) 0x46d8d1 VMOVSD	(%R14),%XMM5

  (729) 0x46d8d6 VMOVSD	0x8(%RCX,%RAX,8),%XMM2

  (729) 0x46d8dc VDIVSD	%XMM14,%XMM1,%XMM13

  (729) 0x46d8e1 VADDSD	0x8(%R10,%RAX,8),%XMM14,%XMM1

  (729) 0x46d8e8 VMOVSD	(%R12,%RAX,8),%XMM15

  (729) 0x46d8ee MOV	-0x48(%RBP),%RBX

  (729) 0x46d8f2 VMULSD	%XMM4,%XMM5,%XMM18

  (729) 0x46d8f8 VMULSD	%XMM6,%XMM4,%XMM4

  (729) 0x46d8fc VFMADD231SD	%XMM0,%XMM14,%XMM18

  (729) 0x46d902 VMULSD	%XMM6,%XMM0,%XMM0

  (729) 0x46d906 VCOMISD	%XMM7,%XMM18

  (729) 0x46d90c VDIVSD	%XMM5,%XMM20,%XMM21

  (729) 0x46d912 VDIVSD	%XMM14,%XMM0,%XMM0

  (729) 0x46d917 VADDSD	%XMM21,%XMM13,%XMM3

  (729) 0x46d91d VSUBSD	-0x8(%RCX,%RAX,8),%XMM2,%XMM13

  (729) 0x46d923 VADDSD	(%R15),%XMM5,%XMM2

  (729) 0x46d928 VDIVSD	%XMM1,%XMM13,%XMM13

  (729) 0x46d92c VSUBSD	(%RBX,%RAX,8),%XMM15,%XMM1

  (729) 0x46d931 VDIVSD	%XMM2,%XMM1,%XMM1

  (729) 0x46d935 VMULSD	%XMM13,%XMM13,%XMM15

  (729) 0x46d93a VDIVSD	%XMM5,%XMM4,%XMM2

  (729) 0x46d93e VMULSD	%XMM1,%XMM1,%XMM22

  (729) 0x46d944 VADDSD	%XMM15,%XMM22,%XMM23

  (729) 0x46d94a VMAXSD	%XMM8,%XMM23,%XMM24

  (729) 0x46d950 VMULSD	%XMM22,%XMM2,%XMM4

  (729) 0x46d956 VMULSD	%XMM13,%XMM1,%XMM2

  (729) 0x46d95b VFMADD132SD	%XMM15,%XMM4,%XMM0

  (729) 0x46d960 VFMADD132SD	%XMM3,%XMM0,%XMM2

  (729) 0x46d965 VDIVSD	%XMM24,%XMM2,%XMM3

  (729) 0x46d96b JAE	46d977

  (729) 0x46d96d VCOMISD	%XMM7,%XMM3

  (729) 0x46d971 JBE	46d7b8

  (729) 0x46d977 VXORPD	%XMM1,%XMM1,%XMM1

  (729) 0x46d97b JMP	46d834

0x46d980 ADD	$0x88,%RSP

0x46d987 POP	%RBX

0x46d988 POP	%R12

0x46d98a POP	%R13

0x46d98c POP	%R14

0x46d98e POP	%R15

0x46d990 POP	%RBP

0x46d991 RET

0x46d992 NOPW	(%RAX,%RAX,1)

  (729) 0x46d998 VCOMISD	%XMM7,%XMM4

  (729) 0x46d99c VXORPD	%XMM12,%XMM4,%XMM13

  (729) 0x46d9a1 VMOVAPD	%XMM13,%XMM4

  (729) 0x46d9a5 JBE	46d9ea

  (729) 0x46d9a7 VMOVAPD	%XMM11,%XMM0

  (729) 0x46d9ab JMP	46d7d1

(728) 0x46d9b0 LEA	0x1(%R15),%RCX

(728) 0x46d9b4 MOV	%ESI,-0x54(%RBP)

(728) 0x46d9b7 MOV	%RCX,-0x60(%RBP)

(728) 0x46d9bb NOPL	(%RAX,%RAX,1)

(728) 0x46d9c0 MOV	-0x60(%RBP),%R15

(728) 0x46d9c4 CMP	%R15D,-0x7c(%RBP)

(728) 0x46d9c8 JLE	46d980

(728) 0x46d9ca MOV	-0x84(%RBP),%ECX

(728) 0x46d9d0 MOV	-0x54(%RBP),%ESI

(728) 0x46d9d3 MOV	-0x58(%RBP),%EDX

(728) 0x46d9d6 MOV	-0x80(%RBP),%R9D

(728) 0x46d9da SUB	%ESI,%ECX

(728) 0x46d9dc JMP	46d688

0x46d9e1 INC	%ECX

0x46d9e3 XOR	%EDX,%EDX

0x46d9e5 JMP	46d5eb

  (729) 0x46d9ea VMOVSD	0x1ae6(%RIP),%XMM0

  (729) 0x46d9f2 JMP	46d7d1

0x46d9f7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.68	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.32	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 2.33 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.00 to 3.00 cycles (5.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	87
nb uops	96
loop length	326
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	8.33	8.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	8.33
cycles	6.10	11.93	8.33	8.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	9%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 46d570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x44(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x7c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x3c(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 46d9e1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x471>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RCX,%RSI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,-0x84(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL -0x58(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x30(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ 0x16aa(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x1e8a(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ 0x2daa(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xf72(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDX,%R9,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46d5eb <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 2.33 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 14.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	87
nb uops	96
loop length	326
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	8.00	8.33	8.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	8.33
cycles	6.10	11.93	8.33	8.33	9.00	6.07	5.90	9.00	9.00	9.00	5.93	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.00
Dispatch	11.93
DIV/SQRT	12.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	9%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 46d570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x44(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x7c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x3c(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 46d9e1 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x471>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RCX,%RSI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,-0x84(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 46d980 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL -0x58(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x30(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ 0x16aa(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x1e8a(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ 0x2daa(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xf72(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDX,%R9,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x88,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46d5eb <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.61	0.75
▼Loop 728 - viscosity.cpp:38-64 - exec–	0.00	0.00
○Loop 729 - viscosity.cpp:39-64 - exec	2.61	0.75

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code