OV - exec - Function revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ...	Module: exec	Source: revert.cpp:34-38 [...]	Coverage (incl. loops): 2.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

0x44a710 PUSH	%RBP

0x44a711 MOV	%RSP,%RBP

0x44a714 PUSH	%R15

0x44a716 PUSH	%R14

0x44a718 PUSH	%R13

0x44a71a PUSH	%R12

0x44a71c PUSH	%RBX

0x44a71d AND	$-0x40,%RSP

0x44a721 ADD	$-0x80,%RSP

0x44a725 MOV	0x28(%RDI),%EAX

0x44a728 MOV	0x2c(%RDI),%ECX

0x44a72b MOV	0x20(%RDI),%EBX

0x44a72e ADD	$0x2,%ECX

0x44a731 LEA	0x1(%RBX),%EDX

0x44a734 LEA	0x1(%RAX),%R12D

0x44a738 MOV	%ECX,0x4c(%RSP)

0x44a73c MOV	%EDX,0x48(%RSP)

0x44a740 MOV	0x24(%RDI),%ESI

0x44a743 CMP	%ECX,%R12D

0x44a746 JGE	44ac43

0x44a74c MOV	%ECX,%EBX

0x44a74e LEA	0x2(%RSI),%R15D

0x44a752 SUB	%R12D,%EBX

0x44a755 CMP	%R15D,%EDX

0x44a758 JGE	44ac43

0x44a75e MOV	%RDI,%R14

0x44a761 MOV	%R15D,%EDI

0x44a764 SUB	%EDX,%EDI

0x44a766 MOV	%EDI,0x78(%RSP)

0x44a76a CALL	404630 <omp_get_num_threads@plt>

0x44a76f MOV	%EAX,%R13D

0x44a772 CALL	404520 <omp_get_thread_num@plt>

0x44a777 MOV	%EAX,%R8D

0x44a77a MOV	0x78(%RSP),%EAX

0x44a77e XOR	%EDX,%EDX

0x44a780 IMUL	%EBX,%EAX

0x44a783 DIV	%R13D

0x44a786 MOV	%EAX,%R13D

0x44a789 CMP	%EDX,%R8D

0x44a78c JB	44ac64

0x44a792 IMUL	%R13D,%R8D

0x44a796 LEA	(%R8,%RDX,1),%R9D

0x44a79a LEA	(%R13,%R9,1),%R10D

0x44a79f MOV	%R10D,0x44(%RSP)

0x44a7a4 CMP	%R10D,%R9D

0x44a7a7 JAE	44ac43

0x44a7ad MOV	%R9D,%EAX

0x44a7b0 XOR	%EDX,%EDX

0x44a7b2 DIVL	0x78(%RSP)

0x44a7b6 MOV	0x48(%RSP),%R11D

0x44a7bb MOV	0x10(%R14),%RBX

0x44a7bf MOV	(%R14),%RSI

0x44a7c2 MOV	%RBX,0x28(%RSP)

0x44a7c7 MOV	%RSI,0x38(%RSP)

0x44a7cc ADD	%EDX,%R11D

0x44a7cf MOV	%R15D,%EDX

0x44a7d2 MOV	0x8(%R14),%R15

0x44a7d6 MOV	0x18(%R14),%R14

0x44a7da MOV	%R11D,0x7c(%RSP)

0x44a7df MOV	%R15,0x30(%RSP)

0x44a7e4 MOV	%R14,0x20(%RSP)

0x44a7e9 ADD	%R12D,%EAX

0x44a7ec SUB	%R11D,%EDX

0x44a7ef MOVSXD	%EAX,%RBX

0x44a7f2 NOPW	(%RAX,%RAX,1)

(350) 0x44a7f8 CMP	%EDX,%R13D

(350) 0x44a7fb CMOVBE	%R13D,%EDX

(350) 0x44a7ff LEA	(%R9,%RDX,1),%R12D

(350) 0x44a803 CMP	%R12D,%R9D

(350) 0x44a806 JAE	44ac16

(350) 0x44a80c MOV	0x38(%RSP),%RCX

(350) 0x44a811 MOV	0x30(%RSP),%RDI

(350) 0x44a816 MOV	0x28(%RSP),%R10

(350) 0x44a81b MOV	0x20(%RSP),%RAX

(350) 0x44a820 MOV	(%RCX),%R8

(350) 0x44a823 MOV	(%RDI),%RSI

(350) 0x44a826 MOV	(%R10),%R11

(350) 0x44a829 MOV	0x10(%R10),%R13

(350) 0x44a82d MOV	(%RAX),%R10

(350) 0x44a830 IMUL	%RBX,%R8

(350) 0x44a834 IMUL	%RBX,%RSI

(350) 0x44a838 IMUL	%RBX,%R11

(350) 0x44a83c IMUL	%RBX,%R10

(350) 0x44a840 MOV	0x10(%RCX),%R15

(350) 0x44a844 MOV	0x10(%RAX),%RCX

(350) 0x44a848 MOV	0x10(%RDI),%R14

(350) 0x44a84c LEA	-0x1(%RDX),%EDI

(350) 0x44a84f MOV	%R8,0x50(%RSP)

(350) 0x44a854 MOV	%RSI,0x58(%RSP)

(350) 0x44a859 MOV	%R11,0x60(%RSP)

(350) 0x44a85e MOV	%RCX,0x70(%RSP)

(350) 0x44a863 MOV	%R10,0x68(%RSP)

(350) 0x44a868 CMP	$0x6,%EDI

(350) 0x44a86b JBE	44ac58

(350) 0x44a871 MOVSXD	0x7c(%RSP),%RAX

(350) 0x44a876 LEA	(%R11,%RAX,1),%R11

(350) 0x44a87a LEA	(%RSI,%RAX,1),%RDI

(350) 0x44a87e LEA	(%R13,%R11,8),%RSI

(350) 0x44a883 MOV	%EDX,%R11D

(350) 0x44a886 LEA	(%R8,%RAX,1),%RCX

(350) 0x44a88a SHR	$0x3,%R11D

(350) 0x44a88e ADD	%R10,%RAX

(350) 0x44a891 MOV	0x70(%RSP),%R10

(350) 0x44a896 SAL	$0x6,%R11

(350) 0x44a89a LEA	(%R15,%RCX,8),%R8

(350) 0x44a89e LEA	(%R10,%RAX,8),%RCX

(350) 0x44a8a2 LEA	-0x40(%R11),%R10

(350) 0x44a8a6 SHR	$0x6,%R10

(350) 0x44a8aa INC	%R10

(350) 0x44a8ad LEA	(%R14,%RDI,8),%RDI

(350) 0x44a8b1 XOR	%EAX,%EAX

(350) 0x44a8b3 AND	$0x7,%R10D

(350) 0x44a8b7 JE	44a9d3

(350) 0x44a8bd CMP	$0x1,%R10

(350) 0x44a8c1 JE	44a9aa

(350) 0x44a8c7 CMP	$0x2,%R10

(350) 0x44a8cb JE	44a98a

(350) 0x44a8d1 CMP	$0x3,%R10

(350) 0x44a8d5 JE	44a96a

(350) 0x44a8db CMP	$0x4,%R10

(350) 0x44a8df JE	44a94a

(350) 0x44a8e1 CMP	$0x5,%R10

(350) 0x44a8e5 JE	44a92a

(350) 0x44a8e7 CMP	$0x6,%R10

(350) 0x44a8eb JE	44a90a

(350) 0x44a8ed VMOVUPD	(%R8),%ZMM0

(350) 0x44a8f3 MOV	$0x40,%EAX

(350) 0x44a8f8 VMOVUPD	%ZMM0,(%RDI)

(350) 0x44a8fe VMOVUPD	(%RSI),%ZMM1

(350) 0x44a904 VMOVUPD	%ZMM1,(%RCX)

(350) 0x44a90a VMOVUPD	(%R8,%RAX,1),%ZMM2

(350) 0x44a911 VMOVUPD	%ZMM2,(%RDI,%RAX,1)

(350) 0x44a918 VMOVUPD	(%RSI,%RAX,1),%ZMM3

(350) 0x44a91f VMOVUPD	%ZMM3,(%RCX,%RAX,1)

(350) 0x44a926 ADD	$0x40,%RAX

(350) 0x44a92a VMOVUPD	(%R8,%RAX,1),%ZMM4

(350) 0x44a931 VMOVUPD	%ZMM4,(%RDI,%RAX,1)

(350) 0x44a938 VMOVUPD	(%RSI,%RAX,1),%ZMM5

(350) 0x44a93f VMOVUPD	%ZMM5,(%RCX,%RAX,1)

(350) 0x44a946 ADD	$0x40,%RAX

(350) 0x44a94a VMOVUPD	(%R8,%RAX,1),%ZMM6

(350) 0x44a951 VMOVUPD	%ZMM6,(%RDI,%RAX,1)

(350) 0x44a958 VMOVUPD	(%RSI,%RAX,1),%ZMM7

(350) 0x44a95f VMOVUPD	%ZMM7,(%RCX,%RAX,1)

(350) 0x44a966 ADD	$0x40,%RAX

(350) 0x44a96a VMOVUPD	(%R8,%RAX,1),%ZMM8

(350) 0x44a971 VMOVUPD	%ZMM8,(%RDI,%RAX,1)

(350) 0x44a978 VMOVUPD	(%RSI,%RAX,1),%ZMM9

(350) 0x44a97f VMOVUPD	%ZMM9,(%RCX,%RAX,1)

(350) 0x44a986 ADD	$0x40,%RAX

(350) 0x44a98a VMOVUPD	(%R8,%RAX,1),%ZMM10

(350) 0x44a991 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(350) 0x44a998 VMOVUPD	(%RSI,%RAX,1),%ZMM11

(350) 0x44a99f VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(350) 0x44a9a6 ADD	$0x40,%RAX

(350) 0x44a9aa VMOVUPD	(%R8,%RAX,1),%ZMM12

(350) 0x44a9b1 VMOVUPD	%ZMM12,(%RDI,%RAX,1)

(350) 0x44a9b8 VMOVUPD	(%RSI,%RAX,1),%ZMM13

(350) 0x44a9bf VMOVUPD	%ZMM13,(%RCX,%RAX,1)

(350) 0x44a9c6 ADD	$0x40,%RAX

(350) 0x44a9ca CMP	%R11,%RAX

(350) 0x44a9cd JE	44aade

  (351) 0x44a9d3 VMOVUPD	(%R8,%RAX,1),%ZMM14

  (351) 0x44a9da VMOVUPD	%ZMM14,(%RDI,%RAX,1)

  (351) 0x44a9e1 VMOVUPD	(%RSI,%RAX,1),%ZMM15

  (351) 0x44a9e8 VMOVUPD	%ZMM15,(%RCX,%RAX,1)

  (351) 0x44a9ef VMOVUPD	0x40(%R8,%RAX,1),%ZMM0

  (351) 0x44a9f7 VMOVUPD	%ZMM0,0x40(%RDI,%RAX,1)

  (351) 0x44a9ff VMOVUPD	0x40(%RSI,%RAX,1),%ZMM1

  (351) 0x44aa07 VMOVUPD	%ZMM1,0x40(%RCX,%RAX,1)

  (351) 0x44aa0f VMOVUPD	0x80(%R8,%RAX,1),%ZMM2

  (351) 0x44aa17 VMOVUPD	%ZMM2,0x80(%RDI,%RAX,1)

  (351) 0x44aa1f VMOVUPD	0x80(%RSI,%RAX,1),%ZMM3

  (351) 0x44aa27 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (351) 0x44aa2f VMOVUPD	0xc0(%R8,%RAX,1),%ZMM4

  (351) 0x44aa37 VMOVUPD	%ZMM4,0xc0(%RDI,%RAX,1)

  (351) 0x44aa3f VMOVUPD	0xc0(%RSI,%RAX,1),%ZMM5

  (351) 0x44aa47 VMOVUPD	%ZMM5,0xc0(%RCX,%RAX,1)

  (351) 0x44aa4f VMOVUPD	0x100(%R8,%RAX,1),%ZMM6

  (351) 0x44aa57 VMOVUPD	%ZMM6,0x100(%RDI,%RAX,1)

  (351) 0x44aa5f VMOVUPD	0x100(%RSI,%RAX,1),%ZMM7

  (351) 0x44aa67 VMOVUPD	%ZMM7,0x100(%RCX,%RAX,1)

  (351) 0x44aa6f VMOVUPD	0x140(%R8,%RAX,1),%ZMM8

  (351) 0x44aa77 VMOVUPD	%ZMM8,0x140(%RDI,%RAX,1)

  (351) 0x44aa7f VMOVUPD	0x140(%RSI,%RAX,1),%ZMM9

  (351) 0x44aa87 VMOVUPD	%ZMM9,0x140(%RCX,%RAX,1)

  (351) 0x44aa8f VMOVUPD	0x180(%R8,%RAX,1),%ZMM10

  (351) 0x44aa97 VMOVUPD	%ZMM10,0x180(%RDI,%RAX,1)

  (351) 0x44aa9f VMOVUPD	0x180(%RSI,%RAX,1),%ZMM11

  (351) 0x44aaa7 VMOVUPD	%ZMM11,0x180(%RCX,%RAX,1)

  (351) 0x44aaaf VMOVUPD	0x1c0(%R8,%RAX,1),%ZMM12

  (351) 0x44aab7 VMOVUPD	%ZMM12,0x1c0(%RDI,%RAX,1)

  (351) 0x44aabf VMOVUPD	0x1c0(%RSI,%RAX,1),%ZMM13

  (351) 0x44aac7 VMOVUPD	%ZMM13,0x1c0(%RCX,%RAX,1)

  (351) 0x44aacf ADD	$0x200,%RAX

  (351) 0x44aad5 CMP	%R11,%RAX

  (351) 0x44aad8 JNE	44a9d3

(350) 0x44aade MOV	0x7c(%RSP),%ESI

(350) 0x44aae2 MOV	%EDX,%R8D

(350) 0x44aae5 AND	$-0x8,%R8D

(350) 0x44aae9 ADD	%R8D,%ESI

(350) 0x44aaec ADD	%R8D,%R9D

(350) 0x44aaef TEST	$0x7,%DL

(350) 0x44aaf2 JE	44ac13

(350) 0x44aaf8 SUB	%R8D,%EDX

(350) 0x44aafb LEA	-0x1(%RDX),%EDI

(350) 0x44aafe CMP	$0x2,%EDI

(350) 0x44ab01 JBE	44ab65

(350) 0x44ab03 MOVSXD	0x7c(%RSP),%RCX

(350) 0x44ab08 MOV	0x50(%RSP),%R11

(350) 0x44ab0d MOV	0x58(%RSP),%R10

(350) 0x44ab12 ADD	%RCX,%R11

(350) 0x44ab15 ADD	%R8,%R11

(350) 0x44ab18 MOV	0x60(%RSP),%RAX

(350) 0x44ab1d ADD	%RCX,%R10

(350) 0x44ab20 VMOVUPD	(%R15,%R11,8),%YMM14

(350) 0x44ab26 MOV	0x68(%RSP),%RDI

(350) 0x44ab2b ADD	%R8,%R10

(350) 0x44ab2e ADD	%RCX,%RAX

(350) 0x44ab31 ADD	%R8,%RAX

(350) 0x44ab34 VMOVUPD	%YMM14,(%R14,%R10,8)

(350) 0x44ab3a ADD	%RDI,%RCX

(350) 0x44ab3d ADD	%R8,%RCX

(350) 0x44ab40 VMOVUPD	(%R13,%RAX,8),%YMM15

(350) 0x44ab47 MOV	0x70(%RSP),%R8

(350) 0x44ab4c VMOVUPD	%YMM15,(%R8,%RCX,8)

(350) 0x44ab52 MOV	%EDX,%ECX

(350) 0x44ab54 AND	$-0x4,%ECX

(350) 0x44ab57 ADD	%ECX,%ESI

(350) 0x44ab59 ADD	%ECX,%R9D

(350) 0x44ab5c AND	$0x3,%EDX

(350) 0x44ab5f JE	44ac13

(350) 0x44ab65 MOV	0x50(%RSP),%RDI

(350) 0x44ab6a MOVSXD	%ESI,%RAX

(350) 0x44ab6d LEA	(%RDI,%RAX,1),%RDX

(350) 0x44ab71 MOV	0x58(%RSP),%RCX

(350) 0x44ab76 VMOVSD	(%R15,%RDX,8),%XMM0

(350) 0x44ab7c MOV	0x60(%RSP),%R8

(350) 0x44ab81 LEA	(%RCX,%RAX,1),%R11

(350) 0x44ab85 VMOVSD	%XMM0,(%R14,%R11,8)

(350) 0x44ab8b LEA	(%R8,%RAX,1),%R10

(350) 0x44ab8f VMOVSD	(%R13,%R10,8),%XMM1

(350) 0x44ab96 MOV	0x68(%RSP),%R10

(350) 0x44ab9b MOV	0x70(%RSP),%R11

(350) 0x44aba0 ADD	%R10,%RAX

(350) 0x44aba3 VMOVSD	%XMM1,(%R11,%RAX,8)

(350) 0x44aba9 LEA	0x1(%R9),%EAX

(350) 0x44abad CMP	%R12D,%EAX

(350) 0x44abb0 JAE	44ac13

(350) 0x44abb2 LEA	0x1(%RSI),%EAX

(350) 0x44abb5 CLTQ

(350) 0x44abb7 LEA	(%RDI,%RAX,1),%RDX

(350) 0x44abbb VMOVSD	(%R15,%RDX,8),%XMM2

(350) 0x44abc1 LEA	(%RCX,%RAX,1),%RDX

(350) 0x44abc5 VMOVSD	%XMM2,(%R14,%RDX,8)

(350) 0x44abcb LEA	(%R8,%RAX,1),%RDX

(350) 0x44abcf VMOVSD	(%R13,%RDX,8),%XMM3

(350) 0x44abd6 ADD	%R10,%RAX

(350) 0x44abd9 ADD	$0x2,%R9D

(350) 0x44abdd VMOVSD	%XMM3,(%R11,%RAX,8)

(350) 0x44abe3 CMP	%R12D,%R9D

(350) 0x44abe6 JAE	44ac13

(350) 0x44abe8 ADD	$0x2,%ESI

(350) 0x44abeb MOVSXD	%ESI,%R9

(350) 0x44abee ADD	%R9,%RDI

(350) 0x44abf1 VMOVSD	(%R15,%RDI,8),%XMM4

(350) 0x44abf7 ADD	%R9,%RCX

(350) 0x44abfa VMOVSD	%XMM4,(%R14,%RCX,8)

(350) 0x44ac00 ADD	%R9,%R8

(350) 0x44ac03 VMOVSD	(%R13,%R8,8),%XMM5

(350) 0x44ac0a ADD	%R9,%R10

(350) 0x44ac0d VMOVSD	%XMM5,(%R11,%R10,8)

(350) 0x44ac13 MOV	%R12D,%R9D

(350) 0x44ac16 INC	%RBX

(350) 0x44ac19 CMP	%EBX,0x4c(%RSP)

(350) 0x44ac1d JLE	44ac40

(350) 0x44ac1f MOV	0x44(%RSP),%R13D

(350) 0x44ac24 MOV	0x48(%RSP),%R12D

(350) 0x44ac29 MOV	0x78(%RSP),%EDX

(350) 0x44ac2d MOV	%R12D,0x7c(%RSP)

(350) 0x44ac32 SUB	%R9D,%R13D

(350) 0x44ac35 JMP	44a7f8

0x44ac3a NOPW	(%RAX,%RAX,1)

0x44ac40 VZEROUPPER

0x44ac43 LEA	-0x28(%RBP),%RSP

0x44ac47 POP	%RBX

0x44ac48 POP	%R12

0x44ac4a POP	%R13

0x44ac4c POP	%R14

0x44ac4e POP	%R15

0x44ac50 POP	%RBP

0x44ac51 RET

0x44ac52 NOPW	(%RAX,%RAX,1)

(350) 0x44ac58 MOV	0x7c(%RSP),%ESI

(350) 0x44ac5c XOR	%R8D,%R8D

(350) 0x44ac5f JMP	44aaf8

0x44ac64 INC	%R13D

0x44ac67 XOR	%EDX,%EDX

0x44ac69 JMP	44a792

0x44ac6e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 44a710

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44ac64 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 44a792 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 44a710

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44ac64 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 44ac43 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 44a792 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.32	0.67
▼Loop 350 - revert.cpp:36-38 - exec–	0.00	0.01
○Loop 351 - revert.cpp:37-38 - exec	2.32	0.67

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code