OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:34-38 [...]	Coverage (incl. loops): 2.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density0(i, j) = density1(i, j);

38:       energy0(i, j) = energy1(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x449f60 PUSH	%RBP

0x449f61 MOV	%RSP,%RBP

0x449f64 PUSH	%R15

0x449f66 PUSH	%R14

0x449f68 PUSH	%R13

0x449f6a PUSH	%R12

0x449f6c PUSH	%RBX

0x449f6d AND	$-0x40,%RSP

0x449f71 ADD	$-0x80,%RSP

0x449f75 MOV	0x28(%RDI),%EAX

0x449f78 MOV	0x2c(%RDI),%ECX

0x449f7b MOV	0x20(%RDI),%EBX

0x449f7e ADD	$0x2,%ECX

0x449f81 LEA	0x1(%RBX),%EDX

0x449f84 LEA	0x1(%RAX),%R12D

0x449f88 MOV	%ECX,0x4c(%RSP)

0x449f8c MOV	%EDX,0x48(%RSP)

0x449f90 MOV	0x24(%RDI),%ESI

0x449f93 CMP	%ECX,%R12D

0x449f96 JGE	44a493

0x449f9c MOV	%ECX,%EBX

0x449f9e LEA	0x2(%RSI),%R15D

0x449fa2 SUB	%R12D,%EBX

0x449fa5 CMP	%R15D,%EDX

0x449fa8 JGE	44a493

0x449fae MOV	%RDI,%R14

0x449fb1 MOV	%R15D,%EDI

0x449fb4 SUB	%EDX,%EDI

0x449fb6 MOV	%EDI,0x78(%RSP)

0x449fba CALL	404630 <omp_get_num_threads@plt>

0x449fbf MOV	%EAX,%R13D

0x449fc2 CALL	404520 <omp_get_thread_num@plt>

0x449fc7 MOV	%EAX,%R8D

0x449fca MOV	0x78(%RSP),%EAX

0x449fce XOR	%EDX,%EDX

0x449fd0 IMUL	%EBX,%EAX

0x449fd3 DIV	%R13D

0x449fd6 MOV	%EAX,%R13D

0x449fd9 CMP	%EDX,%R8D

0x449fdc JB	44a4b4

0x449fe2 IMUL	%R13D,%R8D

0x449fe6 LEA	(%R8,%RDX,1),%R9D

0x449fea LEA	(%R13,%R9,1),%R10D

0x449fef MOV	%R10D,0x44(%RSP)

0x449ff4 CMP	%R10D,%R9D

0x449ff7 JAE	44a493

0x449ffd MOV	%R9D,%EAX

0x44a000 XOR	%EDX,%EDX

0x44a002 DIVL	0x78(%RSP)

0x44a006 MOV	0x48(%RSP),%R11D

0x44a00b MOV	0x18(%R14),%RBX

0x44a00f MOV	0x8(%R14),%RSI

0x44a013 MOV	%RBX,0x28(%RSP)

0x44a018 MOV	%RSI,0x38(%RSP)

0x44a01d ADD	%EDX,%R11D

0x44a020 MOV	%R15D,%EDX

0x44a023 MOV	(%R14),%R15

0x44a026 MOV	0x10(%R14),%R14

0x44a02a MOV	%R11D,0x7c(%RSP)

0x44a02f MOV	%R15,0x30(%RSP)

0x44a034 MOV	%R14,0x20(%RSP)

0x44a039 ADD	%R12D,%EAX

0x44a03c SUB	%R11D,%EDX

0x44a03f MOVSXD	%EAX,%RBX

0x44a042 NOPW	(%RAX,%RAX,1)

(347) 0x44a048 CMP	%EDX,%R13D

(347) 0x44a04b CMOVBE	%R13D,%EDX

(347) 0x44a04f LEA	(%R9,%RDX,1),%R12D

(347) 0x44a053 CMP	%R12D,%R9D

(347) 0x44a056 JAE	44a466

(347) 0x44a05c MOV	0x38(%RSP),%RCX

(347) 0x44a061 MOV	0x30(%RSP),%RDI

(347) 0x44a066 MOV	0x28(%RSP),%R10

(347) 0x44a06b MOV	0x20(%RSP),%RAX

(347) 0x44a070 MOV	(%RCX),%R8

(347) 0x44a073 MOV	(%RDI),%RSI

(347) 0x44a076 MOV	(%R10),%R11

(347) 0x44a079 MOV	0x10(%R10),%R13

(347) 0x44a07d MOV	(%RAX),%R10

(347) 0x44a080 IMUL	%RBX,%R8

(347) 0x44a084 IMUL	%RBX,%RSI

(347) 0x44a088 IMUL	%RBX,%R11

(347) 0x44a08c IMUL	%RBX,%R10

(347) 0x44a090 MOV	0x10(%RCX),%R15

(347) 0x44a094 MOV	0x10(%RAX),%RCX

(347) 0x44a098 MOV	0x10(%RDI),%R14

(347) 0x44a09c LEA	-0x1(%RDX),%EDI

(347) 0x44a09f MOV	%R8,0x50(%RSP)

(347) 0x44a0a4 MOV	%RSI,0x58(%RSP)

(347) 0x44a0a9 MOV	%R11,0x60(%RSP)

(347) 0x44a0ae MOV	%RCX,0x70(%RSP)

(347) 0x44a0b3 MOV	%R10,0x68(%RSP)

(347) 0x44a0b8 CMP	$0x6,%EDI

(347) 0x44a0bb JBE	44a4a8

(347) 0x44a0c1 MOVSXD	0x7c(%RSP),%RAX

(347) 0x44a0c6 LEA	(%R11,%RAX,1),%R11

(347) 0x44a0ca LEA	(%RSI,%RAX,1),%RDI

(347) 0x44a0ce LEA	(%R13,%R11,8),%RSI

(347) 0x44a0d3 MOV	%EDX,%R11D

(347) 0x44a0d6 LEA	(%R8,%RAX,1),%RCX

(347) 0x44a0da SHR	$0x3,%R11D

(347) 0x44a0de ADD	%R10,%RAX

(347) 0x44a0e1 MOV	0x70(%RSP),%R10

(347) 0x44a0e6 SAL	$0x6,%R11

(347) 0x44a0ea LEA	(%R15,%RCX,8),%R8

(347) 0x44a0ee LEA	(%R10,%RAX,8),%RCX

(347) 0x44a0f2 LEA	-0x40(%R11),%R10

(347) 0x44a0f6 SHR	$0x6,%R10

(347) 0x44a0fa INC	%R10

(347) 0x44a0fd LEA	(%R14,%RDI,8),%RDI

(347) 0x44a101 XOR	%EAX,%EAX

(347) 0x44a103 AND	$0x7,%R10D

(347) 0x44a107 JE	44a223

(347) 0x44a10d CMP	$0x1,%R10

(347) 0x44a111 JE	44a1fa

(347) 0x44a117 CMP	$0x2,%R10

(347) 0x44a11b JE	44a1da

(347) 0x44a121 CMP	$0x3,%R10

(347) 0x44a125 JE	44a1ba

(347) 0x44a12b CMP	$0x4,%R10

(347) 0x44a12f JE	44a19a

(347) 0x44a131 CMP	$0x5,%R10

(347) 0x44a135 JE	44a17a

(347) 0x44a137 CMP	$0x6,%R10

(347) 0x44a13b JE	44a15a

(347) 0x44a13d VMOVUPD	(%R8),%ZMM0

(347) 0x44a143 MOV	$0x40,%EAX

(347) 0x44a148 VMOVUPD	%ZMM0,(%RDI)

(347) 0x44a14e VMOVUPD	(%RSI),%ZMM1

(347) 0x44a154 VMOVUPD	%ZMM1,(%RCX)

(347) 0x44a15a VMOVUPD	(%R8,%RAX,1),%ZMM2

(347) 0x44a161 VMOVUPD	%ZMM2,(%RDI,%RAX,1)

(347) 0x44a168 VMOVUPD	(%RSI,%RAX,1),%ZMM3

(347) 0x44a16f VMOVUPD	%ZMM3,(%RCX,%RAX,1)

(347) 0x44a176 ADD	$0x40,%RAX

(347) 0x44a17a VMOVUPD	(%R8,%RAX,1),%ZMM4

(347) 0x44a181 VMOVUPD	%ZMM4,(%RDI,%RAX,1)

(347) 0x44a188 VMOVUPD	(%RSI,%RAX,1),%ZMM5

(347) 0x44a18f VMOVUPD	%ZMM5,(%RCX,%RAX,1)

(347) 0x44a196 ADD	$0x40,%RAX

(347) 0x44a19a VMOVUPD	(%R8,%RAX,1),%ZMM6

(347) 0x44a1a1 VMOVUPD	%ZMM6,(%RDI,%RAX,1)

(347) 0x44a1a8 VMOVUPD	(%RSI,%RAX,1),%ZMM7

(347) 0x44a1af VMOVUPD	%ZMM7,(%RCX,%RAX,1)

(347) 0x44a1b6 ADD	$0x40,%RAX

(347) 0x44a1ba VMOVUPD	(%R8,%RAX,1),%ZMM8

(347) 0x44a1c1 VMOVUPD	%ZMM8,(%RDI,%RAX,1)

(347) 0x44a1c8 VMOVUPD	(%RSI,%RAX,1),%ZMM9

(347) 0x44a1cf VMOVUPD	%ZMM9,(%RCX,%RAX,1)

(347) 0x44a1d6 ADD	$0x40,%RAX

(347) 0x44a1da VMOVUPD	(%R8,%RAX,1),%ZMM10

(347) 0x44a1e1 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(347) 0x44a1e8 VMOVUPD	(%RSI,%RAX,1),%ZMM11

(347) 0x44a1ef VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(347) 0x44a1f6 ADD	$0x40,%RAX

(347) 0x44a1fa VMOVUPD	(%R8,%RAX,1),%ZMM12

(347) 0x44a201 VMOVUPD	%ZMM12,(%RDI,%RAX,1)

(347) 0x44a208 VMOVUPD	(%RSI,%RAX,1),%ZMM13

(347) 0x44a20f VMOVUPD	%ZMM13,(%RCX,%RAX,1)

(347) 0x44a216 ADD	$0x40,%RAX

(347) 0x44a21a CMP	%R11,%RAX

(347) 0x44a21d JE	44a32e

  (348) 0x44a223 VMOVUPD	(%R8,%RAX,1),%ZMM14

  (348) 0x44a22a VMOVUPD	%ZMM14,(%RDI,%RAX,1)

  (348) 0x44a231 VMOVUPD	(%RSI,%RAX,1),%ZMM15

  (348) 0x44a238 VMOVUPD	%ZMM15,(%RCX,%RAX,1)

  (348) 0x44a23f VMOVUPD	0x40(%R8,%RAX,1),%ZMM0

  (348) 0x44a247 VMOVUPD	%ZMM0,0x40(%RDI,%RAX,1)

  (348) 0x44a24f VMOVUPD	0x40(%RSI,%RAX,1),%ZMM1

  (348) 0x44a257 VMOVUPD	%ZMM1,0x40(%RCX,%RAX,1)

  (348) 0x44a25f VMOVUPD	0x80(%R8,%RAX,1),%ZMM2

  (348) 0x44a267 VMOVUPD	%ZMM2,0x80(%RDI,%RAX,1)

  (348) 0x44a26f VMOVUPD	0x80(%RSI,%RAX,1),%ZMM3

  (348) 0x44a277 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (348) 0x44a27f VMOVUPD	0xc0(%R8,%RAX,1),%ZMM4

  (348) 0x44a287 VMOVUPD	%ZMM4,0xc0(%RDI,%RAX,1)

  (348) 0x44a28f VMOVUPD	0xc0(%RSI,%RAX,1),%ZMM5

  (348) 0x44a297 VMOVUPD	%ZMM5,0xc0(%RCX,%RAX,1)

  (348) 0x44a29f VMOVUPD	0x100(%R8,%RAX,1),%ZMM6

  (348) 0x44a2a7 VMOVUPD	%ZMM6,0x100(%RDI,%RAX,1)

  (348) 0x44a2af VMOVUPD	0x100(%RSI,%RAX,1),%ZMM7

  (348) 0x44a2b7 VMOVUPD	%ZMM7,0x100(%RCX,%RAX,1)

  (348) 0x44a2bf VMOVUPD	0x140(%R8,%RAX,1),%ZMM8

  (348) 0x44a2c7 VMOVUPD	%ZMM8,0x140(%RDI,%RAX,1)

  (348) 0x44a2cf VMOVUPD	0x140(%RSI,%RAX,1),%ZMM9

  (348) 0x44a2d7 VMOVUPD	%ZMM9,0x140(%RCX,%RAX,1)

  (348) 0x44a2df VMOVUPD	0x180(%R8,%RAX,1),%ZMM10

  (348) 0x44a2e7 VMOVUPD	%ZMM10,0x180(%RDI,%RAX,1)

  (348) 0x44a2ef VMOVUPD	0x180(%RSI,%RAX,1),%ZMM11

  (348) 0x44a2f7 VMOVUPD	%ZMM11,0x180(%RCX,%RAX,1)

  (348) 0x44a2ff VMOVUPD	0x1c0(%R8,%RAX,1),%ZMM12

  (348) 0x44a307 VMOVUPD	%ZMM12,0x1c0(%RDI,%RAX,1)

  (348) 0x44a30f VMOVUPD	0x1c0(%RSI,%RAX,1),%ZMM13

  (348) 0x44a317 VMOVUPD	%ZMM13,0x1c0(%RCX,%RAX,1)

  (348) 0x44a31f ADD	$0x200,%RAX

  (348) 0x44a325 CMP	%R11,%RAX

  (348) 0x44a328 JNE	44a223

(347) 0x44a32e MOV	0x7c(%RSP),%ESI

(347) 0x44a332 MOV	%EDX,%R8D

(347) 0x44a335 AND	$-0x8,%R8D

(347) 0x44a339 ADD	%R8D,%ESI

(347) 0x44a33c ADD	%R8D,%R9D

(347) 0x44a33f TEST	$0x7,%DL

(347) 0x44a342 JE	44a463

(347) 0x44a348 SUB	%R8D,%EDX

(347) 0x44a34b LEA	-0x1(%RDX),%EDI

(347) 0x44a34e CMP	$0x2,%EDI

(347) 0x44a351 JBE	44a3b5

(347) 0x44a353 MOVSXD	0x7c(%RSP),%RCX

(347) 0x44a358 MOV	0x50(%RSP),%R11

(347) 0x44a35d MOV	0x58(%RSP),%R10

(347) 0x44a362 ADD	%RCX,%R11

(347) 0x44a365 ADD	%R8,%R11

(347) 0x44a368 MOV	0x60(%RSP),%RAX

(347) 0x44a36d ADD	%RCX,%R10

(347) 0x44a370 VMOVUPD	(%R15,%R11,8),%YMM14

(347) 0x44a376 MOV	0x68(%RSP),%RDI

(347) 0x44a37b ADD	%R8,%R10

(347) 0x44a37e ADD	%RCX,%RAX

(347) 0x44a381 ADD	%R8,%RAX

(347) 0x44a384 VMOVUPD	%YMM14,(%R14,%R10,8)

(347) 0x44a38a ADD	%RDI,%RCX

(347) 0x44a38d ADD	%R8,%RCX

(347) 0x44a390 VMOVUPD	(%R13,%RAX,8),%YMM15

(347) 0x44a397 MOV	0x70(%RSP),%R8

(347) 0x44a39c VMOVUPD	%YMM15,(%R8,%RCX,8)

(347) 0x44a3a2 MOV	%EDX,%ECX

(347) 0x44a3a4 AND	$-0x4,%ECX

(347) 0x44a3a7 ADD	%ECX,%ESI

(347) 0x44a3a9 ADD	%ECX,%R9D

(347) 0x44a3ac AND	$0x3,%EDX

(347) 0x44a3af JE	44a463

(347) 0x44a3b5 MOV	0x50(%RSP),%RDI

(347) 0x44a3ba MOVSXD	%ESI,%RAX

(347) 0x44a3bd LEA	(%RDI,%RAX,1),%RDX

(347) 0x44a3c1 MOV	0x58(%RSP),%RCX

(347) 0x44a3c6 VMOVSD	(%R15,%RDX,8),%XMM0

(347) 0x44a3cc MOV	0x60(%RSP),%R8

(347) 0x44a3d1 LEA	(%RCX,%RAX,1),%R11

(347) 0x44a3d5 VMOVSD	%XMM0,(%R14,%R11,8)

(347) 0x44a3db LEA	(%R8,%RAX,1),%R10

(347) 0x44a3df VMOVSD	(%R13,%R10,8),%XMM1

(347) 0x44a3e6 MOV	0x68(%RSP),%R10

(347) 0x44a3eb MOV	0x70(%RSP),%R11

(347) 0x44a3f0 ADD	%R10,%RAX

(347) 0x44a3f3 VMOVSD	%XMM1,(%R11,%RAX,8)

(347) 0x44a3f9 LEA	0x1(%R9),%EAX

(347) 0x44a3fd CMP	%R12D,%EAX

(347) 0x44a400 JAE	44a463

(347) 0x44a402 LEA	0x1(%RSI),%EAX

(347) 0x44a405 CLTQ

(347) 0x44a407 LEA	(%RDI,%RAX,1),%RDX

(347) 0x44a40b VMOVSD	(%R15,%RDX,8),%XMM2

(347) 0x44a411 LEA	(%RCX,%RAX,1),%RDX

(347) 0x44a415 VMOVSD	%XMM2,(%R14,%RDX,8)

(347) 0x44a41b LEA	(%R8,%RAX,1),%RDX

(347) 0x44a41f VMOVSD	(%R13,%RDX,8),%XMM3

(347) 0x44a426 ADD	%R10,%RAX

(347) 0x44a429 ADD	$0x2,%R9D

(347) 0x44a42d VMOVSD	%XMM3,(%R11,%RAX,8)

(347) 0x44a433 CMP	%R12D,%R9D

(347) 0x44a436 JAE	44a463

(347) 0x44a438 ADD	$0x2,%ESI

(347) 0x44a43b MOVSXD	%ESI,%R9

(347) 0x44a43e ADD	%R9,%RDI

(347) 0x44a441 VMOVSD	(%R15,%RDI,8),%XMM4

(347) 0x44a447 ADD	%R9,%RCX

(347) 0x44a44a VMOVSD	%XMM4,(%R14,%RCX,8)

(347) 0x44a450 ADD	%R9,%R8

(347) 0x44a453 VMOVSD	(%R13,%R8,8),%XMM5

(347) 0x44a45a ADD	%R9,%R10

(347) 0x44a45d VMOVSD	%XMM5,(%R11,%R10,8)

(347) 0x44a463 MOV	%R12D,%R9D

(347) 0x44a466 INC	%RBX

(347) 0x44a469 CMP	%EBX,0x4c(%RSP)

(347) 0x44a46d JLE	44a490

(347) 0x44a46f MOV	0x44(%RSP),%R13D

(347) 0x44a474 MOV	0x48(%RSP),%R12D

(347) 0x44a479 MOV	0x78(%RSP),%EDX

(347) 0x44a47d MOV	%R12D,0x7c(%RSP)

(347) 0x44a482 SUB	%R9D,%R13D

(347) 0x44a485 JMP	44a048

0x44a48a NOPW	(%RAX,%RAX,1)

0x44a490 VZEROUPPER

0x44a493 LEA	-0x28(%RBP),%RSP

0x44a497 POP	%RBX

0x44a498 POP	%R12

0x44a49a POP	%R13

0x44a49c POP	%R14

0x44a49e POP	%R15

0x44a4a0 POP	%RBP

0x44a4a1 RET

0x44a4a2 NOPW	(%RAX,%RAX,1)

(347) 0x44a4a8 MOV	0x7c(%RSP),%ESI

(347) 0x44a4ac XOR	%R8D,%R8D

(347) 0x44a4af JMP	44a348

0x44a4b4 INC	%R13D

0x44a4b7 XOR	%EDX,%EDX

0x44a4b9 JMP	449fe2

0x44a4be XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
○97.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 449f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44a4b4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 449fe2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 449f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44a4b4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 44a493 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 449fe2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.32	0.67
▼Loop 347 - reset_field.cpp:36-38 - exec–	0.00	0.01
○Loop 348 - reset_field.cpp:37-38 - exec	2.31	0.67

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Vectorization

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code