OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:44-48 [...]	Coverage (incl. loops): 2.70% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

46:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

47:       xvel0(i, j) = xvel1(i, j);

48:       yvel0(i, j) = yvel1(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x449a00 PUSH	%RBP

0x449a01 MOV	%RSP,%RBP

0x449a04 PUSH	%R15

0x449a06 PUSH	%R14

0x449a08 PUSH	%R13

0x449a0a PUSH	%R12

0x449a0c PUSH	%RBX

0x449a0d AND	$-0x40,%RSP

0x449a11 ADD	$-0x80,%RSP

0x449a15 MOV	0x28(%RDI),%EAX

0x449a18 MOV	0x2c(%RDI),%ECX

0x449a1b MOV	0x20(%RDI),%EBX

0x449a1e ADD	$0x3,%ECX

0x449a21 LEA	0x1(%RBX),%EDX

0x449a24 LEA	0x1(%RAX),%R12D

0x449a28 MOV	%ECX,0x4c(%RSP)

0x449a2c MOV	%EDX,0x48(%RSP)

0x449a30 MOV	0x24(%RDI),%ESI

0x449a33 CMP	%ECX,%R12D

0x449a36 JGE	449f33

0x449a3c MOV	%ECX,%EBX

0x449a3e LEA	0x3(%RSI),%R15D

0x449a42 SUB	%R12D,%EBX

0x449a45 CMP	%R15D,%EDX

0x449a48 JGE	449f33

0x449a4e MOV	%RDI,%R14

0x449a51 MOV	%R15D,%EDI

0x449a54 SUB	%EDX,%EDI

0x449a56 MOV	%EDI,0x78(%RSP)

0x449a5a CALL	404630 <omp_get_num_threads@plt>

0x449a5f MOV	%EAX,%R13D

0x449a62 CALL	404520 <omp_get_thread_num@plt>

0x449a67 MOV	%EAX,%R8D

0x449a6a MOV	0x78(%RSP),%EAX

0x449a6e XOR	%EDX,%EDX

0x449a70 IMUL	%EBX,%EAX

0x449a73 DIV	%R13D

0x449a76 MOV	%EAX,%R13D

0x449a79 CMP	%EDX,%R8D

0x449a7c JB	449f54

0x449a82 IMUL	%R13D,%R8D

0x449a86 LEA	(%R8,%RDX,1),%R9D

0x449a8a LEA	(%R13,%R9,1),%R10D

0x449a8f MOV	%R10D,0x44(%RSP)

0x449a94 CMP	%R10D,%R9D

0x449a97 JAE	449f33

0x449a9d MOV	%R9D,%EAX

0x449aa0 XOR	%EDX,%EDX

0x449aa2 DIVL	0x78(%RSP)

0x449aa6 MOV	0x48(%RSP),%R11D

0x449aab MOV	0x18(%R14),%RBX

0x449aaf MOV	0x8(%R14),%RSI

0x449ab3 MOV	%RBX,0x28(%RSP)

0x449ab8 MOV	%RSI,0x38(%RSP)

0x449abd ADD	%EDX,%R11D

0x449ac0 MOV	%R15D,%EDX

0x449ac3 MOV	(%R14),%R15

0x449ac6 MOV	0x10(%R14),%R14

0x449aca MOV	%R11D,0x7c(%RSP)

0x449acf MOV	%R15,0x30(%RSP)

0x449ad4 MOV	%R14,0x20(%RSP)

0x449ad9 ADD	%R12D,%EAX

0x449adc SUB	%R11D,%EDX

0x449adf MOVSXD	%EAX,%RBX

0x449ae2 NOPW	(%RAX,%RAX,1)

(345) 0x449ae8 CMP	%EDX,%R13D

(345) 0x449aeb CMOVBE	%R13D,%EDX

(345) 0x449aef LEA	(%R9,%RDX,1),%R12D

(345) 0x449af3 CMP	%R12D,%R9D

(345) 0x449af6 JAE	449f06

(345) 0x449afc MOV	0x38(%RSP),%RCX

(345) 0x449b01 MOV	0x30(%RSP),%RDI

(345) 0x449b06 MOV	0x28(%RSP),%R10

(345) 0x449b0b MOV	0x20(%RSP),%RAX

(345) 0x449b10 MOV	(%RCX),%R8

(345) 0x449b13 MOV	(%RDI),%RSI

(345) 0x449b16 MOV	(%R10),%R11

(345) 0x449b19 MOV	0x10(%R10),%R13

(345) 0x449b1d MOV	(%RAX),%R10

(345) 0x449b20 IMUL	%RBX,%R8

(345) 0x449b24 IMUL	%RBX,%RSI

(345) 0x449b28 IMUL	%RBX,%R11

(345) 0x449b2c IMUL	%RBX,%R10

(345) 0x449b30 MOV	0x10(%RCX),%R15

(345) 0x449b34 MOV	0x10(%RAX),%RCX

(345) 0x449b38 MOV	0x10(%RDI),%R14

(345) 0x449b3c LEA	-0x1(%RDX),%EDI

(345) 0x449b3f MOV	%R8,0x50(%RSP)

(345) 0x449b44 MOV	%RSI,0x58(%RSP)

(345) 0x449b49 MOV	%R11,0x60(%RSP)

(345) 0x449b4e MOV	%RCX,0x70(%RSP)

(345) 0x449b53 MOV	%R10,0x68(%RSP)

(345) 0x449b58 CMP	$0x6,%EDI

(345) 0x449b5b JBE	449f48

(345) 0x449b61 MOVSXD	0x7c(%RSP),%RAX

(345) 0x449b66 LEA	(%R11,%RAX,1),%R11

(345) 0x449b6a LEA	(%RSI,%RAX,1),%RDI

(345) 0x449b6e LEA	(%R13,%R11,8),%RSI

(345) 0x449b73 MOV	%EDX,%R11D

(345) 0x449b76 LEA	(%R8,%RAX,1),%RCX

(345) 0x449b7a SHR	$0x3,%R11D

(345) 0x449b7e ADD	%R10,%RAX

(345) 0x449b81 MOV	0x70(%RSP),%R10

(345) 0x449b86 SAL	$0x6,%R11

(345) 0x449b8a LEA	(%R15,%RCX,8),%R8

(345) 0x449b8e LEA	(%R10,%RAX,8),%RCX

(345) 0x449b92 LEA	-0x40(%R11),%R10

(345) 0x449b96 SHR	$0x6,%R10

(345) 0x449b9a INC	%R10

(345) 0x449b9d LEA	(%R14,%RDI,8),%RDI

(345) 0x449ba1 XOR	%EAX,%EAX

(345) 0x449ba3 AND	$0x7,%R10D

(345) 0x449ba7 JE	449cc3

(345) 0x449bad CMP	$0x1,%R10

(345) 0x449bb1 JE	449c9a

(345) 0x449bb7 CMP	$0x2,%R10

(345) 0x449bbb JE	449c7a

(345) 0x449bc1 CMP	$0x3,%R10

(345) 0x449bc5 JE	449c5a

(345) 0x449bcb CMP	$0x4,%R10

(345) 0x449bcf JE	449c3a

(345) 0x449bd1 CMP	$0x5,%R10

(345) 0x449bd5 JE	449c1a

(345) 0x449bd7 CMP	$0x6,%R10

(345) 0x449bdb JE	449bfa

(345) 0x449bdd VMOVUPD	(%R8),%ZMM0

(345) 0x449be3 MOV	$0x40,%EAX

(345) 0x449be8 VMOVUPD	%ZMM0,(%RDI)

(345) 0x449bee VMOVUPD	(%RSI),%ZMM1

(345) 0x449bf4 VMOVUPD	%ZMM1,(%RCX)

(345) 0x449bfa VMOVUPD	(%R8,%RAX,1),%ZMM2

(345) 0x449c01 VMOVUPD	%ZMM2,(%RDI,%RAX,1)

(345) 0x449c08 VMOVUPD	(%RSI,%RAX,1),%ZMM3

(345) 0x449c0f VMOVUPD	%ZMM3,(%RCX,%RAX,1)

(345) 0x449c16 ADD	$0x40,%RAX

(345) 0x449c1a VMOVUPD	(%R8,%RAX,1),%ZMM4

(345) 0x449c21 VMOVUPD	%ZMM4,(%RDI,%RAX,1)

(345) 0x449c28 VMOVUPD	(%RSI,%RAX,1),%ZMM5

(345) 0x449c2f VMOVUPD	%ZMM5,(%RCX,%RAX,1)

(345) 0x449c36 ADD	$0x40,%RAX

(345) 0x449c3a VMOVUPD	(%R8,%RAX,1),%ZMM6

(345) 0x449c41 VMOVUPD	%ZMM6,(%RDI,%RAX,1)

(345) 0x449c48 VMOVUPD	(%RSI,%RAX,1),%ZMM7

(345) 0x449c4f VMOVUPD	%ZMM7,(%RCX,%RAX,1)

(345) 0x449c56 ADD	$0x40,%RAX

(345) 0x449c5a VMOVUPD	(%R8,%RAX,1),%ZMM8

(345) 0x449c61 VMOVUPD	%ZMM8,(%RDI,%RAX,1)

(345) 0x449c68 VMOVUPD	(%RSI,%RAX,1),%ZMM9

(345) 0x449c6f VMOVUPD	%ZMM9,(%RCX,%RAX,1)

(345) 0x449c76 ADD	$0x40,%RAX

(345) 0x449c7a VMOVUPD	(%R8,%RAX,1),%ZMM10

(345) 0x449c81 VMOVUPD	%ZMM10,(%RDI,%RAX,1)

(345) 0x449c88 VMOVUPD	(%RSI,%RAX,1),%ZMM11

(345) 0x449c8f VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(345) 0x449c96 ADD	$0x40,%RAX

(345) 0x449c9a VMOVUPD	(%R8,%RAX,1),%ZMM12

(345) 0x449ca1 VMOVUPD	%ZMM12,(%RDI,%RAX,1)

(345) 0x449ca8 VMOVUPD	(%RSI,%RAX,1),%ZMM13

(345) 0x449caf VMOVUPD	%ZMM13,(%RCX,%RAX,1)

(345) 0x449cb6 ADD	$0x40,%RAX

(345) 0x449cba CMP	%R11,%RAX

(345) 0x449cbd JE	449dce

  (346) 0x449cc3 VMOVUPD	(%R8,%RAX,1),%ZMM14

  (346) 0x449cca VMOVUPD	%ZMM14,(%RDI,%RAX,1)

  (346) 0x449cd1 VMOVUPD	(%RSI,%RAX,1),%ZMM15

  (346) 0x449cd8 VMOVUPD	%ZMM15,(%RCX,%RAX,1)

  (346) 0x449cdf VMOVUPD	0x40(%R8,%RAX,1),%ZMM0

  (346) 0x449ce7 VMOVUPD	%ZMM0,0x40(%RDI,%RAX,1)

  (346) 0x449cef VMOVUPD	0x40(%RSI,%RAX,1),%ZMM1

  (346) 0x449cf7 VMOVUPD	%ZMM1,0x40(%RCX,%RAX,1)

  (346) 0x449cff VMOVUPD	0x80(%R8,%RAX,1),%ZMM2

  (346) 0x449d07 VMOVUPD	%ZMM2,0x80(%RDI,%RAX,1)

  (346) 0x449d0f VMOVUPD	0x80(%RSI,%RAX,1),%ZMM3

  (346) 0x449d17 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (346) 0x449d1f VMOVUPD	0xc0(%R8,%RAX,1),%ZMM4

  (346) 0x449d27 VMOVUPD	%ZMM4,0xc0(%RDI,%RAX,1)

  (346) 0x449d2f VMOVUPD	0xc0(%RSI,%RAX,1),%ZMM5

  (346) 0x449d37 VMOVUPD	%ZMM5,0xc0(%RCX,%RAX,1)

  (346) 0x449d3f VMOVUPD	0x100(%R8,%RAX,1),%ZMM6

  (346) 0x449d47 VMOVUPD	%ZMM6,0x100(%RDI,%RAX,1)

  (346) 0x449d4f VMOVUPD	0x100(%RSI,%RAX,1),%ZMM7

  (346) 0x449d57 VMOVUPD	%ZMM7,0x100(%RCX,%RAX,1)

  (346) 0x449d5f VMOVUPD	0x140(%R8,%RAX,1),%ZMM8

  (346) 0x449d67 VMOVUPD	%ZMM8,0x140(%RDI,%RAX,1)

  (346) 0x449d6f VMOVUPD	0x140(%RSI,%RAX,1),%ZMM9

  (346) 0x449d77 VMOVUPD	%ZMM9,0x140(%RCX,%RAX,1)

  (346) 0x449d7f VMOVUPD	0x180(%R8,%RAX,1),%ZMM10

  (346) 0x449d87 VMOVUPD	%ZMM10,0x180(%RDI,%RAX,1)

  (346) 0x449d8f VMOVUPD	0x180(%RSI,%RAX,1),%ZMM11

  (346) 0x449d97 VMOVUPD	%ZMM11,0x180(%RCX,%RAX,1)

  (346) 0x449d9f VMOVUPD	0x1c0(%R8,%RAX,1),%ZMM12

  (346) 0x449da7 VMOVUPD	%ZMM12,0x1c0(%RDI,%RAX,1)

  (346) 0x449daf VMOVUPD	0x1c0(%RSI,%RAX,1),%ZMM13

  (346) 0x449db7 VMOVUPD	%ZMM13,0x1c0(%RCX,%RAX,1)

  (346) 0x449dbf ADD	$0x200,%RAX

  (346) 0x449dc5 CMP	%R11,%RAX

  (346) 0x449dc8 JNE	449cc3

(345) 0x449dce MOV	0x7c(%RSP),%ESI

(345) 0x449dd2 MOV	%EDX,%R8D

(345) 0x449dd5 AND	$-0x8,%R8D

(345) 0x449dd9 ADD	%R8D,%ESI

(345) 0x449ddc ADD	%R8D,%R9D

(345) 0x449ddf TEST	$0x7,%DL

(345) 0x449de2 JE	449f03

(345) 0x449de8 SUB	%R8D,%EDX

(345) 0x449deb LEA	-0x1(%RDX),%EDI

(345) 0x449dee CMP	$0x2,%EDI

(345) 0x449df1 JBE	449e55

(345) 0x449df3 MOVSXD	0x7c(%RSP),%RCX

(345) 0x449df8 MOV	0x50(%RSP),%R11

(345) 0x449dfd MOV	0x58(%RSP),%R10

(345) 0x449e02 ADD	%RCX,%R11

(345) 0x449e05 ADD	%R8,%R11

(345) 0x449e08 MOV	0x60(%RSP),%RAX

(345) 0x449e0d ADD	%RCX,%R10

(345) 0x449e10 VMOVUPD	(%R15,%R11,8),%YMM14

(345) 0x449e16 MOV	0x68(%RSP),%RDI

(345) 0x449e1b ADD	%R8,%R10

(345) 0x449e1e ADD	%RCX,%RAX

(345) 0x449e21 ADD	%R8,%RAX

(345) 0x449e24 VMOVUPD	%YMM14,(%R14,%R10,8)

(345) 0x449e2a ADD	%RDI,%RCX

(345) 0x449e2d ADD	%R8,%RCX

(345) 0x449e30 VMOVUPD	(%R13,%RAX,8),%YMM15

(345) 0x449e37 MOV	0x70(%RSP),%R8

(345) 0x449e3c VMOVUPD	%YMM15,(%R8,%RCX,8)

(345) 0x449e42 MOV	%EDX,%ECX

(345) 0x449e44 AND	$-0x4,%ECX

(345) 0x449e47 ADD	%ECX,%ESI

(345) 0x449e49 ADD	%ECX,%R9D

(345) 0x449e4c AND	$0x3,%EDX

(345) 0x449e4f JE	449f03

(345) 0x449e55 MOV	0x50(%RSP),%RDI

(345) 0x449e5a MOVSXD	%ESI,%RAX

(345) 0x449e5d LEA	(%RDI,%RAX,1),%RDX

(345) 0x449e61 MOV	0x58(%RSP),%RCX

(345) 0x449e66 VMOVSD	(%R15,%RDX,8),%XMM0

(345) 0x449e6c MOV	0x60(%RSP),%R8

(345) 0x449e71 LEA	(%RCX,%RAX,1),%R11

(345) 0x449e75 VMOVSD	%XMM0,(%R14,%R11,8)

(345) 0x449e7b LEA	(%R8,%RAX,1),%R10

(345) 0x449e7f VMOVSD	(%R13,%R10,8),%XMM1

(345) 0x449e86 MOV	0x68(%RSP),%R10

(345) 0x449e8b MOV	0x70(%RSP),%R11

(345) 0x449e90 ADD	%R10,%RAX

(345) 0x449e93 VMOVSD	%XMM1,(%R11,%RAX,8)

(345) 0x449e99 LEA	0x1(%R9),%EAX

(345) 0x449e9d CMP	%R12D,%EAX

(345) 0x449ea0 JAE	449f03

(345) 0x449ea2 LEA	0x1(%RSI),%EAX

(345) 0x449ea5 CLTQ

(345) 0x449ea7 LEA	(%RDI,%RAX,1),%RDX

(345) 0x449eab VMOVSD	(%R15,%RDX,8),%XMM2

(345) 0x449eb1 LEA	(%RCX,%RAX,1),%RDX

(345) 0x449eb5 VMOVSD	%XMM2,(%R14,%RDX,8)

(345) 0x449ebb LEA	(%R8,%RAX,1),%RDX

(345) 0x449ebf VMOVSD	(%R13,%RDX,8),%XMM3

(345) 0x449ec6 ADD	%R10,%RAX

(345) 0x449ec9 ADD	$0x2,%R9D

(345) 0x449ecd VMOVSD	%XMM3,(%R11,%RAX,8)

(345) 0x449ed3 CMP	%R12D,%R9D

(345) 0x449ed6 JAE	449f03

(345) 0x449ed8 ADD	$0x2,%ESI

(345) 0x449edb MOVSXD	%ESI,%R9

(345) 0x449ede ADD	%R9,%RDI

(345) 0x449ee1 VMOVSD	(%R15,%RDI,8),%XMM4

(345) 0x449ee7 ADD	%R9,%RCX

(345) 0x449eea VMOVSD	%XMM4,(%R14,%RCX,8)

(345) 0x449ef0 ADD	%R9,%R8

(345) 0x449ef3 VMOVSD	(%R13,%R8,8),%XMM5

(345) 0x449efa ADD	%R9,%R10

(345) 0x449efd VMOVSD	%XMM5,(%R11,%R10,8)

(345) 0x449f03 MOV	%R12D,%R9D

(345) 0x449f06 INC	%RBX

(345) 0x449f09 CMP	%EBX,0x4c(%RSP)

(345) 0x449f0d JLE	449f30

(345) 0x449f0f MOV	0x44(%RSP),%R13D

(345) 0x449f14 MOV	0x48(%RSP),%R12D

(345) 0x449f19 MOV	0x78(%RSP),%EDX

(345) 0x449f1d MOV	%R12D,0x7c(%RSP)

(345) 0x449f22 SUB	%R9D,%R13D

(345) 0x449f25 JMP	449ae8

0x449f2a NOPW	(%RAX,%RAX,1)

0x449f30 VZEROUPPER

0x449f33 LEA	-0x28(%RBP),%RSP

0x449f37 POP	%RBX

0x449f38 POP	%R12

0x449f3a POP	%R13

0x449f3c POP	%R14

0x449f3e POP	%R15

0x449f40 POP	%RBP

0x449f41 RET

0x449f42 NOPW	(%RAX,%RAX,1)

(345) 0x449f48 MOV	0x7c(%RSP),%ESI

(345) 0x449f4c XOR	%R8D,%R8D

(345) 0x449f4f JMP	449de8

0x449f54 INC	%R13D

0x449f57 XOR	%EDX,%EDX

0x449f59 JMP	449a82

0x449f5e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 449a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 449f54 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 449a82 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 13.83 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	80
nb uops	90
loop length	274
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.00
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	20%

Vector efficiency ratios

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 449a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RBX),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 449f54 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x554>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 449f33 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x48(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 449a82 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.70	0.78
▼Loop 345 - reset_field.cpp:46-48 - exec–	0.00	0.01
○Loop 346 - reset_field.cpp:47-48 - exec	2.69	0.77

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Vectorization

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code