OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 5.13% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

0x447b10 PUSH	%RBP

0x447b11 MOV	%RSP,%RBP

0x447b14 PUSH	%R15

0x447b16 PUSH	%R14

0x447b18 PUSH	%R13

0x447b1a PUSH	%R12

0x447b1c PUSH	%RBX

0x447b1d MOV	%RDI,%RBX

0x447b20 AND	$-0x40,%RSP

0x447b24 SUB	$0x1c0,%RSP

0x447b2b MOV	0x68(%RDI),%EAX

0x447b2e MOV	0x6c(%RDI),%EDX

0x447b31 MOV	0x60(%RDI),%EDI

0x447b34 ADD	$0x2,%EDX

0x447b37 LEA	0x1(%RDI),%ESI

0x447b3a LEA	0x1(%RAX),%R12D

0x447b3e MOV	%EDX,0x98(%RSP)

0x447b45 MOV	%ESI,0x94(%RSP)

0x447b4c MOV	0x64(%RBX),%ECX

0x447b4f CMP	%EDX,%R12D

0x447b52 JGE	448653

0x447b58 MOV	%EDX,%R14D

0x447b5b LEA	0x2(%RCX),%R15D

0x447b5f SUB	%R12D,%R14D

0x447b62 CMP	%R15D,%ESI

0x447b65 JGE	448653

0x447b6b MOV	%R15D,%R8D

0x447b6e SUB	%ESI,%R8D

0x447b71 MOV	%R8D,0x9c(%RSP)

0x447b79 CALL	404630 <omp_get_num_threads@plt>

0x447b7e MOV	%EAX,%R13D

0x447b81 CALL	404520 <omp_get_thread_num@plt>

0x447b86 MOV	%EAX,%R9D

0x447b89 MOV	0x9c(%RSP),%EAX

0x447b90 XOR	%EDX,%EDX

0x447b92 IMUL	%R14D,%EAX

0x447b96 DIV	%R13D

0x447b99 MOV	%EAX,%ECX

0x447b9b CMP	%EDX,%R9D

0x447b9e JB	44867f

0x447ba4 IMUL	%ECX,%R9D

0x447ba8 LEA	(%R9,%RDX,1),%EAX

0x447bac LEA	(%RCX,%RAX,1),%R10D

0x447bb0 MOV	%EAX,0x17c(%RSP)

0x447bb7 MOV	%R10D,0x90(%RSP)

0x447bbf CMP	%R10D,%EAX

0x447bc2 JAE	448653

0x447bc8 XOR	%EDX,%EDX

0x447bca DIVL	0x9c(%RSP)

0x447bd1 MOV	0x94(%RSP),%R11D

0x447bd9 VMOVSD	0x27ddf(%RIP),%XMM1

0x447be1 MOV	0x8(%RBX),%RSI

0x447be5 MOV	0x10(%RBX),%R14

0x447be9 MOV	0x58(%RBX),%R8

0x447bed MOV	0x18(%RBX),%R13

0x447bf1 MOV	0x40(%RBX),%R9

0x447bf5 MOV	0x20(%RBX),%R10

0x447bf9 VMULSD	(%RBX),%XMM1,%XMM1

0x447bfd MOV	%RSI,0x88(%RSP)

0x447c05 MOV	0x38(%RBX),%RSI

0x447c09 VMOVSD	0x278c7(%RIP),%XMM6

0x447c11 MOV	%R14,0x78(%RSP)

0x447c16 MOV	%R8,0x70(%RSP)

0x447c1b MOV	%R13,0x68(%RSP)

0x447c20 MOV	%R9,0x60(%RSP)

0x447c25 MOV	%R10,0x58(%RSP)

0x447c2a MOV	%RSI,0x40(%RSP)

0x447c2f VBROADCASTSD	%XMM1,%YMM2

0x447c34 VBROADCASTSD	%XMM6,%YMM7

0x447c39 VBROADCASTSD	%XMM1,%ZMM5

0x447c3f VBROADCASTSD	%XMM6,%ZMM4

0x447c45 LEA	(%RDX,%R11,1),%EDI

0x447c49 MOV	%R15D,%EDX

0x447c4c MOV	0x48(%RBX),%R11

0x447c50 MOV	0x50(%RBX),%R15

0x447c54 MOV	%EDI,0x158(%RSP)

0x447c5b SUB	%EDI,%EDX

0x447c5d ADD	%R12D,%EAX

0x447c60 MOV	0x30(%RBX),%RDI

0x447c64 MOV	0x28(%RBX),%RBX

0x447c68 CLTQ

0x447c6a MOV	%R15,0x80(%RSP)

0x447c72 MOV	%R11,0x50(%RSP)

0x447c77 MOV	%RDI,0x48(%RSP)

0x447c7c MOV	%RBX,0x38(%RSP)

0x447c81 MOV	%RAX,0x160(%RSP)

0x447c89 NOPL	(%RAX)

(336) 0x447c90 CMP	%EDX,%ECX

(336) 0x447c92 CMOVBE	%ECX,%EDX

(336) 0x447c95 MOV	0x17c(%RSP),%R12D

(336) 0x447c9d MOV	%EDX,0x178(%RSP)

(336) 0x447ca4 LEA	(%R12,%RDX,1),%ECX

(336) 0x447ca8 MOV	%ECX,0x15c(%RSP)

(336) 0x447caf CMP	%ECX,%R12D

(336) 0x447cb2 JAE	448603

(336) 0x447cb8 MOV	0x80(%RSP),%RDX

(336) 0x447cc0 MOV	0x160(%RSP),%RDI

(336) 0x447cc8 MOV	(%RDX),%R15

(336) 0x447ccb MOV	0x70(%RSP),%R10

(336) 0x447cd0 MOV	0x88(%RSP),%RAX

(336) 0x447cd8 MOV	%RDI,%RCX

(336) 0x447cdb MOV	0x10(%R10),%R11

(336) 0x447cdf IMUL	%R15,%RCX

(336) 0x447ce3 MOV	0x10(%RAX),%R12

(336) 0x447ce7 MOV	(%RAX),%RSI

(336) 0x447cea MOV	(%R10),%RAX

(336) 0x447ced MOV	0x78(%RSP),%R14

(336) 0x447cf2 MOV	%R11,0x170(%RSP)

(336) 0x447cfa MOV	%RDI,%R11

(336) 0x447cfd IMUL	%RAX,%R11

(336) 0x447d01 ADD	%RCX,%R15

(336) 0x447d04 MOV	(%R14),%R9

(336) 0x447d07 MOV	%R15,0xd0(%RSP)

(336) 0x447d0f MOV	0x68(%RSP),%R15

(336) 0x447d14 MOV	%RDI,%RBX

(336) 0x447d17 MOV	0x10(%R14),%R8

(336) 0x447d1b MOV	0x10(%RDX),%R13

(336) 0x447d1f MOV	0x10(%R15),%R14

(336) 0x447d23 LEA	(%RAX,%R11,1),%RDX

(336) 0x447d27 IMUL	%RDI,%RSI

(336) 0x447d2b MOV	%RDI,%RAX

(336) 0x447d2e IMUL	%R9,%RBX

(336) 0x447d32 IMUL	(%R15),%RDI

(336) 0x447d36 MOV	0x60(%RSP),%R15

(336) 0x447d3b MOV	%R8,0xd8(%RSP)

(336) 0x447d43 MOV	0x10(%R15),%R8

(336) 0x447d47 ADD	%RBX,%R9

(336) 0x447d4a MOV	%RDX,0xe8(%RSP)

(336) 0x447d52 MOV	%R14,0xf0(%RSP)

(336) 0x447d5a MOV	%R8,0x100(%RSP)

(336) 0x447d62 MOV	%R12,0xa8(%RSP)

(336) 0x447d6a MOV	%RSI,0xa0(%RSP)

(336) 0x447d72 MOV	%R13,0x168(%RSP)

(336) 0x447d7a MOV	%RCX,0xb0(%RSP)

(336) 0x447d82 MOV	%RBX,0xb8(%RSP)

(336) 0x447d8a MOV	%R11,0xc0(%RSP)

(336) 0x447d92 MOV	%R9,0xe0(%RSP)

(336) 0x447d9a MOV	%RDI,0xc8(%RSP)

(336) 0x447da2 MOV	(%R15),%R9

(336) 0x447da5 MOV	0x58(%RSP),%R10

(336) 0x447daa MOV	0x50(%RSP),%R15

(336) 0x447daf MOV	(%R10),%R8

(336) 0x447db2 MOV	0x10(%R10),%RDX

(336) 0x447db6 IMUL	%RAX,%R8

(336) 0x447dba MOV	%RDX,0x110(%RSP)

(336) 0x447dc2 MOV	0x48(%RSP),%RDX

(336) 0x447dc7 IMUL	%RAX,%R9

(336) 0x447dcb MOV	(%R15),%R10

(336) 0x447dce MOV	%R8,0x108(%RSP)

(336) 0x447dd6 MOV	(%RDX),%R8

(336) 0x447dd9 MOV	0x10(%RDX),%R14

(336) 0x447ddd IMUL	%RAX,%R10

(336) 0x447de1 IMUL	%RAX,%R8

(336) 0x447de5 MOV	%R9,0xf8(%RSP)

(336) 0x447ded MOV	%R14,0x140(%RSP)

(336) 0x447df5 MOV	0x10(%R15),%R9

(336) 0x447df9 MOV	0x38(%RSP),%R14

(336) 0x447dfe MOV	0x40(%RSP),%R15

(336) 0x447e03 MOV	%R10,0x118(%RSP)

(336) 0x447e0b MOV	%R8,0x148(%RSP)

(336) 0x447e13 MOV	(%R15),%R10

(336) 0x447e16 MOV	(%R14),%R8

(336) 0x447e19 IMUL	%RAX,%R10

(336) 0x447e1d IMUL	%RAX,%R8

(336) 0x447e21 MOV	0x178(%RSP),%EAX

(336) 0x447e28 MOV	%R9,0x150(%RSP)

(336) 0x447e30 MOV	0x10(%R14),%RDX

(336) 0x447e34 MOV	0x10(%R15),%R9

(336) 0x447e38 LEA	-0x1(%RAX),%R15D

(336) 0x447e3c MOV	%R9,0x130(%RSP)

(336) 0x447e44 MOV	%R10,0x138(%RSP)

(336) 0x447e4c MOV	%RDX,0x120(%RSP)

(336) 0x447e54 MOV	%R8,0x128(%RSP)

(336) 0x447e5c CMP	$0x6,%R15D

(336) 0x447e60 JBE	448668

(336) 0x447e66 MOVSXD	0x158(%RSP),%RAX

(336) 0x447e6e MOV	%R13,%R10

(336) 0x447e71 ADD	%RAX,%RCX

(336) 0x447e74 SAL	$0x3,%RCX

(336) 0x447e78 LEA	(%R13,%RCX,1),%R14

(336) 0x447e7d MOV	0xd0(%RSP),%R13

(336) 0x447e85 ADD	%RAX,%RSI

(336) 0x447e88 LEA	(%R13,%RAX,1),%RDX

(336) 0x447e8d SAL	$0x3,%RSI

(336) 0x447e91 SAL	$0x3,%RDX

(336) 0x447e95 MOV	%R12,%R9

(336) 0x447e98 LEA	(%R12,%RSI,1),%R15

(336) 0x447e9c LEA	(%R10,%RDX,1),%R12

(336) 0x447ea0 MOV	%R12,0x188(%RSP)

(336) 0x447ea8 LEA	0x8(%R10,%RCX,1),%R12

(336) 0x447ead LEA	0x8(%R10,%RDX,1),%RCX

(336) 0x447eb2 MOV	0xd8(%RSP),%R8

(336) 0x447eba MOV	%RCX,0x190(%RSP)

(336) 0x447ec2 MOV	0xe0(%RSP),%RCX

(336) 0x447eca LEA	(%RBX,%RAX,1),%R10

(336) 0x447ece LEA	(%R8,%R10,8),%RBX

(336) 0x447ed2 LEA	(%RCX,%RAX,1),%R10

(336) 0x447ed6 LEA	(%R11,%RAX,1),%RDX

(336) 0x447eda LEA	0x8(%R9,%RSI,1),%R13

(336) 0x447edf LEA	(%R8,%R10,8),%R10

(336) 0x447ee3 MOV	0x170(%RSP),%RSI

(336) 0x447eeb MOV	0xe8(%RSP),%R8

(336) 0x447ef3 SAL	$0x3,%RDX

(336) 0x447ef7 LEA	0x8(%RSI,%RDX,1),%R9

(336) 0x447efc LEA	(%RSI,%RDX,1),%R11

(336) 0x447f00 LEA	(%R8,%RAX,1),%RDX

(336) 0x447f04 SAL	$0x3,%RDX

(336) 0x447f08 LEA	(%RDI,%RAX,1),%RCX

(336) 0x447f0c MOV	%R9,0x198(%RSP)

(336) 0x447f14 MOV	0xf0(%RSP),%RDI

(336) 0x447f1c LEA	(%RSI,%RDX,1),%R9

(336) 0x447f20 LEA	0x8(%RSI,%RDX,1),%RSI

(336) 0x447f25 MOV	0xf8(%RSP),%RDX

(336) 0x447f2d MOV	%RSI,0x1a0(%RSP)

(336) 0x447f35 MOV	0x100(%RSP),%RSI

(336) 0x447f3d ADD	%RAX,%RDX

(336) 0x447f40 LEA	(%RDI,%RCX,8),%R8

(336) 0x447f44 MOV	0x108(%RSP),%RCX

(336) 0x447f4c LEA	(%RSI,%RDX,8),%RDI

(336) 0x447f50 MOV	0x110(%RSP),%RSI

(336) 0x447f58 LEA	(%RCX,%RAX,1),%RDX

(336) 0x447f5c MOV	0x118(%RSP),%RCX

(336) 0x447f64 LEA	(%RSI,%RDX,8),%RDX

(336) 0x447f68 MOV	0x150(%RSP),%RSI

(336) 0x447f70 LEA	(%RCX,%RAX,1),%RCX

(336) 0x447f74 LEA	(%RSI,%RCX,8),%RCX

(336) 0x447f78 MOV	0x148(%RSP),%RSI

(336) 0x447f80 MOV	%RCX,0x1a8(%RSP)

(336) 0x447f88 LEA	(%RSI,%RAX,1),%RCX

(336) 0x447f8c MOV	0x140(%RSP),%RSI

(336) 0x447f94 LEA	(%RSI,%RCX,8),%RCX

(336) 0x447f98 MOV	0x138(%RSP),%RSI

(336) 0x447fa0 MOV	%RCX,0x1b0(%RSP)

(336) 0x447fa8 LEA	(%RSI,%RAX,1),%RCX

(336) 0x447fac MOV	0x130(%RSP),%RSI

(336) 0x447fb4 LEA	(%RSI,%RCX,8),%RCX

(336) 0x447fb8 MOV	0x128(%RSP),%RSI

(336) 0x447fc0 MOV	%RCX,0x1b8(%RSP)

(336) 0x447fc8 MOV	0x120(%RSP),%RCX

(336) 0x447fd0 ADD	%RSI,%RAX

(336) 0x447fd3 LEA	(%RCX,%RAX,8),%RSI

(336) 0x447fd7 MOV	0x178(%RSP),%ECX

(336) 0x447fde XOR	%EAX,%EAX

(336) 0x447fe0 SHR	$0x3,%ECX

(336) 0x447fe3 SAL	$0x6,%RCX

(336) 0x447fe7 MOV	%RCX,0x180(%RSP)

(336) 0x447fef NOP

  (338) 0x447ff0 VMOVUPD	(%R14,%RAX,1),%ZMM8

  (338) 0x447ff7 MOV	0x188(%RSP),%RCX

  (338) 0x447fff VMOVUPD	(%R11,%RAX,1),%ZMM3

  (338) 0x448006 VADDPD	(%RCX,%RAX,1),%ZMM8,%ZMM10

  (338) 0x44800d MOV	0x198(%RSP),%RCX

  (338) 0x448015 VMOVUPD	(%RBX,%RAX,1),%ZMM0

  (338) 0x44801c VADDPD	(%RCX,%RAX,1),%ZMM3,%ZMM9

  (338) 0x448023 VMOVUPD	(%R12,%RAX,1),%ZMM14

  (338) 0x44802a MOV	0x190(%RSP),%RCX

  (338) 0x448032 VADDPD	%ZMM0,%ZMM0,%ZMM11

  (338) 0x448038 VADDPD	(%RCX,%RAX,1),%ZMM14,%ZMM8

  (338) 0x44803f VMOVUPD	(%R9,%RAX,1),%ZMM3

  (338) 0x448046 VMOVUPD	(%R10,%RAX,1),%ZMM0

  (338) 0x44804d MOV	0x1a0(%RSP),%RCX

  (338) 0x448055 VMULPD	%ZMM11,%ZMM9,%ZMM13

  (338) 0x44805b VADDPD	(%RCX,%RAX,1),%ZMM3,%ZMM9

  (338) 0x448062 VADDPD	%ZMM0,%ZMM0,%ZMM11

  (338) 0x448068 VMOVUPD	(%R13,%RAX,1),%ZMM12

  (338) 0x448070 VMOVUPD	(%R15,%RAX,1),%ZMM14

  (338) 0x448077 VADDPD	%ZMM12,%ZMM12,%ZMM15

  (338) 0x44807d VMULPD	%ZMM11,%ZMM9,%ZMM12

  (338) 0x448083 VMOVUPD	(%RDI,%RAX,1),%ZMM0

  (338) 0x44808a MOV	0x1a8(%RSP),%RCX

  (338) 0x448092 VMOVUPD	(%R8,%RAX,1),%ZMM3

  (338) 0x448099 VADDPD	(%RCX,%RAX,1),%ZMM0,%ZMM11

  (338) 0x4480a0 VFMADD132PD	%ZMM8,%ZMM12,%ZMM15

  (338) 0x4480a6 VADDPD	%ZMM14,%ZMM14,%ZMM8

  (338) 0x4480ac VDIVPD	(%RDX,%RAX,1),%ZMM11,%ZMM12

  (338) 0x4480b3 VDIVPD	%ZMM3,%ZMM4,%ZMM14

  (338) 0x4480b9 VFMADD132PD	%ZMM10,%ZMM13,%ZMM8

  (338) 0x4480bf MOV	0x1b0(%RSP),%RCX

  (338) 0x4480c7 VSUBPD	%ZMM8,%ZMM15,%ZMM10

  (338) 0x4480cd VMULPD	%ZMM14,%ZMM12,%ZMM8

  (338) 0x4480d3 VMULPD	%ZMM5,%ZMM10,%ZMM9

  (338) 0x4480d9 VADDPD	%ZMM9,%ZMM3,%ZMM13

  (338) 0x4480df VFNMADD213PD	(%RCX,%RAX,1),%ZMM8,%ZMM9

  (338) 0x4480e6 MOV	0x1b8(%RSP),%RCX

  (338) 0x4480ee VDIVPD	%ZMM13,%ZMM3,%ZMM15

  (338) 0x4480f4 VMOVUPD	%ZMM9,(%RCX,%RAX,1)

  (338) 0x4480fb VMULPD	(%RDX,%RAX,1),%ZMM15,%ZMM10

  (338) 0x448102 MOV	0x180(%RSP),%RCX

  (338) 0x44810a VMOVUPD	%ZMM10,(%RSI,%RAX,1)

  (338) 0x448111 ADD	$0x40,%RAX

  (338) 0x448115 CMP	%RCX,%RAX

  (338) 0x448118 JNE	447ff0

(336) 0x44811e MOV	0x178(%RSP),%R15D

(336) 0x448126 MOV	0x158(%RSP),%R14D

(336) 0x44812e MOV	%R15D,%EAX

(336) 0x448131 AND	$-0x8,%EAX

(336) 0x448134 ADD	%EAX,%R14D

(336) 0x448137 ADD	%EAX,0x17c(%RSP)

(336) 0x44813e AND	$0x7,%R15D

(336) 0x448142 MOV	%R14D,0x1b8(%RSP)

(336) 0x44814a JE	4485f3

(336) 0x448150 MOV	0x178(%RSP),%R14D

(336) 0x448158 SUB	%EAX,%R14D

(336) 0x44815b LEA	-0x1(%R14),%R13D

(336) 0x44815f CMP	$0x2,%R13D

(336) 0x448163 JBE	4483c0

(336) 0x448169 MOVSXD	0x158(%RSP),%RDX

(336) 0x448171 MOV	0xa0(%RSP),%R12

(336) 0x448179 MOV	0xb0(%RSP),%RBX

(336) 0x448181 MOV	0xc0(%RSP),%R10

(336) 0x448189 LEA	(%R12,%RDX,1),%RCX

(336) 0x44818d MOV	0xf8(%RSP),%R12

(336) 0x448195 MOV	0xd0(%RSP),%R11

(336) 0x44819d MOV	0xc8(%RSP),%R15

(336) 0x4481a5 LEA	(%RBX,%RDX,1),%RDI

(336) 0x4481a9 LEA	(%R10,%RDX,1),%R9

(336) 0x4481ad LEA	(%R12,%RDX,1),%RBX

(336) 0x4481b1 MOV	0x108(%RSP),%R10

(336) 0x4481b9 LEA	(%R11,%RDX,1),%R8

(336) 0x4481bd LEA	(%R15,%RDX,1),%R13

(336) 0x4481c1 LEA	(%RBX,%RAX,1),%R11

(336) 0x4481c5 MOV	0x148(%RSP),%RBX

(336) 0x4481cd LEA	(%R13,%RAX,1),%R15

(336) 0x4481d2 MOV	0x110(%RSP),%R12

(336) 0x4481da LEA	(%R10,%RDX,1),%R13

(336) 0x4481de MOV	0x138(%RSP),%R10

(336) 0x4481e6 ADD	%RAX,%R13

(336) 0x4481e9 ADD	%RDX,%RBX

(336) 0x4481ec LEA	(%R12,%R13,8),%R12

(336) 0x4481f0 ADD	%RAX,%RBX

(336) 0x4481f3 LEA	(%R10,%RDX,1),%R13

(336) 0x4481f7 MOV	%RBX,0x1a8(%RSP)

(336) 0x4481ff LEA	(%R13,%RAX,1),%RBX

(336) 0x448204 MOV	0x128(%RSP),%R10

(336) 0x44820c MOV	%RBX,0x1a0(%RSP)

(336) 0x448214 MOV	0x168(%RSP),%RBX

(336) 0x44821c ADD	%RAX,%R8

(336) 0x44821f VMOVUPD	(%RBX,%R8,8),%YMM9

(336) 0x448225 LEA	(%R10,%RDX,1),%R13

(336) 0x448229 MOV	0xb8(%RSP),%R10

(336) 0x448231 ADD	%RAX,%RDI

(336) 0x448234 VADDPD	(%RBX,%RDI,8),%YMM9,%YMM13

(336) 0x448239 LEA	(%R10,%RDX,1),%RBX

(336) 0x44823d MOV	0xd8(%RSP),%R10

(336) 0x448245 ADD	%RAX,%RBX

(336) 0x448248 VMOVUPD	(%R10,%RBX,8),%YMM3

(336) 0x44824e MOV	0x170(%RSP),%RBX

(336) 0x448256 ADD	%RAX,%R9

(336) 0x448259 VMOVUPD	(%RBX,%R9,8),%YMM0

(336) 0x44825f MOV	%R11,0x1b0(%RSP)

(336) 0x448267 VADDPD	0x8(%RBX,%R9,8),%YMM0,%YMM11

(336) 0x44826e MOV	0x168(%RSP),%RBX

(336) 0x448276 MOV	0xe8(%RSP),%RSI

(336) 0x44827e VMOVUPD	0x8(%RBX,%R8,8),%YMM10

(336) 0x448285 MOV	0x118(%RSP),%R11

(336) 0x44828d VADDPD	0x8(%RBX,%RDI,8),%YMM10,%YMM9

(336) 0x448293 MOV	0xe0(%RSP),%RDI

(336) 0x44829b MOV	0xa8(%RSP),%R9

(336) 0x4482a3 ADD	%RDX,%R11

(336) 0x4482a6 LEA	(%RSI,%RDX,1),%RSI

(336) 0x4482aa ADD	%RDI,%RDX

(336) 0x4482ad ADD	%RAX,%RCX

(336) 0x4482b0 ADD	%RAX,%RDX

(336) 0x4482b3 VMOVUPD	0x8(%R9,%RCX,8),%YMM14

(336) 0x4482ba ADD	%RAX,%RSI

(336) 0x4482bd ADD	%RAX,%R11

(336) 0x4482c0 VADDPD	%YMM3,%YMM3,%YMM15

(336) 0x4482c4 LEA	(%R13,%RAX,1),%R13

(336) 0x4482c9 VMOVUPD	(%R10,%RDX,8),%YMM3

(336) 0x4482cf MOV	0x170(%RSP),%RAX

(336) 0x4482d7 VMULPD	%YMM11,%YMM15,%YMM12

(336) 0x4482dc VMOVUPD	(%RAX,%RSI,8),%YMM0

(336) 0x4482e1 VADDPD	%YMM3,%YMM3,%YMM15

(336) 0x4482e5 VADDPD	0x8(%RAX,%RSI,8),%YMM0,%YMM11

(336) 0x4482eb VADDPD	%YMM14,%YMM14,%YMM8

(336) 0x4482f0 VMOVUPD	(%R9,%RCX,8),%YMM10

(336) 0x4482f6 VMULPD	%YMM11,%YMM15,%YMM14

(336) 0x4482fb MOV	0xf0(%RSP),%RDX

(336) 0x448303 MOV	0x150(%RSP),%RCX

(336) 0x44830b VMOVUPD	(%RDX,%R15,8),%YMM15

(336) 0x448311 VMOVUPD	(%RCX,%R11,8),%YMM3

(336) 0x448317 VFMADD132PD	%YMM9,%YMM14,%YMM8

(336) 0x44831c VADDPD	%YMM10,%YMM10,%YMM9

(336) 0x448321 VDIVPD	%YMM15,%YMM7,%YMM10

(336) 0x448326 MOV	0x100(%RSP),%R8

(336) 0x44832e VFMADD132PD	%YMM13,%YMM12,%YMM9

(336) 0x448333 MOV	0x1b0(%RSP),%RSI

(336) 0x44833b MOV	0x140(%RSP),%R15

(336) 0x448343 VADDPD	(%R8,%RSI,8),%YMM3,%YMM11

(336) 0x448349 MOV	0x1a8(%RSP),%R11

(336) 0x448351 VSUBPD	%YMM9,%YMM8,%YMM13

(336) 0x448356 VDIVPD	(%R12),%YMM11,%YMM14

(336) 0x44835c MOV	0x130(%RSP),%R10

(336) 0x448364 VMULPD	%YMM2,%YMM13,%YMM12

(336) 0x448368 MOV	0x1a0(%RSP),%R9

(336) 0x448370 VADDPD	%YMM15,%YMM12,%YMM8

(336) 0x448375 VDIVPD	%YMM8,%YMM15,%YMM0

(336) 0x44837a VMULPD	%YMM10,%YMM14,%YMM9

(336) 0x44837f VFNMADD213PD	(%R15,%R11,8),%YMM9,%YMM12

(336) 0x448385 VMOVUPD	%YMM12,(%R10,%R9,8)

(336) 0x44838b VMULPD	(%R12),%YMM0,%YMM13

(336) 0x448391 MOV	0x120(%RSP),%R12

(336) 0x448399 VMOVUPD	%YMM13,(%R12,%R13,8)

(336) 0x44839f MOV	%R14D,%R13D

(336) 0x4483a2 AND	$-0x4,%R13D

(336) 0x4483a6 ADD	%R13D,0x1b8(%RSP)

(336) 0x4483ae ADD	%R13D,0x17c(%RSP)

(336) 0x4483b6 AND	$0x3,%R14D

(336) 0x4483ba JE	4485f3

(336) 0x4483c0 MOVSXD	0x1b8(%RSP),%R14

(336) 0x4483c8 MOV	0xa8(%RSP),%RBX

(336) 0x4483d0 MOV	0xa0(%RSP),%RDI

(336) 0x4483d8 MOV	0x168(%RSP),%RDX

(336) 0x4483e0 MOV	0xd8(%RSP),%R11

(336) 0x4483e8 MOV	0x170(%RSP),%R12

(336) 0x4483f0 MOV	%R14,0x1a0(%RSP)

(336) 0x4483f8 MOV	0xb0(%RSP),%RAX

(336) 0x448400 MOV	0xd0(%RSP),%RCX

(336) 0x448408 MOV	0xb8(%RSP),%RSI

(336) 0x448410 MOV	0xc0(%RSP),%R13

(336) 0x448418 MOV	%R14,%R10

(336) 0x44841b LEA	(%RBX,%RDI,8),%R9

(336) 0x44841f MOV	0xe0(%RSP),%R14

(336) 0x448427 MOV	0xe8(%RSP),%RBX

(336) 0x44842f LEA	(%RDX,%RAX,8),%R8

(336) 0x448433 LEA	(%RDX,%RCX,8),%RDI

(336) 0x448437 MOV	0xc8(%RSP),%RAX

(336) 0x44843f MOV	0xf0(%RSP),%RDX

(336) 0x448447 LEA	(%R11,%RSI,8),%R15

(336) 0x44844b LEA	(%R12,%RBX,8),%RCX

(336) 0x44844f LEA	(%R12,%R13,8),%RSI

(336) 0x448453 LEA	(%R11,%R14,8),%R14

(336) 0x448457 MOV	0xf8(%RSP),%R12

(336) 0x44845f MOV	0x100(%RSP),%R11

(336) 0x448467 MOV	0x108(%RSP),%RBX

(336) 0x44846f LEA	(%RDX,%RAX,8),%R13

(336) 0x448473 LEA	(%R11,%R12,8),%R12

(336) 0x448477 MOV	0x150(%RSP),%RAX

(336) 0x44847f MOV	0x118(%RSP),%R11

(336) 0x448487 MOV	0x110(%RSP),%RDX

(336) 0x44848f LEA	(%RDX,%RBX,8),%RDX

(336) 0x448493 LEA	(%RAX,%R11,8),%RBX

(336) 0x448497 MOV	0x140(%RSP),%RAX

(336) 0x44849f MOV	0x148(%RSP),%R11

(336) 0x4484a7 MOV	%RBX,0x1b8(%RSP)

(336) 0x4484af LEA	(%RAX,%R11,8),%RBX

(336) 0x4484b3 MOV	0x130(%RSP),%RAX

(336) 0x4484bb MOV	0x138(%RSP),%R11

(336) 0x4484c3 MOV	%RBX,0x1b0(%RSP)

(336) 0x4484cb LEA	(%RAX,%R11,8),%RBX

(336) 0x4484cf MOV	0x120(%RSP),%RAX

(336) 0x4484d7 MOV	0x128(%RSP),%R11

(336) 0x4484df LEA	(%RAX,%R11,8),%R11

(336) 0x4484e3 MOV	0x17c(%RSP),%EAX

(336) 0x4484ea SUB	%R10D,%EAX

(336) 0x4484ed MOV	%EAX,0x1a8(%RSP)

(336) 0x4484f4 MOV	0x1a0(%RSP),%RAX

(336) 0x4484fc MOV	%R11,0x1a0(%RSP)

  (337) 0x448504 VMOVSD	0x8(%RSI,%RAX,8),%XMM8

  (337) 0x44850a VMOVSD	(%R15,%RAX,8),%XMM3

  (337) 0x448510 VADDSD	(%RSI,%RAX,8),%XMM8,%XMM0

  (337) 0x448515 VADDSD	%XMM3,%XMM3,%XMM11

  (337) 0x448519 VMOVSD	(%RCX,%RAX,8),%XMM8

  (337) 0x44851e VMOVSD	(%R14,%RAX,8),%XMM3

  (337) 0x448524 VMULSD	%XMM11,%XMM0,%XMM14

  (337) 0x448529 VADDSD	0x8(%RCX,%RAX,8),%XMM8,%XMM0

  (337) 0x44852f VADDSD	%XMM3,%XMM3,%XMM11

  (337) 0x448533 VMOVSD	0x8(%RDI,%RAX,8),%XMM10

  (337) 0x448539 VMOVSD	(%RDI,%RAX,8),%XMM12

  (337) 0x44853e VADDSD	0x8(%R8,%RAX,8),%XMM10,%XMM9

  (337) 0x448545 VMOVSD	0x8(%R9,%RAX,8),%XMM13

  (337) 0x44854c VMULSD	%XMM11,%XMM0,%XMM10

  (337) 0x448551 VADDSD	(%R8,%RAX,8),%XMM12,%XMM15

  (337) 0x448557 VADDSD	%XMM13,%XMM13,%XMM12

  (337) 0x44855c VMOVSD	(%R9,%RAX,8),%XMM13

  (337) 0x448562 VMOVSD	(%R12,%RAX,8),%XMM3

  (337) 0x448568 VFMADD132SD	%XMM12,%XMM10,%XMM9

  (337) 0x44856d VADDSD	%XMM13,%XMM13,%XMM12

  (337) 0x448572 MOV	0x1b8(%RSP),%R10

  (337) 0x44857a MOV	0x1b0(%RSP),%R11

  (337) 0x448582 VFMADD132SD	%XMM12,%XMM14,%XMM15

  (337) 0x448587 VADDSD	(%R10,%RAX,8),%XMM3,%XMM11

  (337) 0x44858d MOV	0x1a0(%RSP),%R10

  (337) 0x448595 VDIVSD	(%RDX,%RAX,8),%XMM11,%XMM10

  (337) 0x44859a VSUBSD	%XMM15,%XMM9,%XMM15

  (337) 0x44859f VMOVSD	(%R13,%RAX,8),%XMM9

  (337) 0x4485a6 VDIVSD	%XMM9,%XMM6,%XMM13

  (337) 0x4485ab VMULSD	%XMM1,%XMM15,%XMM14

  (337) 0x4485af VADDSD	%XMM9,%XMM14,%XMM8

  (337) 0x4485b4 VDIVSD	%XMM8,%XMM9,%XMM0

  (337) 0x4485b9 VMULSD	%XMM13,%XMM10,%XMM12

  (337) 0x4485be VFNMADD213SD	(%R11,%RAX,8),%XMM12,%XMM14

  (337) 0x4485c4 MOV	0x15c(%RSP),%R11D

  (337) 0x4485cc VMOVSD	%XMM14,(%RBX,%RAX,8)

  (337) 0x4485d1 VMULSD	(%RDX,%RAX,8),%XMM0,%XMM15

  (337) 0x4485d6 VMOVSD	%XMM15,(%R10,%RAX,8)

  (337) 0x4485dc MOV	0x1a8(%RSP),%R10D

  (337) 0x4485e4 INC	%RAX

  (337) 0x4485e7 ADD	%EAX,%R10D

  (337) 0x4485ea CMP	%R11D,%R10D

  (337) 0x4485ed JB	448504

(336) 0x4485f3 MOV	0x15c(%RSP),%R9D

(336) 0x4485fb MOV	%R9D,0x17c(%RSP)

(336) 0x448603 INCQ	0x160(%RSP)

(336) 0x44860b MOV	0x160(%RSP),%R8

(336) 0x448613 CMP	%R8D,0x98(%RSP)

(336) 0x44861b JLE	448650

(336) 0x44861d MOV	0x90(%RSP),%ECX

(336) 0x448624 MOV	0x17c(%RSP),%EDI

(336) 0x44862b MOV	0x94(%RSP),%R15D

(336) 0x448633 MOV	0x9c(%RSP),%EDX

(336) 0x44863a MOV	%R15D,0x158(%RSP)

(336) 0x448642 SUB	%EDI,%ECX

(336) 0x448644 JMP	447c90

0x448649 NOPL	(%RAX)

0x448650 VZEROUPPER

0x448653 LEA	-0x28(%RBP),%RSP

0x448657 POP	%RBX

0x448658 POP	%R12

0x44865a POP	%R13

0x44865c POP	%R14

0x44865e POP	%R15

0x448660 POP	%RBP

0x448661 RET

0x448662 NOPW	(%RAX,%RAX,1)

(336) 0x448668 MOV	0x158(%RSP),%R12D

(336) 0x448670 XOR	%EAX,%EAX

(336) 0x448672 MOV	%R12D,0x1b8(%RSP)

(336) 0x44867a JMP	448150

0x44867f INC	%ECX

0x448681 XOR	%EDX,%EDX

0x448683 JMP	447ba4

0x448688 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 4.00 cycles (4.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.67 to 3.00 cycles (6.22x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.67 to 17.50 cycles (1.07x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:63

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	102
nb uops	112
loop length	432
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.67 cycles
front end	18.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	9.33	9.33	13.00	7.40	7.20	13.00	13.00	13.00	7.20	9.33
cycles	7.20	12.10	9.33	9.33	13.00	7.40	7.20	13.00	13.00	13.00	7.20	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.67
Dispatch	13.00
DIV/SQRT	12.00
Overall L1	18.67

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

3% of peak load performance is reached (7.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.67 to 13.00 cycles (1.44x speedup).

ASM code

In the binary file, the address of the function is: 447b10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x1c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x6c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RDI),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x94(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x64(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R8D,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x9c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44867f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb6f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x17c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x9c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x94(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x27ddf(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RBX),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RSI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x278c7(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R11,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x48(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 447ba4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x94>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 4.00 cycles (4.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.67 to 17.50 cycles (1.07x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:63

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	102
nb uops	112
loop length	432
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.67 cycles
front end	18.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	8.00	9.33	9.33	13.00	7.40	7.20	13.00	13.00	13.00	7.20	9.33
cycles	7.20	12.10	9.33	9.33	13.00	7.40	7.20	13.00	13.00	13.00	7.20	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.67
Dispatch	13.00
DIV/SQRT	12.00
Overall L1	18.67

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

3% of peak load performance is reached (7.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 447b10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x1c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x6c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RDI),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x94(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x64(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R8D,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x9c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 44867f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb6f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R9,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x17c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 448653 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x9c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x94(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x27ddf(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RBX),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RSI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x278c7(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R11,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x48(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 447ba4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x94>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.13	1.48
▼Loop 336 - PdV.cpp:50-63 - exec–	0.00	0.01
○Loop 338 - PdV.cpp:51-63 - exec	5.12	1.47
○Loop 337 - PdV.cpp:55-63 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code