OV - exec - Function clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D<double>&, clover::Buffer1D<double>&, int, int, int, int, int, int, int) [clone ._omp

	Function: clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D<double>& ...	Module: exec	Source: pack_kernel.cpp:120-124 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp: 120 - 124

--------------------------------------------------------------------------------

120: #pragma omp parallel for simd

121:   for (int k = (y_min - depth + 1); k < (y_max + y_inc + depth + 2); k++) {

122:     for (int j = 0; j < depth; ++j) {

123:       int index = buffer_offset + j + k * depth;

124:       right_snd[index] = field(x_max + 1 - j, k);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4440a0 PUSH	%RBP

0x4440a1 MOV	%RSP,%RBP

0x4440a4 PUSH	%R15

0x4440a6 PUSH	%R14

0x4440a8 PUSH	%R13

0x4440aa PUSH	%R12

0x4440ac MOV	%RDI,%R12

0x4440af PUSH	%RBX

0x4440b0 AND	$-0x40,%RSP

0x4440b4 SUB	$0x40,%RSP

0x4440b8 MOV	0x1c(%RDI),%EBX

0x4440bb MOV	0x14(%RDI),%R14D

0x4440bf CALL	404630 <omp_get_num_threads@plt>

0x4440c4 MOV	%EAX,%R13D

0x4440c7 CALL	404520 <omp_get_thread_num@plt>

0x4440cc MOV	%EAX,%ECX

0x4440ce MOV	0x18(%R12),%EAX

0x4440d3 SUB	%EBX,%R14D

0x4440d6 ADD	0x24(%R12),%EAX

0x4440db INC	%R14D

0x4440de LEA	0x2(%RBX,%RAX,1),%EAX

0x4440e2 SUB	%R14D,%EAX

0x4440e5 CLTD

0x4440e6 IDIV	%R13D

0x4440e9 CMP	%EDX,%ECX

0x4440eb JL	4445d2

0x4440f1 IMUL	%EAX,%ECX

0x4440f4 ADD	%ECX,%EDX

0x4440f6 ADD	%EDX,%EAX

0x4440f8 CMP	%EAX,%EDX

0x4440fa JGE	4445c3

0x444100 MOVSXD	0x20(%R12),%RSI

0x444105 MOV	0x10(%R12),%EDI

0x44410a ADD	%R14D,%EAX

0x44410d MOV	%ESI,0x4(%RSP)

0x444111 MOV	%EDI,(%RSP)

0x444114 MOV	%EAX,0x38(%RSP)

0x444118 MOV	(%R12),%R9

0x44411c MOV	0x8(%R12),%R15

0x444121 ADD	%R14D,%EDX

0x444124 TEST	%EBX,%EBX

0x444126 JLE	4445c3

0x44412c MOVSXD	%EDX,%R11

0x44412f IMUL	%EBX,%EDX

0x444132 MOVSXD	%EBX,%R14

0x444135 LEA	(,%R14,8),%RCX

0x44413d MOVSXD	%EDX,%R8

0x444140 ADD	%RSI,%R8

0x444143 SUB	%R8D,%EDX

0x444146 MOV	$0x8,%ESI

0x44414b MOV	(%R9),%R12

0x44414e MOV	%EDX,0x1c(%RSP)

0x444152 LEA	-0x1(%RBX),%R13D

0x444156 LEA	0x1(%RDI),%EAX

0x444159 MOVSXD	%EDI,%RDX

0x44415c SUB	%RCX,%RSI

0x44415f MOV	%R14,0x20(%RSP)

0x444164 MOV	%R13D,0x3c(%RSP)

0x444169 MOV	%EBX,%R14D

0x44416c MOV	%RCX,0x30(%RSP)

0x444171 MOV	%EAX,0x18(%RSP)

0x444175 MOV	%RDX,0x10(%RSP)

0x44417a MOV	%RSI,0x8(%RSP)

0x44417f MOV	%R12,0x28(%RSP)

0x444184 SHR	$0x3,%R14D

0x444188 MOV	0x10(%R9),%R10

0x44418c MOV	0x8(%R15),%R12

0x444190 VMOVDQA64	0x2c1a6(%RIP),%ZMM0

0x44419a SAL	$0x6,%R14

(317) 0x44419e MOV	0x28(%RSP),%R9

(317) 0x4441a3 LEA	(,%R8,8),%RSI

(317) 0x4441ab IMUL	%R11,%R9

(317) 0x4441af CMPL	$0x2,0x3c(%RSP)

(317) 0x4441b4 JBE	444460

(317) 0x4441ba MOV	0x1c(%RSP),%EDI

(317) 0x4441be LEA	(%RDI,%R8,1),%ECX

  (318) 0x4441c2 MOV	0x10(%RSP),%R15

  (318) 0x4441c7 MOV	0x8(%RSP),%RAX

  (318) 0x4441cc LEA	0x2(%R9,%R15,1),%RDI

  (318) 0x4441d1 MOV	0x30(%RSP),%R15

  (318) 0x4441d6 LEA	(,%R8,8),%RSI

  (318) 0x4441de SAL	$0x3,%RDI

  (318) 0x4441e2 LEA	-0x8(%RDI,%RAX,1),%RDX

  (318) 0x4441e7 ADD	%RSI,%R15

  (318) 0x4441ea ADD	%R10,%RDX

  (318) 0x4441ed ADD	%R12,%R15

  (318) 0x4441f0 LEA	(%R12,%RSI,1),%R13

  (318) 0x4441f4 CMP	%R15,%RDX

  (318) 0x4441f7 JAE	444206

  (318) 0x4441f9 LEA	(%R10,%RDI,1),%RAX

  (318) 0x4441fd CMP	%RAX,%R13

  (318) 0x444200 JB	444460

  (318) 0x444206 CMPL	$0x6,0x3c(%RSP)

  (318) 0x44420b JBE	4445db

  (318) 0x444211 LEA	-0x40(%R14),%RSI

  (318) 0x444215 LEA	-0x40(%R10,%RDI,1),%RAX

  (318) 0x44421a SHR	$0x6,%RSI

  (318) 0x44421e MOV	%RAX,%R15

  (318) 0x444221 INC	%RSI

  (318) 0x444224 MOV	%R13,%RDX

  (318) 0x444227 SUB	%R14,%R15

  (318) 0x44422a AND	$0x7,%ESI

  (318) 0x44422d JE	4442fa

  (318) 0x444233 CMP	$0x1,%RSI

  (318) 0x444237 JE	4442dd

  (318) 0x44423d CMP	$0x2,%RSI

  (318) 0x444241 JE	4442c8

  (318) 0x444247 CMP	$0x3,%RSI

  (318) 0x44424b JE	4442b3

  (318) 0x44424d CMP	$0x4,%RSI

  (318) 0x444251 JE	44429e

  (318) 0x444253 CMP	$0x5,%RSI

  (318) 0x444257 JE	444289

  (318) 0x444259 CMP	$0x6,%RSI

  (318) 0x44425d JE	444274

  (318) 0x44425f VPERMPD	(%RAX),%ZMM0,%ZMM1

  (318) 0x444265 ADD	$0x40,%RDX

  (318) 0x444269 VMOVUPD	%ZMM1,(%R13)

  (318) 0x444270 SUB	$0x40,%RAX

  (318) 0x444274 VPERMPD	(%RAX),%ZMM0,%ZMM2

  (318) 0x44427a ADD	$0x40,%RDX

  (318) 0x44427e VMOVUPD	%ZMM2,-0x40(%RDX)

  (318) 0x444285 SUB	$0x40,%RAX

  (318) 0x444289 VPERMPD	(%RAX),%ZMM0,%ZMM3

  (318) 0x44428f ADD	$0x40,%RDX

  (318) 0x444293 VMOVUPD	%ZMM3,-0x40(%RDX)

  (318) 0x44429a SUB	$0x40,%RAX

  (318) 0x44429e VPERMPD	(%RAX),%ZMM0,%ZMM4

  (318) 0x4442a4 ADD	$0x40,%RDX

  (318) 0x4442a8 VMOVUPD	%ZMM4,-0x40(%RDX)

  (318) 0x4442af SUB	$0x40,%RAX

  (318) 0x4442b3 VPERMPD	(%RAX),%ZMM0,%ZMM5

  (318) 0x4442b9 ADD	$0x40,%RDX

  (318) 0x4442bd VMOVUPD	%ZMM5,-0x40(%RDX)

  (318) 0x4442c4 SUB	$0x40,%RAX

  (318) 0x4442c8 VPERMPD	(%RAX),%ZMM0,%ZMM6

  (318) 0x4442ce ADD	$0x40,%RDX

  (318) 0x4442d2 VMOVUPD	%ZMM6,-0x40(%RDX)

  (318) 0x4442d9 SUB	$0x40,%RAX

  (318) 0x4442dd VPERMPD	(%RAX),%ZMM0,%ZMM7

  (318) 0x4442e3 SUB	$0x40,%RAX

  (318) 0x4442e7 VMOVUPD	%ZMM7,(%RDX)

  (318) 0x4442ed ADD	$0x40,%RDX

  (318) 0x4442f1 CMP	%RAX,%R15

  (318) 0x4442f4 JE	44437a

    (319) 0x4442fa VPERMPD	(%RAX),%ZMM0,%ZMM8

    (319) 0x444300 SUB	$0x200,%RAX

    (319) 0x444306 VMOVUPD	%ZMM8,(%RDX)

    (319) 0x44430c VPERMPD	0x1c0(%RAX),%ZMM0,%ZMM9

    (319) 0x444313 ADD	$0x200,%RDX

    (319) 0x44431a VMOVUPD	%ZMM9,-0x1c0(%RDX)

    (319) 0x444321 VPERMPD	0x180(%RAX),%ZMM0,%ZMM10

    (319) 0x444328 VMOVUPD	%ZMM10,-0x180(%RDX)

    (319) 0x44432f VPERMPD	0x140(%RAX),%ZMM0,%ZMM11

    (319) 0x444336 VMOVUPD	%ZMM11,-0x140(%RDX)

    (319) 0x44433d VPERMPD	0x100(%RAX),%ZMM0,%ZMM12

    (319) 0x444344 VMOVUPD	%ZMM12,-0x100(%RDX)

    (319) 0x44434b VPERMPD	0xc0(%RAX),%ZMM0,%ZMM13

    (319) 0x444352 VMOVUPD	%ZMM13,-0xc0(%RDX)

    (319) 0x444359 VPERMPD	0x80(%RAX),%ZMM0,%ZMM14

    (319) 0x444360 VMOVUPD	%ZMM14,-0x80(%RDX)

    (319) 0x444367 VPERMPD	0x40(%RAX),%ZMM0,%ZMM15

    (319) 0x44436e VMOVUPD	%ZMM15,-0x40(%RDX)

    (319) 0x444375 CMP	%RAX,%R15

    (319) 0x444378 JNE	4442fa

  (318) 0x44437a MOV	%EBX,%EAX

  (318) 0x44437c AND	$-0x8,%EAX

  (318) 0x44437f MOV	%EAX,%EDX

  (318) 0x444381 CMP	%EAX,%EBX

  (318) 0x444383 JE	444430

  (318) 0x444389 MOV	%EBX,%ESI

  (318) 0x44438b SUB	%EAX,%ESI

  (318) 0x44438d LEA	-0x1(%RSI),%R13D

  (318) 0x444391 CMP	$0x2,%R13D

  (318) 0x444395 JBE	4443bd

  (318) 0x444397 MOV	%RDX,%R15

  (318) 0x44439a ADD	%R10,%RDI

  (318) 0x44439d NEG	%R15

  (318) 0x4443a0 VPERMPD	$0x1b,-0x20(%RDI,%R15,8),%YMM1

  (318) 0x4443a8 MOV	%ESI,%EDI

  (318) 0x4443aa AND	$-0x4,%EDI

  (318) 0x4443ad ADD	%R8,%RDX

  (318) 0x4443b0 ADD	%EDI,%EAX

  (318) 0x4443b2 AND	$0x3,%ESI

  (318) 0x4443b5 VMOVUPD	%YMM1,(%R12,%RDX,8)

  (318) 0x4443bb JE	444430

  (318) 0x4443bd MOV	0x18(%RSP),%R13D

  (318) 0x4443c2 MOV	0x4(%RSP),%R15D

  (318) 0x4443c7 MOV	%R13D,%EDX

  (318) 0x4443ca SUB	%EAX,%EDX

  (318) 0x4443cc MOVSXD	%EDX,%RSI

  (318) 0x4443cf ADD	%R9,%RSI

  (318) 0x4443d2 LEA	(%R15,%RAX,1),%EDI

  (318) 0x4443d6 ADD	%ECX,%EDI

  (318) 0x4443d8 VMOVSD	(%R10,%RSI,8),%XMM2

  (318) 0x4443de MOVSXD	%EDI,%RDX

  (318) 0x4443e1 LEA	0x1(%RAX),%EDI

  (318) 0x4443e4 VMOVSD	%XMM2,(%R12,%RDX,8)

  (318) 0x4443ea CMP	%EDI,%EBX

  (318) 0x4443ec JLE	444430

  (318) 0x4443ee MOV	(%RSP),%ESI

  (318) 0x4443f1 ADD	%R15D,%EDI

  (318) 0x4443f4 SUB	%EAX,%ESI

  (318) 0x4443f6 MOVSXD	%ESI,%RDX

  (318) 0x4443f9 ADD	%R9,%RDX

  (318) 0x4443fc VMOVSD	(%R10,%RDX,8),%XMM3

  (318) 0x444402 ADD	%ECX,%EDI

  (318) 0x444404 MOVSXD	%EDI,%RDI

  (318) 0x444407 ADD	$0x2,%EAX

  (318) 0x44440a VMOVSD	%XMM3,(%R12,%RDI,8)

  (318) 0x444410 CMP	%EAX,%EBX

  (318) 0x444412 JLE	444430

  (318) 0x444414 SUB	%EAX,%R13D

  (318) 0x444417 MOVSXD	%R13D,%R13

  (318) 0x44441a ADD	%R9,%R13

  (318) 0x44441d ADD	%R15D,%EAX

  (318) 0x444420 VMOVSD	(%R10,%R13,8),%XMM4

  (318) 0x444426 ADD	%ECX,%EAX

  (318) 0x444428 CLTQ

  (318) 0x44442a VMOVSD	%XMM4,(%R12,%RAX,8)

  (318) 0x444430 MOV	0x20(%RSP),%R9

  (318) 0x444435 INC	%R11

  (318) 0x444438 ADD	%R9,%R8

  (318) 0x44443b CMP	%R11D,0x38(%RSP)

  (318) 0x444440 JLE	4445c0

  (318) 0x444446 MOV	0x1c(%RSP),%ECX

  (318) 0x44444a MOV	0x28(%RSP),%R9

  (318) 0x44444f LEA	(%RCX,%R8,1),%ECX

  (318) 0x444453 IMUL	%R11,%R9

  (318) 0x444457 JMP	4441c2

0x44445c NOPL	(%RAX)

(317) 0x444460 MOV	0x30(%RSP),%RDI

(317) 0x444465 LEA	(%R12,%RSI,1),%R15

(317) 0x444469 ADD	%R12,%RDI

(317) 0x44446c ADD	%RDI,%RSI

(317) 0x44446f MOV	%RSI,%R13

(317) 0x444472 SUB	%R15,%R13

(317) 0x444475 MOVSXD	0x18(%RSP),%RAX

(317) 0x44447a SUB	$0x8,%R13

(317) 0x44447e SHR	$0x3,%R13

(317) 0x444482 ADD	%R9,%RAX

(317) 0x444485 INC	%R13

(317) 0x444488 LEA	(%R10,%RAX,8),%RDX

(317) 0x44448c AND	$0x7,%R13D

(317) 0x444490 JE	444541

(317) 0x444496 CMP	$0x1,%R13

(317) 0x44449a JE	44452a

(317) 0x4444a0 CMP	$0x2,%R13

(317) 0x4444a4 JE	444518

(317) 0x4444a6 CMP	$0x3,%R13

(317) 0x4444aa JE	444506

(317) 0x4444ac CMP	$0x4,%R13

(317) 0x4444b0 JE	4444f4

(317) 0x4444b2 CMP	$0x5,%R13

(317) 0x4444b6 JE	4444e2

(317) 0x4444b8 CMP	$0x6,%R13

(317) 0x4444bc JE	4444d0

(317) 0x4444be VMOVSD	(%RDX),%XMM5

(317) 0x4444c2 ADD	$0x8,%R15

(317) 0x4444c6 VMOVSD	%XMM5,-0x8(%R15)

(317) 0x4444cc SUB	$0x8,%RDX

(317) 0x4444d0 VMOVSD	(%RDX),%XMM6

(317) 0x4444d4 ADD	$0x8,%R15

(317) 0x4444d8 VMOVSD	%XMM6,-0x8(%R15)

(317) 0x4444de SUB	$0x8,%RDX

(317) 0x4444e2 VMOVSD	(%RDX),%XMM7

(317) 0x4444e6 ADD	$0x8,%R15

(317) 0x4444ea VMOVSD	%XMM7,-0x8(%R15)

(317) 0x4444f0 SUB	$0x8,%RDX

(317) 0x4444f4 VMOVSD	(%RDX),%XMM8

(317) 0x4444f8 ADD	$0x8,%R15

(317) 0x4444fc VMOVSD	%XMM8,-0x8(%R15)

(317) 0x444502 SUB	$0x8,%RDX

(317) 0x444506 VMOVSD	(%RDX),%XMM9

(317) 0x44450a ADD	$0x8,%R15

(317) 0x44450e VMOVSD	%XMM9,-0x8(%R15)

(317) 0x444514 SUB	$0x8,%RDX

(317) 0x444518 VMOVSD	(%RDX),%XMM10

(317) 0x44451c ADD	$0x8,%R15

(317) 0x444520 VMOVSD	%XMM10,-0x8(%R15)

(317) 0x444526 SUB	$0x8,%RDX

(317) 0x44452a VMOVSD	(%RDX),%XMM11

(317) 0x44452e ADD	$0x8,%R15

(317) 0x444532 VMOVSD	%XMM11,-0x8(%R15)

(317) 0x444538 SUB	$0x8,%RDX

(317) 0x44453c CMP	%R15,%RSI

(317) 0x44453f JE	4445a5

  (316) 0x444541 VMOVSD	(%RDX),%XMM12

  (316) 0x444545 ADD	$0x40,%R15

  (316) 0x444549 VMOVSD	%XMM12,-0x40(%R15)

  (316) 0x44454f VMOVSD	-0x8(%RDX),%XMM13

  (316) 0x444554 SUB	$0x40,%RDX

  (316) 0x444558 VMOVSD	%XMM13,-0x38(%R15)

  (316) 0x44455e VMOVSD	0x30(%RDX),%XMM14

  (316) 0x444563 VMOVSD	%XMM14,-0x30(%R15)

  (316) 0x444569 VMOVSD	0x28(%RDX),%XMM15

  (316) 0x44456e VMOVSD	%XMM15,-0x28(%R15)

  (316) 0x444574 VMOVSD	0x20(%RDX),%XMM1

  (316) 0x444579 VMOVSD	%XMM1,-0x20(%R15)

  (316) 0x44457f VMOVSD	0x18(%RDX),%XMM2

  (316) 0x444584 VMOVSD	%XMM2,-0x18(%R15)

  (316) 0x44458a VMOVSD	0x10(%RDX),%XMM3

  (316) 0x44458f VMOVSD	%XMM3,-0x10(%R15)

  (316) 0x444595 VMOVSD	0x8(%RDX),%XMM4

  (316) 0x44459a VMOVSD	%XMM4,-0x8(%R15)

  (316) 0x4445a0 CMP	%R15,%RSI

  (316) 0x4445a3 JNE	444541

(317) 0x4445a5 MOV	0x20(%RSP),%RSI

(317) 0x4445aa INC	%R11

(317) 0x4445ad ADD	%RSI,%R8

(317) 0x4445b0 CMP	%R11D,0x38(%RSP)

(317) 0x4445b5 JG	44419e

0x4445bb NOPL	(%RAX,%RAX,1)

0x4445c0 VZEROUPPER

0x4445c3 LEA	-0x28(%RBP),%RSP

0x4445c7 POP	%RBX

0x4445c8 POP	%R12

0x4445ca POP	%R13

0x4445cc POP	%R14

0x4445ce POP	%R15

0x4445d0 POP	%RBP

0x4445d1 RET

0x4445d2 INC	%EAX

0x4445d4 XOR	%EDX,%EDX

0x4445d6 JMP	4440f1

  (318) 0x4445db MOV	%EBX,%ESI

  (318) 0x4445dd XOR	%EDX,%EDX

  (318) 0x4445df XOR	%EAX,%EAX

  (318) 0x4445e1 JMP	444397

0x4445e6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.89	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.69	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	pack_kernel.cpp:120-124
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:120-124
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 3.53 cycles (4.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 10.77 cycles (1.39x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:122

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	84
nb uops	90
loop length	300
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	7.20	6.33	6.33	9.50	7.20	7.10	9.50	9.50	9.50	7.20	6.33
cycles	7.30	11.13	6.33	6.33	9.50	7.20	7.10	9.50	9.50	9.50	7.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.00
Dispatch	11.13
DIV/SQRT	6.00
Overall L1	15.00

Vectorization ratios

all	5%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

all	11%
load	39%
store	9%
mul	6%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

4% of peak load performance is reached (8.53 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 11.13 cycles (1.35x speedup).

ASM code

In the binary file, the address of the function is: 4440a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x14(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD 0x24(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RBX,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4445d2 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x532>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4445c3 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x20(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%R12),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4445c3 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
IMUL %EBX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOVSXD %EBX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R14,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB %R8D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R9),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x1(%RBX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RDI),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EDI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
SUB %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SHR $0x3,%R14D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x10(%R9),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R15),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQA64 0x2c1a6(%RIP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
SAL $0x6,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4440f1 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	pack_kernel.cpp:120-124
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:120-124
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 3.53 cycles (4.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:122

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:121

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	84
nb uops	90
loop length	300
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	7.20	6.33	6.33	9.50	7.20	7.10	9.50	9.50	9.50	7.20	6.33
cycles	7.30	11.13	6.33	6.33	9.50	7.20	7.10	9.50	9.50	9.50	7.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.00
Dispatch	11.13
DIV/SQRT	6.00
Overall L1	15.00

Vectorization ratios

all	5%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

all	11%
load	39%
store	9%
mul	6%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

4% of peak load performance is reached (8.53 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4440a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x14(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD 0x24(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RBX,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4445d2 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x532>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4445c3 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x20(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%R12),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4445c3 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
IMUL %EBX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOVSXD %EBX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R14,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB %R8D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R9),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x1(%RBX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RDI),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EDI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
SUB %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SHR $0x3,%R14D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x10(%R9),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R15),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQA64 0x2c1a6(%RIP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
SAL $0x6,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4440f1 <_Z25clover_pack_message_rightR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼clover_pack_message_right(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]–	0.02	0.00
▼Loop 317 - pack_kernel.cpp:121-124 - exec–	0.02	0.01
○Loop 316 - pack_kernel.cpp:122-124 - exec	0.00	0.00
▼Loop 318 - context.h:69-69 - exec–	0.00	0.00
○Loop 319 - pack_kernel.cpp:122-124 - exec	0.00	0.00

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