OV - exec - Function clover_pack_message_left(global_variables&, int, int, int, int, clover::Buffer2D<double>&, clover::Buffer1D<double>&, int, int, int, int, int, int, int) [clone ._omp

	Function: clover_pack_message_left(global_variables&, int, int, int, int, clover::Buffer2D<double>&, ...	Module: exec	Source: pack_kernel.cpp:55-59 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp: 55 - 59

--------------------------------------------------------------------------------

55: #pragma omp parallel for simd

56:   for (int k = (y_min - depth + 1); k < (y_max + y_inc + depth + 2); k++) {

57:     for (int j = 0; j < depth; ++j) {

58:       int index = buffer_offset + j + k * depth;

59:       left_snd[index] = field(x_min + x_inc - 1 + j + 2, k);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x443640 PUSH	%RBP

0x443641 MOV	%RSP,%RBP

0x443644 PUSH	%R15

0x443646 PUSH	%R14

0x443648 PUSH	%R13

0x44364a PUSH	%R12

0x44364c MOV	%RDI,%R12

0x44364f PUSH	%RBX

0x443650 AND	$-0x40,%RSP

0x443654 SUB	$0x40,%RSP

0x443658 MOV	0x1c(%RDI),%EBX

0x44365b MOV	0x14(%RDI),%R14D

0x44365f CALL	404630 <omp_get_num_threads@plt>

0x443664 MOV	%EAX,%R13D

0x443667 CALL	404520 <omp_get_thread_num@plt>

0x44366c MOV	%EAX,%ECX

0x44366e MOV	0x18(%R12),%EAX

0x443673 SUB	%EBX,%R14D

0x443676 ADD	0x28(%R12),%EAX

0x44367b INC	%R14D

0x44367e LEA	0x2(%RBX,%RAX,1),%EAX

0x443682 SUB	%R14D,%EAX

0x443685 CLTD

0x443686 IDIV	%R13D

0x443689 CMP	%EDX,%ECX

0x44368b JL	443b3b

0x443691 IMUL	%EAX,%ECX

0x443694 ADD	%ECX,%EDX

0x443696 ADD	%EDX,%EAX

0x443698 CMP	%EAX,%EDX

0x44369a JGE	4439cd

0x4436a0 MOV	0x20(%R12),%EDI

0x4436a5 ADD	%R14D,%EAX

0x4436a8 MOV	%EDI,0x38(%RSP)

0x4436ac MOV	%EAX,0x3c(%RSP)

0x4436b0 MOVSXD	0x24(%R12),%R11

0x4436b5 MOVSXD	0x10(%R12),%R8

0x4436ba MOV	(%R12),%R10

0x4436be MOV	0x8(%R12),%R9

0x4436c3 ADD	%R14D,%EDX

0x4436c6 TEST	%EBX,%EBX

0x4436c8 JLE	4439cd

0x4436ce MOV	%EDX,%R12D

0x4436d1 IMUL	%EBX,%R12D

0x4436d5 MOVSXD	%EDX,%RSI

0x4436d8 MOVSXD	%EDI,%RDX

0x4436db MOVSXD	%R12D,%R14

0x4436de LEA	(%R11,%R8,1),%EAX

0x4436e2 MOVSXD	%EBX,%R15

0x4436e5 ADD	%R14,%RDX

0x4436e8 MOV	(%R10),%R13

0x4436eb MOV	0x10(%R10),%RDI

0x4436ef SUB	%EDX,%R12D

0x4436f2 MOVSXD	%EAX,%R10

0x4436f5 LEA	(,%R15,8),%RCX

0x4436fd ADD	%R8,%R11

0x443700 DEC	%EAX

0x443702 MOV	%R10,0x8(%RSP)

0x443707 MOV	%R15,0x28(%RSP)

0x44370c MOV	%EBX,%R10D

0x44370f MOV	%R12D,0x14(%RSP)

0x443714 MOV	%RCX,0x18(%RSP)

0x443719 MOV	%R11,0x20(%RSP)

0x44371e MOV	%EAX,0x10(%RSP)

0x443722 SHR	$0x3,%R10D

0x443726 MOV	0x8(%R9),%R9

0x44372a MOV	%R13,0x30(%RSP)

0x44372f SAL	$0x6,%R10

0x443733 LEA	-0x1(%RBX),%R13D

0x443737 NOPW	(%RAX,%RAX,1)

(310) 0x443740 MOV	0x30(%RSP),%R8

(310) 0x443745 LEA	(,%RDX,8),%RCX

(310) 0x44374d IMUL	%RSI,%R8

(310) 0x443751 CMP	$0x2,%R13D

(310) 0x443755 JBE	4439e0

(310) 0x44375b MOV	0x20(%RSP),%R11

(310) 0x443760 LEA	(,%RDX,8),%RCX

(310) 0x443768 LEA	(%R11,%R8,1),%R12

(310) 0x44376c LEA	(%R9,%RCX,1),%RAX

(310) 0x443770 LEA	0x10(,%R12,8),%R11

(310) 0x443778 LEA	(%RDI,%R11,1),%R15

(310) 0x44377c MOV	%RAX,%R14

(310) 0x44377f SUB	%R15,%R14

(310) 0x443782 CMP	$0x30,%R14

(310) 0x443786 JBE	4439e0

(310) 0x44378c CMP	$0x6,%R13D

(310) 0x443790 JBE	443b44

(310) 0x443796 LEA	-0x40(%R10),%R14

(310) 0x44379a SHR	$0x6,%R14

(310) 0x44379e INC	%R14

(310) 0x4437a1 LEA	-0x8(%RDI,%R11,1),%R15

(310) 0x4437a6 XOR	%R11D,%R11D

(310) 0x4437a9 AND	$0x7,%R14D

(310) 0x4437ad JE	443862

(310) 0x4437b3 CMP	$0x1,%R14

(310) 0x4437b7 JE	443847

(310) 0x4437bd CMP	$0x2,%R14

(310) 0x4437c1 JE	443835

(310) 0x4437c3 CMP	$0x3,%R14

(310) 0x4437c7 JE	443823

(310) 0x4437c9 CMP	$0x4,%R14

(310) 0x4437cd JE	443811

(310) 0x4437cf CMP	$0x5,%R14

(310) 0x4437d3 JE	4437ff

(310) 0x4437d5 CMP	$0x6,%R14

(310) 0x4437d9 JE	4437ed

(310) 0x4437db VMOVUPD	(%R15),%ZMM0

(310) 0x4437e1 MOV	$0x40,%R11D

(310) 0x4437e7 VMOVUPD	%ZMM0,(%RAX)

(310) 0x4437ed VMOVUPD	(%R15,%R11,1),%ZMM1

(310) 0x4437f4 VMOVUPD	%ZMM1,(%RAX,%R11,1)

(310) 0x4437fb ADD	$0x40,%R11

(310) 0x4437ff VMOVUPD	(%R15,%R11,1),%ZMM2

(310) 0x443806 VMOVUPD	%ZMM2,(%RAX,%R11,1)

(310) 0x44380d ADD	$0x40,%R11

(310) 0x443811 VMOVUPD	(%R15,%R11,1),%ZMM3

(310) 0x443818 VMOVUPD	%ZMM3,(%RAX,%R11,1)

(310) 0x44381f ADD	$0x40,%R11

(310) 0x443823 VMOVUPD	(%R15,%R11,1),%ZMM4

(310) 0x44382a VMOVUPD	%ZMM4,(%RAX,%R11,1)

(310) 0x443831 ADD	$0x40,%R11

(310) 0x443835 VMOVUPD	(%R15,%R11,1),%ZMM5

(310) 0x44383c VMOVUPD	%ZMM5,(%RAX,%R11,1)

(310) 0x443843 ADD	$0x40,%R11

(310) 0x443847 VMOVUPD	(%R15,%R11,1),%ZMM6

(310) 0x44384e VMOVUPD	%ZMM6,(%RAX,%R11,1)

(310) 0x443855 ADD	$0x40,%R11

(310) 0x443859 CMP	%R11,%R10

(310) 0x44385c JE	4438f0

  (311) 0x443862 VMOVUPD	(%R15,%R11,1),%ZMM7

  (311) 0x443869 VMOVUPD	%ZMM7,(%RAX,%R11,1)

  (311) 0x443870 VMOVUPD	0x40(%R15,%R11,1),%ZMM8

  (311) 0x443878 VMOVUPD	%ZMM8,0x40(%RAX,%R11,1)

  (311) 0x443880 VMOVUPD	0x80(%R15,%R11,1),%ZMM9

  (311) 0x443888 VMOVUPD	%ZMM9,0x80(%RAX,%R11,1)

  (311) 0x443890 VMOVUPD	0xc0(%R15,%R11,1),%ZMM10

  (311) 0x443898 VMOVUPD	%ZMM10,0xc0(%RAX,%R11,1)

  (311) 0x4438a0 VMOVUPD	0x100(%R15,%R11,1),%ZMM11

  (311) 0x4438a8 VMOVUPD	%ZMM11,0x100(%RAX,%R11,1)

  (311) 0x4438b0 VMOVUPD	0x140(%R15,%R11,1),%ZMM12

  (311) 0x4438b8 VMOVUPD	%ZMM12,0x140(%RAX,%R11,1)

  (311) 0x4438c0 VMOVUPD	0x180(%R15,%R11,1),%ZMM13

  (311) 0x4438c8 VMOVUPD	%ZMM13,0x180(%RAX,%R11,1)

  (311) 0x4438d0 VMOVUPD	0x1c0(%R15,%R11,1),%ZMM14

  (311) 0x4438d8 VMOVUPD	%ZMM14,0x1c0(%RAX,%R11,1)

  (311) 0x4438e0 ADD	$0x200,%R11

  (311) 0x4438e7 CMP	%R11,%R10

  (311) 0x4438ea JNE	443862

(310) 0x4438f0 MOV	%EBX,%EAX

(310) 0x4438f2 AND	$-0x8,%EAX

(310) 0x4438f5 MOV	%EAX,%ECX

(310) 0x4438f7 CMP	%EAX,%EBX

(310) 0x4438f9 JE	4439b5

(310) 0x4438ff MOV	%EBX,%R11D

(310) 0x443902 SUB	%EAX,%R11D

(310) 0x443905 LEA	-0x1(%R11),%R15D

(310) 0x443909 CMP	$0x2,%R15D

(310) 0x44390d JBE	443935

(310) 0x44390f LEA	0x1(%R12,%RCX,1),%R12

(310) 0x443914 VMOVUPD	(%RDI,%R12,8),%YMM15

(310) 0x44391a ADD	%RDX,%RCX

(310) 0x44391d VMOVUPD	%YMM15,(%R9,%RCX,8)

(310) 0x443923 MOV	%R11D,%ECX

(310) 0x443926 AND	$-0x4,%ECX

(310) 0x443929 ADD	%ECX,%EAX

(310) 0x44392b AND	$0x3,%R11D

(310) 0x44392f JE	4439b5

(310) 0x443935 MOV	0x14(%RSP),%R14D

(310) 0x44393a MOV	0x10(%RSP),%R15D

(310) 0x44393f LEA	(%R14,%RDX,1),%R12D

(310) 0x443943 LEA	0x2(%RAX,%R15,1),%R11D

(310) 0x443948 MOV	0x38(%RSP),%R14D

(310) 0x44394d MOVSXD	%R11D,%RCX

(310) 0x443950 ADD	%R8,%RCX

(310) 0x443953 LEA	(%R14,%RAX,1),%R11D

(310) 0x443957 VMOVSD	(%RDI,%RCX,8),%XMM0

(310) 0x44395c ADD	%R12D,%R11D

(310) 0x44395f MOVSXD	%R11D,%RCX

(310) 0x443962 VMOVSD	%XMM0,(%R9,%RCX,8)

(310) 0x443968 LEA	0x1(%RAX),%ECX

(310) 0x44396b CMP	%EBX,%ECX

(310) 0x44396d JGE	4439b5

(310) 0x44396f LEA	0x2(%RCX,%R15,1),%R11D

(310) 0x443974 MOVSXD	%R11D,%R11

(310) 0x443977 ADD	%R8,%R11

(310) 0x44397a ADD	%R14D,%ECX

(310) 0x44397d VMOVSD	(%RDI,%R11,8),%XMM1

(310) 0x443983 ADD	%R12D,%ECX

(310) 0x443986 MOVSXD	%ECX,%RCX

(310) 0x443989 ADD	$0x2,%EAX

(310) 0x44398c VMOVSD	%XMM1,(%R9,%RCX,8)

(310) 0x443992 CMP	%EAX,%EBX

(310) 0x443994 JLE	4439b5

(310) 0x443996 LEA	0x2(%RAX,%R15,1),%R15D

(310) 0x44399b MOVSXD	%R15D,%R11

(310) 0x44399e ADD	%R8,%R11

(310) 0x4439a1 ADD	%R14D,%EAX

(310) 0x4439a4 VMOVSD	(%RDI,%R11,8),%XMM2

(310) 0x4439aa ADD	%R12D,%EAX

(310) 0x4439ad CLTQ

(310) 0x4439af VMOVSD	%XMM2,(%R9,%RAX,8)

(310) 0x4439b5 MOV	0x28(%RSP),%RCX

(310) 0x4439ba INC	%RSI

(310) 0x4439bd ADD	%RCX,%RDX

(310) 0x4439c0 CMP	%ESI,0x3c(%RSP)

(310) 0x4439c4 JG	443740

0x4439ca VZEROUPPER

0x4439cd LEA	-0x28(%RBP),%RSP

0x4439d1 POP	%RBX

0x4439d2 POP	%R12

0x4439d4 POP	%R13

0x4439d6 POP	%R14

0x4439d8 POP	%R15

0x4439da POP	%RBP

0x4439db RET

0x4439dc NOPL	(%RAX)

(310) 0x4439e0 MOV	0x18(%RSP),%R12

(310) 0x4439e5 MOV	0x8(%RSP),%RAX

(310) 0x4439ea LEA	-0x8(%R12),%R14

(310) 0x4439ef SHR	$0x3,%R14

(310) 0x4439f3 ADD	%RAX,%R8

(310) 0x4439f6 INC	%R14

(310) 0x4439f9 LEA	(%RDI,%R8,8),%R8

(310) 0x4439fd ADD	%R9,%RCX

(310) 0x443a00 XOR	%R11D,%R11D

(310) 0x443a03 AND	$0x7,%R14D

(310) 0x443a07 JE	443ab9

(310) 0x443a0d CMP	$0x1,%R14

(310) 0x443a11 JE	443a9a

(310) 0x443a17 CMP	$0x2,%R14

(310) 0x443a1b JE	443a89

(310) 0x443a1d CMP	$0x3,%R14

(310) 0x443a21 JE	443a78

(310) 0x443a23 CMP	$0x4,%R14

(310) 0x443a27 JE	443a67

(310) 0x443a29 CMP	$0x5,%R14

(310) 0x443a2d JE	443a56

(310) 0x443a2f CMP	$0x6,%R14

(310) 0x443a33 JE	443a45

(310) 0x443a35 VMOVSD	0x8(%R8),%XMM3

(310) 0x443a3b MOV	$0x8,%R11D

(310) 0x443a41 VMOVSD	%XMM3,(%RCX)

(310) 0x443a45 VMOVSD	0x8(%R8,%R11,1),%XMM4

(310) 0x443a4c VMOVSD	%XMM4,(%RCX,%R11,1)

(310) 0x443a52 ADD	$0x8,%R11

(310) 0x443a56 VMOVSD	0x8(%R8,%R11,1),%XMM5

(310) 0x443a5d VMOVSD	%XMM5,(%RCX,%R11,1)

(310) 0x443a63 ADD	$0x8,%R11

(310) 0x443a67 VMOVSD	0x8(%R8,%R11,1),%XMM6

(310) 0x443a6e VMOVSD	%XMM6,(%RCX,%R11,1)

(310) 0x443a74 ADD	$0x8,%R11

(310) 0x443a78 VMOVSD	0x8(%R8,%R11,1),%XMM7

(310) 0x443a7f VMOVSD	%XMM7,(%RCX,%R11,1)

(310) 0x443a85 ADD	$0x8,%R11

(310) 0x443a89 VMOVSD	0x8(%R8,%R11,1),%XMM8

(310) 0x443a90 VMOVSD	%XMM8,(%RCX,%R11,1)

(310) 0x443a96 ADD	$0x8,%R11

(310) 0x443a9a VMOVSD	0x8(%R8,%R11,1),%XMM9

(310) 0x443aa1 MOV	0x18(%RSP),%R15

(310) 0x443aa6 VMOVSD	%XMM9,(%RCX,%R11,1)

(310) 0x443aac ADD	$0x8,%R11

(310) 0x443ab0 CMP	%R15,%R11

(310) 0x443ab3 JE	4439b5

  (309) 0x443ab9 VMOVSD	0x8(%R8,%R11,1),%XMM10

  (309) 0x443ac0 MOV	0x18(%RSP),%RAX

  (309) 0x443ac5 VMOVSD	%XMM10,(%RCX,%R11,1)

  (309) 0x443acb VMOVSD	0x10(%R8,%R11,1),%XMM11

  (309) 0x443ad2 VMOVSD	%XMM11,0x8(%RCX,%R11,1)

  (309) 0x443ad9 VMOVSD	0x18(%R8,%R11,1),%XMM12

  (309) 0x443ae0 VMOVSD	%XMM12,0x10(%RCX,%R11,1)

  (309) 0x443ae7 VMOVSD	0x20(%R8,%R11,1),%XMM13

  (309) 0x443aee VMOVSD	%XMM13,0x18(%RCX,%R11,1)

  (309) 0x443af5 VMOVSD	0x28(%R8,%R11,1),%XMM14

  (309) 0x443afc VMOVSD	%XMM14,0x20(%RCX,%R11,1)

  (309) 0x443b03 VMOVSD	0x30(%R8,%R11,1),%XMM15

  (309) 0x443b0a VMOVSD	%XMM15,0x28(%RCX,%R11,1)

  (309) 0x443b11 VMOVSD	0x38(%R8,%R11,1),%XMM0

  (309) 0x443b18 VMOVSD	%XMM0,0x30(%RCX,%R11,1)

  (309) 0x443b1f VMOVSD	0x40(%R8,%R11,1),%XMM1

  (309) 0x443b26 VMOVSD	%XMM1,0x38(%RCX,%R11,1)

  (309) 0x443b2d ADD	$0x40,%R11

  (309) 0x443b31 CMP	%RAX,%R11

  (309) 0x443b34 JNE	443ab9

(310) 0x443b36 JMP	4439b5

0x443b3b INC	%EAX

0x443b3d XOR	%EDX,%EDX

0x443b3f JMP	443691

(310) 0x443b44 MOV	%EBX,%R11D

(310) 0x443b47 XOR	%ECX,%ECX

(310) 0x443b49 XOR	%EAX,%EAX

(310) 0x443b4b JMP	44390f

Coverage (%)	Name	Source Location	Module
○97.50	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.00	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	pack_kernel.cpp:55-59
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:55-59
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.83 to 1.50 cycles (9.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:57

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	83
nb uops	89
loop length	287
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	7.40	6.33	6.33	8.50	7.47	7.30	8.50	8.50	8.50	7.33	6.33
cycles	7.50	11.47	6.33	6.33	8.50	7.47	7.30	8.50	8.50	8.50	7.33	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	14.83
Dispatch	11.47
DIV/SQRT	6.00
Overall L1	14.83

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.58 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.83 to 11.47 cycles (1.29x speedup).

ASM code

In the binary file, the address of the function is: 443640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x14(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD 0x28(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x2(%RBX,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 443b3b <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4439cd <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x38d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R12),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD 0x24(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x10(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4439cd <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x38d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EBX,%R12D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %EDX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %EDI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %R12D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (%R11,%R8,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EBX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV (%R10),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R10),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EBX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12D,0x14(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x8(%R9),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RBX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 443691 <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	pack_kernel.cpp:55-59
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:55-59
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:57

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/pack_kernel.cpp:56

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	83
nb uops	89
loop length	287
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	7.40	6.33	6.33	8.50	7.47	7.30	8.50	8.50	8.50	7.33	6.33
cycles	7.50	11.47	6.33	6.33	8.50	7.47	7.30	8.50	8.50	8.50	7.33	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	14.83
Dispatch	11.47
DIV/SQRT	6.00
Overall L1	14.83

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	6%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.58 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 443640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x14(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EBX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD 0x28(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x2(%RBX,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 443b3b <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x4fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4439cd <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x38d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R12),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD 0x24(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x10(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4439cd <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x38d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EBX,%R12D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %EDX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %EDI,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOVSXD %R12D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (%R11,%R8,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EBX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV (%R10),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R10),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EBX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12D,0x14(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x8(%R9),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RBX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 443691 <_Z24clover_pack_message_leftR16global_variablesiiiiRN6clover8Buffer2DIdEERNS1_8Buffer1DIdEEiiiiiii._omp_fn.0+0x51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼clover_pack_message_left(global_variables&, int, int, int, int, clover::Buffer2D&, clover::Buffer1D&, int, int, int, int, int, int, int) [clone ._omp_fn.0]–	0.01	0.00
▼Loop 310 - pack_kernel.cpp:55-59 - exec–	0.01	0.01
○Loop 309 - pack_kernel.cpp:57-59 - exec	0.00	0.00
○Loop 311 - pack_kernel.cpp:57-59 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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