OV - exec - Function initialise_chunk(int, global_variables&) [clone ._omp

	Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4]	Module: exec	Source: initialise_chunk.cpp:77-82 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 82

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x440880 PUSH	%RBP

0x440881 MOV	%RSP,%RBP

0x440884 PUSH	%R15

0x440886 PUSH	%R14

0x440888 PUSH	%R13

0x44088a PUSH	%R12

0x44088c PUSH	%RBX

0x44088d AND	$-0x40,%RSP

0x440891 ADD	$-0x80,%RSP

0x440895 MOV	0x1c(%RDI),%R14D

0x440899 MOV	0x18(%RDI),%R15D

0x44089d MOV	%R14D,0x68(%RSP)

0x4408a2 MOV	%R15D,0x3c(%RSP)

0x4408a7 TEST	%R14D,%R14D

0x4408aa JLE	440e23

0x4408b0 TEST	%R15D,%R15D

0x4408b3 JLE	440e23

0x4408b9 MOV	%RDI,%R12

0x4408bc CALL	404630 <omp_get_num_threads@plt>

0x4408c1 MOV	%EAX,%EBX

0x4408c3 CALL	404520 <omp_get_thread_num@plt>

0x4408c8 MOV	%EAX,%ESI

0x4408ca MOV	%R14D,%EAX

0x4408cd IMUL	%R15D,%EAX

0x4408d1 XOR	%EDX,%EDX

0x4408d3 DIV	%EBX

0x4408d5 MOV	%EAX,%R14D

0x4408d8 CMP	%EDX,%ESI

0x4408da JB	440e44

0x4408e0 IMUL	%R14D,%ESI

0x4408e4 LEA	(%RSI,%RDX,1),%R10D

0x4408e8 LEA	(%R14,%R10,1),%EDI

0x4408ec MOV	%EDI,0x38(%RSP)

0x4408f0 CMP	%EDI,%R10D

0x4408f3 JAE	440e23

0x4408f9 MOV	0x3c(%RSP),%R8D

0x4408fe MOV	%R10D,%EAX

0x440901 XOR	%EDX,%EDX

0x440903 DIV	%R8D

0x440906 VMOVSD	0x8(%R12),%XMM2

0x44090d MOV	0x10(%R12),%R13

0x440912 VMULSD	(%R12),%XMM2,%XMM4

0x440918 VBROADCASTSD	%XMM4,%YMM3

0x44091d VBROADCASTSD	%XMM4,%ZMM0

0x440923 SUB	%EDX,%R8D

0x440926 MOV	%EDX,0x6c(%RSP)

0x44092a MOVSXD	%EAX,%RBX

0x44092d MOV	%R8D,%EDX

(296) 0x440930 CMP	%EDX,%R14D

(296) 0x440933 CMOVBE	%R14D,%EDX

(296) 0x440937 LEA	(%R10,%RDX,1),%R14D

(296) 0x44093b CMP	%R14D,%R10D

(296) 0x44093e JAE	440dfa

(296) 0x440944 MOV	0x2d0(%R13),%R12

(296) 0x44094b MOV	0x290(%R13),%RSI

(296) 0x440952 MOV	%R12,0x70(%RSP)

(296) 0x440957 MOV	0x2a8(%R13),%R11

(296) 0x44095e MOV	0x2c0(%R13),%R12

(296) 0x440965 IMUL	%RBX,%RSI

(296) 0x440969 IMUL	%RBX,%R11

(296) 0x44096d IMUL	%RBX,%R12

(296) 0x440971 MOV	0x2a0(%R13),%R9

(296) 0x440978 MOV	0x248(%R13),%RCX

(296) 0x44097f MOV	0x2b8(%R13),%RDI

(296) 0x440986 MOV	0x228(%R13),%R15

(296) 0x44098d LEA	-0x1(%RDX),%EAX

(296) 0x440990 MOV	%R9,0x48(%RSP)

(296) 0x440995 MOV	%RSI,0x40(%RSP)

(296) 0x44099a MOV	%RDI,0x60(%RSP)

(296) 0x44099f MOV	%R11,0x50(%RSP)

(296) 0x4409a4 MOV	%R15,0x78(%RSP)

(296) 0x4409a9 MOV	%R12,0x58(%RSP)

(296) 0x4409ae LEA	(%RCX,%RBX,8),%RCX

(296) 0x4409b2 CMP	$0x6,%EAX

(296) 0x4409b5 JBE	440e38

(296) 0x4409bb MOVSXD	0x6c(%RSP),%RAX

(296) 0x4409c0 LEA	(%RSI,%RAX,1),%R8

(296) 0x4409c4 LEA	(%R11,%RAX,1),%RSI

(296) 0x4409c8 LEA	(%R9,%R8,8),%R9

(296) 0x4409cc LEA	(%RDI,%RSI,8),%R8

(296) 0x4409d0 LEA	(%R15,%RAX,8),%RDI

(296) 0x4409d4 ADD	%R12,%RAX

(296) 0x4409d7 MOV	%EDX,%R12D

(296) 0x4409da MOV	0x70(%RSP),%R11

(296) 0x4409df SHR	$0x3,%R12D

(296) 0x4409e3 SAL	$0x6,%R12

(296) 0x4409e7 LEA	(%R11,%RAX,8),%RSI

(296) 0x4409eb LEA	-0x40(%R12),%R11

(296) 0x4409f0 SHR	$0x6,%R11

(296) 0x4409f4 INC	%R11

(296) 0x4409f7 XOR	%EAX,%EAX

(296) 0x4409f9 AND	$0x7,%R11D

(296) 0x4409fd JE	440b48

(296) 0x440a03 CMP	$0x1,%R11

(296) 0x440a07 JE	440b14

(296) 0x440a0d CMP	$0x2,%R11

(296) 0x440a11 JE	440aee

(296) 0x440a17 CMP	$0x3,%R11

(296) 0x440a1b JE	440ac8

(296) 0x440a21 CMP	$0x4,%R11

(296) 0x440a25 JE	440aa2

(296) 0x440a27 CMP	$0x5,%R11

(296) 0x440a2b JE	440a7c

(296) 0x440a2d CMP	$0x6,%R11

(296) 0x440a31 JE	440a56

(296) 0x440a33 VMOVUPD	%ZMM0,(%R9)

(296) 0x440a39 VBROADCASTSD	(%RCX),%ZMM1

(296) 0x440a3f MOV	$0x40,%EAX

(296) 0x440a44 VMOVUPD	%ZMM1,(%R8)

(296) 0x440a4a VMOVUPD	(%RDI),%ZMM5

(296) 0x440a50 VMOVUPD	%ZMM5,(%RSI)

(296) 0x440a56 VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440a5d VBROADCASTSD	(%RCX),%ZMM6

(296) 0x440a63 VMOVUPD	%ZMM6,(%R8,%RAX,1)

(296) 0x440a6a VMOVUPD	(%RDI,%RAX,1),%ZMM7

(296) 0x440a71 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(296) 0x440a78 ADD	$0x40,%RAX

(296) 0x440a7c VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440a83 VBROADCASTSD	(%RCX),%ZMM8

(296) 0x440a89 VMOVUPD	%ZMM8,(%R8,%RAX,1)

(296) 0x440a90 VMOVUPD	(%RDI,%RAX,1),%ZMM9

(296) 0x440a97 VMOVUPD	%ZMM9,(%RSI,%RAX,1)

(296) 0x440a9e ADD	$0x40,%RAX

(296) 0x440aa2 VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440aa9 VBROADCASTSD	(%RCX),%ZMM10

(296) 0x440aaf VMOVUPD	%ZMM10,(%R8,%RAX,1)

(296) 0x440ab6 VMOVUPD	(%RDI,%RAX,1),%ZMM11

(296) 0x440abd VMOVUPD	%ZMM11,(%RSI,%RAX,1)

(296) 0x440ac4 ADD	$0x40,%RAX

(296) 0x440ac8 VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440acf VBROADCASTSD	(%RCX),%ZMM12

(296) 0x440ad5 VMOVUPD	%ZMM12,(%R8,%RAX,1)

(296) 0x440adc VMOVUPD	(%RDI,%RAX,1),%ZMM13

(296) 0x440ae3 VMOVUPD	%ZMM13,(%RSI,%RAX,1)

(296) 0x440aea ADD	$0x40,%RAX

(296) 0x440aee VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440af5 VBROADCASTSD	(%RCX),%ZMM14

(296) 0x440afb VMOVUPD	%ZMM14,(%R8,%RAX,1)

(296) 0x440b02 VMOVUPD	(%RDI,%RAX,1),%ZMM15

(296) 0x440b09 VMOVUPD	%ZMM15,(%RSI,%RAX,1)

(296) 0x440b10 ADD	$0x40,%RAX

(296) 0x440b14 VMOVUPD	%ZMM0,(%R9,%RAX,1)

(296) 0x440b1b VBROADCASTSD	(%RCX),%ZMM2

(296) 0x440b21 MOV	0x78(%RSP),%R15

(296) 0x440b26 VMOVUPD	%ZMM2,(%R8,%RAX,1)

(296) 0x440b2d VMOVUPD	(%RDI,%RAX,1),%ZMM1

(296) 0x440b34 VMOVUPD	%ZMM1,(%RSI,%RAX,1)

(296) 0x440b3b ADD	$0x40,%RAX

(296) 0x440b3f CMP	%RAX,%R12

(296) 0x440b42 JE	440c88

  (297) 0x440b48 VMOVUPD	%ZMM0,(%R9,%RAX,1)

  (297) 0x440b4f VBROADCASTSD	(%RCX),%ZMM5

  (297) 0x440b55 VMOVUPD	%ZMM5,(%R8,%RAX,1)

  (297) 0x440b5c VMOVUPD	(%RDI,%RAX,1),%ZMM6

  (297) 0x440b63 VMOVUPD	%ZMM6,(%RSI,%RAX,1)

  (297) 0x440b6a VMOVUPD	%ZMM0,0x40(%R9,%RAX,1)

  (297) 0x440b72 VBROADCASTSD	(%RCX),%ZMM7

  (297) 0x440b78 VMOVUPD	%ZMM7,0x40(%R8,%RAX,1)

  (297) 0x440b80 VMOVUPD	0x40(%RDI,%RAX,1),%ZMM8

  (297) 0x440b88 VMOVUPD	%ZMM8,0x40(%RSI,%RAX,1)

  (297) 0x440b90 VMOVUPD	%ZMM0,0x80(%R9,%RAX,1)

  (297) 0x440b98 VBROADCASTSD	(%RCX),%ZMM9

  (297) 0x440b9e VMOVUPD	%ZMM9,0x80(%R8,%RAX,1)

  (297) 0x440ba6 VMOVUPD	0x80(%RDI,%RAX,1),%ZMM10

  (297) 0x440bae VMOVUPD	%ZMM10,0x80(%RSI,%RAX,1)

  (297) 0x440bb6 VMOVUPD	%ZMM0,0xc0(%R9,%RAX,1)

  (297) 0x440bbe VBROADCASTSD	(%RCX),%ZMM11

  (297) 0x440bc4 VMOVUPD	%ZMM11,0xc0(%R8,%RAX,1)

  (297) 0x440bcc VMOVUPD	0xc0(%RDI,%RAX,1),%ZMM12

  (297) 0x440bd4 VMOVUPD	%ZMM12,0xc0(%RSI,%RAX,1)

  (297) 0x440bdc VMOVUPD	%ZMM0,0x100(%R9,%RAX,1)

  (297) 0x440be4 VBROADCASTSD	(%RCX),%ZMM13

  (297) 0x440bea VMOVUPD	%ZMM13,0x100(%R8,%RAX,1)

  (297) 0x440bf2 VMOVUPD	0x100(%RDI,%RAX,1),%ZMM14

  (297) 0x440bfa VMOVUPD	%ZMM14,0x100(%RSI,%RAX,1)

  (297) 0x440c02 VMOVUPD	%ZMM0,0x140(%R9,%RAX,1)

  (297) 0x440c0a VBROADCASTSD	(%RCX),%ZMM15

  (297) 0x440c10 VMOVUPD	%ZMM15,0x140(%R8,%RAX,1)

  (297) 0x440c18 VMOVUPD	0x140(%RDI,%RAX,1),%ZMM2

  (297) 0x440c20 VMOVUPD	%ZMM2,0x140(%RSI,%RAX,1)

  (297) 0x440c28 VMOVUPD	%ZMM0,0x180(%R9,%RAX,1)

  (297) 0x440c30 VBROADCASTSD	(%RCX),%ZMM1

  (297) 0x440c36 VMOVUPD	%ZMM1,0x180(%R8,%RAX,1)

  (297) 0x440c3e VMOVUPD	0x180(%RDI,%RAX,1),%ZMM5

  (297) 0x440c46 VMOVUPD	%ZMM5,0x180(%RSI,%RAX,1)

  (297) 0x440c4e VMOVUPD	%ZMM0,0x1c0(%R9,%RAX,1)

  (297) 0x440c56 VBROADCASTSD	(%RCX),%ZMM6

  (297) 0x440c5c VMOVUPD	%ZMM6,0x1c0(%R8,%RAX,1)

  (297) 0x440c64 VMOVUPD	0x1c0(%RDI,%RAX,1),%ZMM7

  (297) 0x440c6c VMOVUPD	%ZMM7,0x1c0(%RSI,%RAX,1)

  (297) 0x440c74 ADD	$0x200,%RAX

  (297) 0x440c7a CMP	%RAX,%R12

  (297) 0x440c7d JNE	440b48

(296) 0x440c83 MOV	%R15,0x78(%RSP)

(296) 0x440c88 MOV	0x6c(%RSP),%EDI

(296) 0x440c8c MOV	%EDX,%R9D

(296) 0x440c8f AND	$-0x8,%R9D

(296) 0x440c93 ADD	%R9D,%EDI

(296) 0x440c96 ADD	%R9D,%R10D

(296) 0x440c99 TEST	$0x7,%DL

(296) 0x440c9c JE	440df7

(296) 0x440ca2 SUB	%R9D,%EDX

(296) 0x440ca5 LEA	-0x1(%RDX),%R8D

(296) 0x440ca9 CMP	$0x2,%R8D

(296) 0x440cad JBE	440d23

(296) 0x440caf MOVSXD	0x6c(%RSP),%RSI

(296) 0x440cb4 MOV	0x40(%RSP),%R12

(296) 0x440cb9 MOV	0x50(%RSP),%R15

(296) 0x440cbe VMOVSD	(%RCX),%XMM8

(296) 0x440cc2 LEA	(%R12,%RSI,1),%R11

(296) 0x440cc6 MOV	0x48(%RSP),%RAX

(296) 0x440ccb ADD	%R9,%R11

(296) 0x440cce LEA	(%R15,%RSI,1),%R8

(296) 0x440cd2 MOV	0x60(%RSP),%R12

(296) 0x440cd7 MOV	0x58(%RSP),%R15

(296) 0x440cdc VMOVUPD	%YMM3,(%RAX,%R11,8)

(296) 0x440ce2 ADD	%R9,%R8

(296) 0x440ce5 MOV	0x78(%RSP),%R11

(296) 0x440cea VBROADCASTSD	%XMM8,%YMM9

(296) 0x440cef LEA	(%RSI,%R9,1),%RAX

(296) 0x440cf3 VMOVUPD	%YMM9,(%R12,%R8,8)

(296) 0x440cf9 ADD	%R15,%RSI

(296) 0x440cfc ADD	%R9,%RSI

(296) 0x440cff VMOVUPD	(%R11,%RAX,8),%YMM10

(296) 0x440d05 MOV	0x70(%RSP),%R9

(296) 0x440d0a VMOVUPD	%YMM10,(%R9,%RSI,8)

(296) 0x440d10 MOV	%EDX,%ESI

(296) 0x440d12 AND	$-0x4,%ESI

(296) 0x440d15 ADD	%ESI,%EDI

(296) 0x440d17 ADD	%ESI,%R10D

(296) 0x440d1a AND	$0x3,%EDX

(296) 0x440d1d JE	440df7

(296) 0x440d23 MOV	0x40(%RSP),%R11

(296) 0x440d28 MOVSXD	%EDI,%RAX

(296) 0x440d2b MOV	0x48(%RSP),%R12

(296) 0x440d30 LEA	(%R11,%RAX,1),%RDX

(296) 0x440d34 VMOVSD	%XMM4,(%R12,%RDX,8)

(296) 0x440d3a MOV	0x50(%RSP),%R9

(296) 0x440d3f VMOVSD	(%RCX),%XMM11

(296) 0x440d43 MOV	0x60(%RSP),%R15

(296) 0x440d48 LEA	(%R9,%RAX,1),%R8

(296) 0x440d4c MOV	0x78(%RSP),%RSI

(296) 0x440d51 VMOVSD	%XMM11,(%R15,%R8,8)

(296) 0x440d57 MOV	0x58(%RSP),%R8

(296) 0x440d5c VMOVSD	(%RSI,%RAX,8),%XMM12

(296) 0x440d61 MOV	0x70(%RSP),%R15

(296) 0x440d66 LEA	(,%RAX,8),%RDX

(296) 0x440d6e ADD	%R8,%RAX

(296) 0x440d71 VMOVSD	%XMM12,(%R15,%RAX,8)

(296) 0x440d77 LEA	0x1(%R10),%EAX

(296) 0x440d7b CMP	%R14D,%EAX

(296) 0x440d7e JAE	440df7

(296) 0x440d80 LEA	0x1(%RDI),%EAX

(296) 0x440d83 CLTQ

(296) 0x440d85 LEA	(%R11,%RAX,1),%RSI

(296) 0x440d89 VMOVSD	%XMM4,(%R12,%RSI,8)

(296) 0x440d8f VMOVSD	(%RCX),%XMM13

(296) 0x440d93 MOV	0x60(%RSP),%R15

(296) 0x440d98 LEA	(%R9,%RAX,1),%RSI

(296) 0x440d9c VMOVSD	%XMM13,(%R15,%RSI,8)

(296) 0x440da2 MOV	0x78(%RSP),%RSI

(296) 0x440da7 ADD	%R8,%RAX

(296) 0x440daa VMOVSD	0x8(%RSI,%RDX,1),%XMM14

(296) 0x440db0 MOV	%R8,%RSI

(296) 0x440db3 MOV	0x70(%RSP),%R8

(296) 0x440db8 ADD	$0x2,%R10D

(296) 0x440dbc VMOVSD	%XMM14,(%R8,%RAX,8)

(296) 0x440dc2 CMP	%R14D,%R10D

(296) 0x440dc5 JAE	440df7

(296) 0x440dc7 ADD	$0x2,%EDI

(296) 0x440dca MOVSXD	%EDI,%R10

(296) 0x440dcd ADD	%R10,%R11

(296) 0x440dd0 VMOVSD	%XMM4,(%R12,%R11,8)

(296) 0x440dd6 VMOVSD	(%RCX),%XMM15

(296) 0x440dda ADD	%R10,%R9

(296) 0x440ddd MOV	0x78(%RSP),%RCX

(296) 0x440de2 VMOVSD	%XMM15,(%R15,%R9,8)

(296) 0x440de8 VMOVSD	0x10(%RCX,%RDX,1),%XMM2

(296) 0x440dee ADD	%R10,%RSI

(296) 0x440df1 VMOVSD	%XMM2,(%R8,%RSI,8)

(296) 0x440df7 MOV	%R14D,%R10D

(296) 0x440dfa INC	%RBX

(296) 0x440dfd CMP	%EBX,0x68(%RSP)

(296) 0x440e01 JLE	440e20

(296) 0x440e03 MOV	0x38(%RSP),%R14D

(296) 0x440e08 MOVL	$0,0x6c(%RSP)

(296) 0x440e10 MOV	0x3c(%RSP),%EDX

(296) 0x440e14 SUB	%R10D,%R14D

(296) 0x440e17 JMP	440930

0x440e1c NOPL	(%RAX)

0x440e20 VZEROUPPER

0x440e23 LEA	-0x28(%RBP),%RSP

0x440e27 POP	%RBX

0x440e28 POP	%R12

0x440e2a POP	%R13

0x440e2c POP	%R14

0x440e2e POP	%R15

0x440e30 POP	%RBP

0x440e31 RET

0x440e32 NOPW	(%RAX,%RAX,1)

(296) 0x440e38 MOV	0x6c(%RSP),%EDI

(296) 0x440e3c XOR	%R9D,%R9D

(296) 0x440e3f JMP	440ca2

0x440e44 INC	%R14D

0x440e47 XOR	%EDX,%EDX

0x440e49 JMP	4408e0

0x440e4e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
○97.40	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.60	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.33 cycles (5.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.18x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 11.00 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 36 bytes (4 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	72
loop length	216
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.60	8.00	4.33	4.33	6.00	4.40	4.60	6.00	6.00	6.00	4.40	4.33
cycles	4.60	10.13	4.33	4.33	6.00	4.40	4.60	6.00	6.00	6.00	4.40	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.00
Dispatch	10.13
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	7%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (3.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.18x speedup).

ASM code

In the binary file, the address of the function is: 440880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R14D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 440e44 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5c4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R14D,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RSI,%RDX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R14,%R10,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
VMOVSD 0x8(%R12),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%R12),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
SUB %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EDX,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R8D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4408e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x60>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.33 cycles (5.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 11.00 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 36 bytes (4 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	72
loop length	216
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.60	8.00	4.33	4.33	6.00	4.40	4.60	6.00	6.00	6.00	4.40	4.33
cycles	4.60	10.13	4.33	4.33	6.00	4.40	4.60	6.00	6.00	6.00	4.40	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.00
Dispatch	10.13
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	7%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (3.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 440880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R14D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 440e44 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5c4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R14D,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RSI,%RDX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R14,%R10,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 440e23 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
VMOVSD 0x8(%R12),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%R12),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
SUB %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EDX,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R8D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4408e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x60>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]–	0.03	0.01
▼Loop 296 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 297 - initialise_chunk.cpp:80-82 - exec	0.03	0.01

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