OV - exec - Function ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: ideal_gas.cpp:37-45 [...]	Coverage (incl. loops): 4.97% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 37 - 45

--------------------------------------------------------------------------------

37: #pragma omp parallel for simd collapse(2)

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

0x43edd0 PUSH	%RBP

0x43edd1 MOV	%RSP,%RBP

0x43edd4 PUSH	%R15

0x43edd6 PUSH	%R14

0x43edd8 MOV	%RDI,%R14

0x43eddb PUSH	%R13

0x43eddd PUSH	%R12

0x43eddf PUSH	%RBX

0x43ede0 AND	$-0x40,%RSP

0x43ede4 ADD	$-0x80,%RSP

0x43ede8 MOV	0x28(%RDI),%EAX

0x43edeb MOV	0x2c(%RDI),%EDX

0x43edee MOV	0x20(%RDI),%EBX

0x43edf1 ADD	$0x2,%EDX

0x43edf4 LEA	0x1(%RBX),%EDI

0x43edf7 LEA	0x1(%RAX),%R12D

0x43edfb MOV	%EDX,0x48(%RSP)

0x43edff MOV	%EDI,0x44(%RSP)

0x43ee03 MOV	0x24(%R14),%ECX

0x43ee07 CMP	%EDX,%R12D

0x43ee0a JGE	43f3e3

0x43ee10 MOV	%EDX,%EBX

0x43ee12 LEA	0x2(%RCX),%R15D

0x43ee16 SUB	%R12D,%EBX

0x43ee19 CMP	%R15D,%EDI

0x43ee1c JGE	43f3e3

0x43ee22 MOV	%R15D,%ESI

0x43ee25 SUB	%EDI,%ESI

0x43ee27 MOV	%ESI,0x4c(%RSP)

0x43ee2b CALL	404630 <omp_get_num_threads@plt>

0x43ee30 MOV	%EAX,%R13D

0x43ee33 CALL	404520 <omp_get_thread_num@plt>

0x43ee38 MOV	%EAX,%R8D

0x43ee3b MOV	0x4c(%RSP),%EAX

0x43ee3f XOR	%EDX,%EDX

0x43ee41 IMUL	%EBX,%EAX

0x43ee44 DIV	%R13D

0x43ee47 MOV	%EAX,%ESI

0x43ee49 CMP	%EDX,%R8D

0x43ee4c JB	43f401

0x43ee52 IMUL	%ESI,%R8D

0x43ee56 LEA	(%R8,%RDX,1),%R9D

0x43ee5a LEA	(%RSI,%R9,1),%R10D

0x43ee5e MOV	%R10D,0x40(%RSP)

0x43ee63 CMP	%R10D,%R9D

0x43ee66 JAE	43f3e3

0x43ee6c MOV	%R9D,%EAX

0x43ee6f XOR	%EDX,%EDX

0x43ee71 DIVL	0x4c(%RSP)

0x43ee75 MOV	0x8(%R14),%RBX

0x43ee79 MOV	0x10(%R14),%R13

0x43ee7d MOV	0x44(%RSP),%R11D

0x43ee82 VMOVSD	0x3064e(%RIP),%XMM7

0x43ee8a VMOVSD	0x30b36(%RIP),%XMM6

0x43ee92 VMOVSD	0x30b36(%RIP),%XMM5

0x43ee9a MOV	%R13,0x28(%RSP)

0x43ee9f MOV	%RBX,0x30(%RSP)

0x43eea4 MOV	%R15D,%ECX

0x43eea7 MOV	(%R14),%R15

0x43eeaa MOV	0x18(%R14),%R14

0x43eeae MOV	%R15,0x38(%RSP)

0x43eeb3 MOV	%R14,0x20(%RSP)

0x43eeb8 VBROADCASTSD	%XMM7,%YMM10

0x43eebd VBROADCASTSD	%XMM6,%YMM9

0x43eec2 VBROADCASTSD	%XMM5,%YMM8

0x43eec7 VBROADCASTSD	%XMM7,%ZMM4

0x43eecd VBROADCASTSD	%XMM6,%ZMM3

0x43eed3 VBROADCASTSD	%XMM5,%ZMM2

0x43eed9 LEA	(%RDX,%R11,1),%EDI

0x43eedd ADD	%R12D,%EAX

0x43eee0 SUB	%EDI,%ECX

0x43eee2 MOVSXD	%EAX,%RBX

0x43eee5 NOPL	(%RAX)

(290) 0x43eee8 CMP	%ECX,%ESI

(290) 0x43eeea CMOVBE	%ESI,%ECX

(290) 0x43eeed LEA	(%R9,%RCX,1),%R13D

(290) 0x43eef1 CMP	%R13D,%R9D

(290) 0x43eef4 JAE	43f3ba

(290) 0x43eefa MOV	0x38(%RSP),%R12

(290) 0x43eeff MOV	0x20(%RSP),%RAX

(290) 0x43ef04 MOV	0x28(%RSP),%R10

(290) 0x43ef09 MOV	(%R12),%RDX

(290) 0x43ef0d MOV	0x30(%RSP),%RSI

(290) 0x43ef12 MOV	0x10(%R12),%R15

(290) 0x43ef17 MOV	0x10(%RAX),%R12

(290) 0x43ef1b MOV	(%R10),%R11

(290) 0x43ef1e MOV	%R12,0x78(%RSP)

(290) 0x43ef23 MOV	0x10(%RSI),%R14

(290) 0x43ef27 MOV	(%RAX),%R12

(290) 0x43ef2a MOV	(%RSI),%RSI

(290) 0x43ef2d IMUL	%RBX,%RDX

(290) 0x43ef31 IMUL	%RBX,%RSI

(290) 0x43ef35 IMUL	%RBX,%R11

(290) 0x43ef39 IMUL	%RBX,%R12

(290) 0x43ef3d MOV	0x10(%R10),%R8

(290) 0x43ef41 LEA	-0x1(%RCX),%R10D

(290) 0x43ef45 MOV	%RDX,0x50(%RSP)

(290) 0x43ef4a MOV	%RSI,0x58(%RSP)

(290) 0x43ef4f MOV	%R8,0x68(%RSP)

(290) 0x43ef54 MOV	%R11,0x60(%RSP)

(290) 0x43ef59 MOV	%R12,0x70(%RSP)

(290) 0x43ef5e CMP	$0x6,%R10D

(290) 0x43ef62 JBE	43f3f8

(290) 0x43ef68 MOVSXD	%EDI,%RAX

(290) 0x43ef6b ADD	%RAX,%RSI

(290) 0x43ef6e ADD	%RAX,%RDX

(290) 0x43ef71 LEA	(%R14,%RSI,8),%R10

(290) 0x43ef75 LEA	(%R11,%RAX,1),%RSI

(290) 0x43ef79 ADD	%R12,%RAX

(290) 0x43ef7c MOV	%ECX,%R12D

(290) 0x43ef7f MOV	0x78(%RSP),%R11

(290) 0x43ef84 SHR	$0x3,%R12D

(290) 0x43ef88 SAL	$0x6,%R12

(290) 0x43ef8c LEA	(%R8,%RSI,8),%R8

(290) 0x43ef90 LEA	(%R11,%RAX,8),%RSI

(290) 0x43ef94 LEA	-0x40(%R12),%R11

(290) 0x43ef99 SHR	$0x6,%R11

(290) 0x43ef9d INC	%R11

(290) 0x43efa0 LEA	(%R15,%RDX,8),%RDX

(290) 0x43efa4 XOR	%EAX,%EAX

(290) 0x43efa6 AND	$0x3,%R11D

(290) 0x43efaa JE	43f0a6

(290) 0x43efb0 CMP	$0x1,%R11

(290) 0x43efb4 JE	43f052

(290) 0x43efba CMP	$0x2,%R11

(290) 0x43efbe JE	43f007

(290) 0x43efc0 VMOVUPD	(%RDX),%ZMM1

(290) 0x43efc6 MOV	$0x40,%EAX

(290) 0x43efcb VMULPD	(%R10),%ZMM1,%ZMM0

(290) 0x43efd1 VDIVPD	%ZMM1,%ZMM4,%ZMM11

(290) 0x43efd7 VMULPD	%ZMM11,%ZMM11,%ZMM15

(290) 0x43efdd VMULPD	%ZMM3,%ZMM0,%ZMM12

(290) 0x43efe3 VMOVUPD	%ZMM12,(%R8)

(290) 0x43efe9 VMULPD	(%RDX),%ZMM2,%ZMM13

(290) 0x43efef VMULPD	%ZMM12,%ZMM13,%ZMM14

(290) 0x43eff5 VMULPD	%ZMM15,%ZMM14,%ZMM1

(290) 0x43effb VSQRTPD	%ZMM1,%ZMM11

(290) 0x43f001 VMOVUPD	%ZMM11,(%RSI)

(290) 0x43f007 VMOVUPD	(%RDX,%RAX,1),%ZMM0

(290) 0x43f00e VMULPD	(%R10,%RAX,1),%ZMM0,%ZMM13

(290) 0x43f015 VDIVPD	%ZMM0,%ZMM4,%ZMM12

(290) 0x43f01b VMULPD	%ZMM12,%ZMM12,%ZMM11

(290) 0x43f021 VMULPD	%ZMM3,%ZMM13,%ZMM14

(290) 0x43f027 VMOVUPD	%ZMM14,(%R8,%RAX,1)

(290) 0x43f02e VMULPD	(%RDX,%RAX,1),%ZMM2,%ZMM15

(290) 0x43f035 VMULPD	%ZMM14,%ZMM15,%ZMM1

(290) 0x43f03b VMULPD	%ZMM11,%ZMM1,%ZMM0

(290) 0x43f041 VSQRTPD	%ZMM0,%ZMM12

(290) 0x43f047 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(290) 0x43f04e ADD	$0x40,%RAX

(290) 0x43f052 VMOVUPD	(%RDX,%RAX,1),%ZMM13

(290) 0x43f059 VMULPD	(%R10,%RAX,1),%ZMM13,%ZMM15

(290) 0x43f060 VDIVPD	%ZMM13,%ZMM4,%ZMM14

(290) 0x43f066 VMULPD	%ZMM14,%ZMM14,%ZMM12

(290) 0x43f06c VMULPD	%ZMM3,%ZMM15,%ZMM1

(290) 0x43f072 VMOVUPD	%ZMM1,(%R8,%RAX,1)

(290) 0x43f079 VMULPD	(%RDX,%RAX,1),%ZMM2,%ZMM11

(290) 0x43f080 VMULPD	%ZMM1,%ZMM11,%ZMM0

(290) 0x43f086 VMULPD	%ZMM12,%ZMM0,%ZMM13

(290) 0x43f08c VSQRTPD	%ZMM13,%ZMM14

(290) 0x43f092 VMOVUPD	%ZMM14,(%RSI,%RAX,1)

(290) 0x43f099 ADD	$0x40,%RAX

(290) 0x43f09d CMP	%RAX,%R12

(290) 0x43f0a0 JE	43f1e0

  (291) 0x43f0a6 VMOVUPD	(%RDX,%RAX,1),%ZMM15

  (291) 0x43f0ad VMULPD	(%R10,%RAX,1),%ZMM15,%ZMM1

  (291) 0x43f0b4 VDIVPD	%ZMM15,%ZMM4,%ZMM11

  (291) 0x43f0ba VMULPD	%ZMM11,%ZMM11,%ZMM14

  (291) 0x43f0c0 VMULPD	%ZMM3,%ZMM1,%ZMM12

  (291) 0x43f0c6 VMOVUPD	%ZMM12,(%R8,%RAX,1)

  (291) 0x43f0cd VMULPD	(%RDX,%RAX,1),%ZMM2,%ZMM0

  (291) 0x43f0d4 VMULPD	%ZMM12,%ZMM0,%ZMM13

  (291) 0x43f0da VMULPD	%ZMM14,%ZMM13,%ZMM15

  (291) 0x43f0e0 VSQRTPD	%ZMM15,%ZMM11

  (291) 0x43f0e6 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

  (291) 0x43f0ed VMOVUPD	0x40(%RDX,%RAX,1),%ZMM1

  (291) 0x43f0f5 VMULPD	0x40(%R10,%RAX,1),%ZMM1,%ZMM0

  (291) 0x43f0fd VDIVPD	%ZMM1,%ZMM4,%ZMM12

  (291) 0x43f103 VMULPD	%ZMM12,%ZMM12,%ZMM11

  (291) 0x43f109 VMULPD	%ZMM3,%ZMM0,%ZMM13

  (291) 0x43f10f VMOVUPD	%ZMM13,0x40(%R8,%RAX,1)

  (291) 0x43f117 VMULPD	0x40(%RDX,%RAX,1),%ZMM2,%ZMM14

  (291) 0x43f11f VMULPD	%ZMM13,%ZMM14,%ZMM15

  (291) 0x43f125 VMULPD	%ZMM11,%ZMM15,%ZMM1

  (291) 0x43f12b VSQRTPD	%ZMM1,%ZMM12

  (291) 0x43f131 VMOVUPD	%ZMM12,0x40(%RSI,%RAX,1)

  (291) 0x43f139 VMOVUPD	0x80(%RDX,%RAX,1),%ZMM0

  (291) 0x43f141 VMULPD	0x80(%R10,%RAX,1),%ZMM0,%ZMM14

  (291) 0x43f149 VDIVPD	%ZMM0,%ZMM4,%ZMM13

  (291) 0x43f14f VMULPD	%ZMM13,%ZMM13,%ZMM12

  (291) 0x43f155 VMULPD	%ZMM3,%ZMM14,%ZMM15

  (291) 0x43f15b VMOVUPD	%ZMM15,0x80(%R8,%RAX,1)

  (291) 0x43f163 VMULPD	0x80(%RDX,%RAX,1),%ZMM2,%ZMM11

  (291) 0x43f16b VMULPD	%ZMM15,%ZMM11,%ZMM1

  (291) 0x43f171 VMULPD	%ZMM12,%ZMM1,%ZMM0

  (291) 0x43f177 VSQRTPD	%ZMM0,%ZMM13

  (291) 0x43f17d VMOVUPD	%ZMM13,0x80(%RSI,%RAX,1)

  (291) 0x43f185 VMOVUPD	0xc0(%RDX,%RAX,1),%ZMM14

  (291) 0x43f18d VMULPD	0xc0(%R10,%RAX,1),%ZMM14,%ZMM11

  (291) 0x43f195 VDIVPD	%ZMM14,%ZMM4,%ZMM15

  (291) 0x43f19b VMULPD	%ZMM15,%ZMM15,%ZMM13

  (291) 0x43f1a1 VMULPD	%ZMM3,%ZMM11,%ZMM1

  (291) 0x43f1a7 VMOVUPD	%ZMM1,0xc0(%R8,%RAX,1)

  (291) 0x43f1af VMULPD	0xc0(%RDX,%RAX,1),%ZMM2,%ZMM12

  (291) 0x43f1b7 VMULPD	%ZMM1,%ZMM12,%ZMM0

  (291) 0x43f1bd VMULPD	%ZMM13,%ZMM0,%ZMM14

  (291) 0x43f1c3 VSQRTPD	%ZMM14,%ZMM15

  (291) 0x43f1c9 VMOVUPD	%ZMM15,0xc0(%RSI,%RAX,1)

  (291) 0x43f1d1 ADD	$0x100,%RAX

  (291) 0x43f1d7 CMP	%RAX,%R12

  (291) 0x43f1da JNE	43f0a6

(290) 0x43f1e0 MOV	%ECX,%EAX

(290) 0x43f1e2 AND	$-0x8,%EAX

(290) 0x43f1e5 LEA	(%RAX,%RDI,1),%EDX

(290) 0x43f1e8 ADD	%EAX,%R9D

(290) 0x43f1eb TEST	$0x7,%CL

(290) 0x43f1ee JE	43f3b7

(290) 0x43f1f4 SUB	%EAX,%ECX

(290) 0x43f1f6 LEA	-0x1(%RCX),%R10D

(290) 0x43f1fa CMP	$0x2,%R10D

(290) 0x43f1fe JBE	43f290

(290) 0x43f204 MOV	0x50(%RSP),%R8

(290) 0x43f209 MOVSXD	%EDI,%RDI

(290) 0x43f20c ADD	%RDI,%R8

(290) 0x43f20f ADD	%RAX,%R8

(290) 0x43f212 LEA	(%R15,%R8,8),%R12

(290) 0x43f216 VMOVUPD	(%R12),%YMM1

(290) 0x43f21c MOV	0x58(%RSP),%R11

(290) 0x43f221 VDIVPD	%YMM1,%YMM10,%YMM11

(290) 0x43f225 LEA	(%R11,%RDI,1),%R10

(290) 0x43f229 ADD	%RAX,%R10

(290) 0x43f22c VMULPD	(%R14,%R10,8),%YMM1,%YMM12

(290) 0x43f232 MOV	0x70(%RSP),%RSI

(290) 0x43f237 MOV	0x60(%RSP),%R8

(290) 0x43f23c ADD	%RDI,%RSI

(290) 0x43f23f ADD	%R8,%RDI

(290) 0x43f242 VMULPD	%YMM9,%YMM12,%YMM13

(290) 0x43f247 ADD	%RAX,%RDI

(290) 0x43f24a ADD	%RAX,%RSI

(290) 0x43f24d MOV	0x68(%RSP),%RAX

(290) 0x43f252 VMOVUPD	%YMM13,(%RAX,%RDI,8)

(290) 0x43f257 VMULPD	(%R12),%YMM8,%YMM0

(290) 0x43f25d MOV	%ECX,%R12D

(290) 0x43f260 AND	$-0x4,%R12D

(290) 0x43f264 MOV	0x78(%RSP),%RDI

(290) 0x43f269 ADD	%R12D,%EDX

(290) 0x43f26c VMULPD	%YMM13,%YMM0,%YMM14

(290) 0x43f271 ADD	%R12D,%R9D

(290) 0x43f274 AND	$0x3,%ECX

(290) 0x43f277 VMULPD	%YMM11,%YMM11,%YMM15

(290) 0x43f27c VMULPD	%YMM15,%YMM14,%YMM1

(290) 0x43f281 VSQRTPD	%YMM1,%YMM11

(290) 0x43f285 VMOVUPD	%YMM11,(%RDI,%RSI,8)

(290) 0x43f28a JE	43f3b7

(290) 0x43f290 MOV	0x50(%RSP),%RDI

(290) 0x43f295 MOVSXD	%EDX,%RAX

(290) 0x43f298 LEA	(%RDI,%RAX,1),%RCX

(290) 0x43f29c LEA	(%R15,%RCX,8),%R8

(290) 0x43f2a0 VMOVSD	(%R8),%XMM12

(290) 0x43f2a5 MOV	0x58(%RSP),%R10

(290) 0x43f2aa VDIVSD	%XMM12,%XMM7,%XMM13

(290) 0x43f2af LEA	(%R10,%RAX,1),%RSI

(290) 0x43f2b3 VMULSD	(%R14,%RSI,8),%XMM12,%XMM0

(290) 0x43f2b9 MOV	0x60(%RSP),%R11

(290) 0x43f2be MOV	0x68(%RSP),%R12

(290) 0x43f2c3 LEA	(%R11,%RAX,1),%RCX

(290) 0x43f2c7 MOV	0x78(%RSP),%RSI

(290) 0x43f2cc VMULSD	%XMM6,%XMM0,%XMM14

(290) 0x43f2d0 VMOVSD	%XMM14,(%R12,%RCX,8)

(290) 0x43f2d6 VMULSD	(%R8),%XMM5,%XMM15

(290) 0x43f2db MOV	0x70(%RSP),%R8

(290) 0x43f2e0 ADD	%R8,%RAX

(290) 0x43f2e3 VMULSD	%XMM14,%XMM15,%XMM1

(290) 0x43f2e8 VMULSD	%XMM13,%XMM13,%XMM11

(290) 0x43f2ed VMULSD	%XMM11,%XMM1,%XMM12

(290) 0x43f2f2 VSQRTSD	%XMM12,%XMM12,%XMM12

(290) 0x43f2f7 VMOVSD	%XMM12,(%RSI,%RAX,8)

(290) 0x43f2fc LEA	0x1(%R9),%EAX

(290) 0x43f300 CMP	%R13D,%EAX

(290) 0x43f303 JAE	43f3b7

(290) 0x43f309 LEA	0x1(%RDX),%EAX

(290) 0x43f30c CLTQ

(290) 0x43f30e LEA	(%RDI,%RAX,1),%RCX

(290) 0x43f312 LEA	(%R15,%RCX,8),%RCX

(290) 0x43f316 VMOVSD	(%RCX),%XMM13

(290) 0x43f31a LEA	(%R10,%RAX,1),%RSI

(290) 0x43f31e VDIVSD	%XMM13,%XMM7,%XMM14

(290) 0x43f323 VMULSD	(%R14,%RSI,8),%XMM13,%XMM0

(290) 0x43f329 LEA	(%R11,%RAX,1),%RSI

(290) 0x43f32d ADD	%R8,%RAX

(290) 0x43f330 ADD	$0x2,%R9D

(290) 0x43f334 VMULSD	%XMM6,%XMM0,%XMM15

(290) 0x43f338 VMOVSD	%XMM15,(%R12,%RSI,8)

(290) 0x43f33e VMULSD	(%RCX),%XMM5,%XMM1

(290) 0x43f342 MOV	%R8,%RSI

(290) 0x43f345 MOV	0x78(%RSP),%R8

(290) 0x43f34a VMULSD	%XMM15,%XMM1,%XMM12

(290) 0x43f34f VMULSD	%XMM14,%XMM14,%XMM11

(290) 0x43f354 VMULSD	%XMM11,%XMM12,%XMM13

(290) 0x43f359 VSQRTSD	%XMM13,%XMM13,%XMM13

(290) 0x43f35e VMOVSD	%XMM13,(%R8,%RAX,8)

(290) 0x43f364 CMP	%R13D,%R9D

(290) 0x43f367 JAE	43f3b7

(290) 0x43f369 ADD	$0x2,%EDX

(290) 0x43f36c MOVSXD	%EDX,%R9

(290) 0x43f36f ADD	%R9,%RDI

(290) 0x43f372 LEA	(%R15,%RDI,8),%R15

(290) 0x43f376 VMOVSD	(%R15),%XMM14

(290) 0x43f37b ADD	%R9,%R10

(290) 0x43f37e VDIVSD	%XMM14,%XMM7,%XMM15

(290) 0x43f383 VMULSD	(%R14,%R10,8),%XMM14,%XMM0

(290) 0x43f389 ADD	%R9,%R11

(290) 0x43f38c ADD	%R9,%RSI

(290) 0x43f38f VMULSD	%XMM6,%XMM0,%XMM1

(290) 0x43f393 VMOVSD	%XMM1,(%R12,%R11,8)

(290) 0x43f399 VMULSD	(%R15),%XMM5,%XMM12

(290) 0x43f39e VMULSD	%XMM1,%XMM12,%XMM13

(290) 0x43f3a2 VMULSD	%XMM15,%XMM15,%XMM11

(290) 0x43f3a7 VMULSD	%XMM11,%XMM13,%XMM14

(290) 0x43f3ac VSQRTSD	%XMM14,%XMM14,%XMM14

(290) 0x43f3b1 VMOVSD	%XMM14,(%R8,%RSI,8)

(290) 0x43f3b7 MOV	%R13D,%R9D

(290) 0x43f3ba INC	%RBX

(290) 0x43f3bd CMP	%EBX,0x48(%RSP)

(290) 0x43f3c1 JLE	43f3e0

(290) 0x43f3c3 MOV	0x40(%RSP),%ESI

(290) 0x43f3c7 MOV	0x4c(%RSP),%ECX

(290) 0x43f3cb MOV	0x44(%RSP),%EDI

(290) 0x43f3cf SUB	%R9D,%ESI

(290) 0x43f3d2 JMP	43eee8

0x43f3d7 NOPW	(%RAX,%RAX,1)

0x43f3e0 VZEROUPPER

0x43f3e3 LEA	-0x28(%RBP),%RSP

0x43f3e7 POP	%RBX

0x43f3e8 POP	%R12

0x43f3ea POP	%R13

0x43f3ec POP	%R14

0x43f3ee POP	%R15

0x43f3f0 POP	%RBP

0x43f3f1 RET

0x43f3f2 NOPW	(%RAX,%RAX,1)

(290) 0x43f3f8 MOV	%EDI,%EDX

(290) 0x43f3fa XOR	%EAX,%EAX

(290) 0x43f3fc JMP	43f1f4

0x43f401 INC	%ESI

0x43f403 XOR	%EDX,%EDX

0x43f405 JMP	43ee52

0x43f40a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.58	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.42	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 6.00 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.33 to 3.00 cycles (5.44x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.33 to 15.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	88
nb uops	98
loop length	328
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	3
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	8.00	7.00	7.00	8.00	7.20	7.30	8.00	8.00	8.00	7.20	7.00
cycles	7.30	11.73	7.00	7.00	8.00	7.20	7.30	8.00	8.00	8.00	7.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.33
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	16.33

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

2% of peak load performance is reached (5.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 43edd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RBX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x4c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43f401 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x631>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x4c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x8(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x44(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x3064e(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30b36(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30b36(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R11,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43ee52 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 6.00 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.33 to 15.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	88
nb uops	98
loop length	328
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	3
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	8.00	7.00	7.00	8.00	7.20	7.30	8.00	8.00	8.00	7.20	7.00
cycles	7.30	11.73	7.00	7.00	8.00	7.20	7.30	8.00	8.00	8.00	7.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.33
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	16.33

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

2% of peak load performance is reached (5.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 43edd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RBX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x4c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43f401 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x631>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43f3e3 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x4c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x8(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x44(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x3064e(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30b36(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x30b36(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R11,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43ee52 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	4.97	1.43
▼Loop 290 - ideal_gas.cpp:39-45 - exec–	0.00	0.01
○Loop 291 - ideal_gas.cpp:40-45 - exec	4.97	1.43

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code