OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x43ce30 PUSH	%RBP

0x43ce31 MOV	%RSP,%RBP

0x43ce34 PUSH	%R15

0x43ce36 PUSH	%R14

0x43ce38 PUSH	%R13

0x43ce3a PUSH	%R12

0x43ce3c PUSH	%RBX

0x43ce3d AND	$-0x40,%RSP

0x43ce41 SUB	$0xc0,%RSP

0x43ce48 MOV	0x2c(%RDI),%R14D

0x43ce4c MOV	0x28(%RDI),%R15D

0x43ce50 MOV	%R14D,0x64(%RSP)

0x43ce55 MOV	%R15D,0x60(%RSP)

0x43ce5a TEST	%R14D,%R14D

0x43ce5d JLE	43d463

0x43ce63 TEST	%R15D,%R15D

0x43ce66 JLE	43d463

0x43ce6c MOV	%RDI,%RBX

0x43ce6f CALL	404630 <omp_get_num_threads@plt>

0x43ce74 MOV	%EAX,%R12D

0x43ce77 CALL	404520 <omp_get_thread_num@plt>

0x43ce7c MOV	%EAX,%ESI

0x43ce7e MOV	%R14D,%EAX

0x43ce81 IMUL	%R15D,%EAX

0x43ce85 XOR	%EDX,%EDX

0x43ce87 DIV	%R12D

0x43ce8a MOV	%EAX,%ECX

0x43ce8c CMP	%EDX,%ESI

0x43ce8e JB	43d498

0x43ce94 IMUL	%ECX,%ESI

0x43ce97 LEA	(%RSI,%RDX,1),%R12D

0x43ce9b LEA	(%RCX,%R12,1),%EDI

0x43ce9f MOV	%EDI,0x5c(%RSP)

0x43cea3 CMP	%EDI,%R12D

0x43cea6 JAE	43d463

0x43ceac MOV	0x60(%RSP),%R8D

0x43ceb1 MOV	%R12D,%EAX

0x43ceb4 XOR	%EDX,%EDX

0x43ceb6 DIV	%R8D

0x43ceb9 MOV	0x8(%RBX),%R9

0x43cebd MOV	(%RBX),%R10

0x43cec0 MOV	0x10(%RBX),%R11

0x43cec4 MOV	0x18(%RBX),%R13

0x43cec8 MOV	%R9,0x50(%RSP)

0x43cecd MOV	%R10,0x48(%RSP)

0x43ced2 MOV	%R11,0x40(%RSP)

0x43ced7 MOV	%R13,0x38(%RSP)

0x43cedc MOV	0x20(%RBX),%R14

0x43cee0 MOVSXD	%EAX,%R15

0x43cee3 MOV	%R15,0xb0(%RSP)

0x43ceeb SUB	%EDX,%R8D

0x43ceee MOV	%EDX,0x9c(%RSP)

0x43cef5 MOV	%R8D,%EDX

0x43cef8 NOPL	(%RAX,%RAX,1)

(282) 0x43cf00 CMP	%EDX,%ECX

(282) 0x43cf02 CMOVBE	%ECX,%EDX

(282) 0x43cf05 LEA	(%R12,%RDX,1),%ECX

(282) 0x43cf09 MOV	%ECX,0x98(%RSP)

(282) 0x43cf10 CMP	%ECX,%R12D

(282) 0x43cf13 JAE	43d42e

(282) 0x43cf19 MOV	0x50(%RSP),%RBX

(282) 0x43cf1e MOV	0xb8(%R14),%R10

(282) 0x43cf25 MOV	0xb0(%RSP),%R15

(282) 0x43cf2d MOV	%R10,0xa8(%RSP)

(282) 0x43cf35 MOV	0x8(%RBX),%R8

(282) 0x43cf39 MOV	(%R14),%R11

(282) 0x43cf3c MOV	0x30(%R14),%RBX

(282) 0x43cf40 MOV	0xa8(%R14),%R10

(282) 0x43cf47 MOV	0x10(%R14),%RAX

(282) 0x43cf4b MOV	0x38(%RSP),%RCX

(282) 0x43cf50 IMUL	%R15,%RBX

(282) 0x43cf54 IMUL	%R15,%R11

(282) 0x43cf58 IMUL	%R15,%R10

(282) 0x43cf5c MOV	0x48(%RSP),%RSI

(282) 0x43cf61 MOV	0x40(%RSP),%R9

(282) 0x43cf66 IMUL	0xd8(%R14),%R15

(282) 0x43cf6e MOV	%RAX,0xa0(%RSP)

(282) 0x43cf76 MOV	0x40(%R14),%R13

(282) 0x43cf7a MOV	0x8(%RCX),%RAX

(282) 0x43cf7e MOV	0xe8(%R14),%RCX

(282) 0x43cf85 MOV	0x8(%RSI),%RDI

(282) 0x43cf89 MOV	0x8(%R9),%RSI

(282) 0x43cf8d LEA	-0x1(%RDX),%R9D

(282) 0x43cf91 MOV	%R13,0x70(%RSP)

(282) 0x43cf96 MOV	%RBX,0x68(%RSP)

(282) 0x43cf9b MOV	%R11,0x78(%RSP)

(282) 0x43cfa0 MOV	%R10,0x80(%RSP)

(282) 0x43cfa8 MOV	%RAX,0xb8(%RSP)

(282) 0x43cfb0 MOV	%RCX,0x90(%RSP)

(282) 0x43cfb8 MOV	%R15,0x88(%RSP)

(282) 0x43cfc0 CMP	$0x6,%R9D

(282) 0x43cfc4 JBE	43d488

(282) 0x43cfca MOVSXD	0x9c(%RSP),%RAX

(282) 0x43cfd2 LEA	(%RBX,%RAX,1),%RBX

(282) 0x43cfd6 LEA	(%R11,%RAX,1),%R9

(282) 0x43cfda LEA	(%R13,%RBX,8),%RBX

(282) 0x43cfdf LEA	(%R10,%RAX,1),%R13

(282) 0x43cfe3 ADD	%R15,%RAX

(282) 0x43cfe6 MOV	%EDX,%R15D

(282) 0x43cfe9 MOV	0xa8(%RSP),%R10

(282) 0x43cff1 SHR	$0x3,%R15D

(282) 0x43cff5 SAL	$0x6,%R15

(282) 0x43cff9 LEA	(%R10,%R13,8),%R10

(282) 0x43cffd LEA	-0x40(%R15),%R13

(282) 0x43d001 MOV	0xa0(%RSP),%R11

(282) 0x43d009 SHR	$0x6,%R13

(282) 0x43d00d INC	%R13

(282) 0x43d010 LEA	(%R11,%R9,8),%R11

(282) 0x43d014 LEA	(%RCX,%RAX,8),%R9

(282) 0x43d018 XOR	%EAX,%EAX

(282) 0x43d01a AND	$0x3,%R13D

(282) 0x43d01e JE	43d478

(282) 0x43d024 CMP	$0x1,%R13

(282) 0x43d028 JE	43d0b1

(282) 0x43d02e CMP	$0x2,%R13

(282) 0x43d032 JE	43d071

(282) 0x43d034 VBROADCASTSD	(%R8),%ZMM0

(282) 0x43d03a MOV	0xb8(%RSP),%RAX

(282) 0x43d042 VMOVUPD	%ZMM0,(%RBX)

(282) 0x43d048 VBROADCASTSD	(%RDI),%ZMM1

(282) 0x43d04e VMOVUPD	%ZMM1,(%R11)

(282) 0x43d054 VBROADCASTSD	(%RSI),%ZMM2

(282) 0x43d05a VMOVUPD	%ZMM2,(%R10)

(282) 0x43d060 VBROADCASTSD	(%RAX),%ZMM3

(282) 0x43d066 MOV	$0x40,%EAX

(282) 0x43d06b VMOVUPD	%ZMM3,(%R9)

(282) 0x43d071 VBROADCASTSD	(%R8),%ZMM4

(282) 0x43d077 MOV	0xb8(%RSP),%RCX

(282) 0x43d07f VMOVUPD	%ZMM4,(%RBX,%RAX,1)

(282) 0x43d086 VBROADCASTSD	(%RDI),%ZMM5

(282) 0x43d08c VMOVUPD	%ZMM5,(%R11,%RAX,1)

(282) 0x43d093 VBROADCASTSD	(%RSI),%ZMM6

(282) 0x43d099 VMOVUPD	%ZMM6,(%R10,%RAX,1)

(282) 0x43d0a0 VBROADCASTSD	(%RCX),%ZMM7

(282) 0x43d0a6 VMOVUPD	%ZMM7,(%R9,%RAX,1)

(282) 0x43d0ad ADD	$0x40,%RAX

(282) 0x43d0b1 VBROADCASTSD	(%R8),%ZMM8

(282) 0x43d0b7 MOV	0xb8(%RSP),%R13

(282) 0x43d0bf VMOVUPD	%ZMM8,(%RBX,%RAX,1)

(282) 0x43d0c6 VBROADCASTSD	(%RDI),%ZMM9

(282) 0x43d0cc VMOVUPD	%ZMM9,(%R11,%RAX,1)

(282) 0x43d0d3 VBROADCASTSD	(%RSI),%ZMM10

(282) 0x43d0d9 VMOVUPD	%ZMM10,(%R10,%RAX,1)

(282) 0x43d0e0 VBROADCASTSD	(%R13),%ZMM11

(282) 0x43d0e7 VMOVUPD	%ZMM11,(%R9,%RAX,1)

(282) 0x43d0ee ADD	$0x40,%RAX

(282) 0x43d0f2 CMP	%RAX,%R15

(282) 0x43d0f5 JE	43d1f2

  (283) 0x43d0fb VBROADCASTSD	(%R8),%ZMM12

  (283) 0x43d101 VMOVUPD	%ZMM12,(%RBX,%RAX,1)

  (283) 0x43d108 VBROADCASTSD	(%RDI),%ZMM13

  (283) 0x43d10e VMOVUPD	%ZMM13,(%R11,%RAX,1)

  (283) 0x43d115 VBROADCASTSD	(%RSI),%ZMM14

  (283) 0x43d11b VMOVUPD	%ZMM14,(%R10,%RAX,1)

  (283) 0x43d122 VBROADCASTSD	(%R13),%ZMM15

  (283) 0x43d129 VMOVUPD	%ZMM15,(%R9,%RAX,1)

  (283) 0x43d130 VBROADCASTSD	(%R8),%ZMM0

  (283) 0x43d136 VMOVUPD	%ZMM0,0x40(%RBX,%RAX,1)

  (283) 0x43d13e VBROADCASTSD	(%RDI),%ZMM1

  (283) 0x43d144 VMOVUPD	%ZMM1,0x40(%R11,%RAX,1)

  (283) 0x43d14c VBROADCASTSD	(%RSI),%ZMM2

  (283) 0x43d152 VMOVUPD	%ZMM2,0x40(%R10,%RAX,1)

  (283) 0x43d15a VBROADCASTSD	(%R13),%ZMM3

  (283) 0x43d161 VMOVUPD	%ZMM3,0x40(%R9,%RAX,1)

  (283) 0x43d169 VBROADCASTSD	(%R8),%ZMM4

  (283) 0x43d16f VMOVUPD	%ZMM4,0x80(%RBX,%RAX,1)

  (283) 0x43d177 VBROADCASTSD	(%RDI),%ZMM5

  (283) 0x43d17d VMOVUPD	%ZMM5,0x80(%R11,%RAX,1)

  (283) 0x43d185 VBROADCASTSD	(%RSI),%ZMM6

  (283) 0x43d18b VMOVUPD	%ZMM6,0x80(%R10,%RAX,1)

  (283) 0x43d193 VBROADCASTSD	(%R13),%ZMM7

  (283) 0x43d19a VMOVUPD	%ZMM7,0x80(%R9,%RAX,1)

  (283) 0x43d1a2 VBROADCASTSD	(%R8),%ZMM8

  (283) 0x43d1a8 VMOVUPD	%ZMM8,0xc0(%RBX,%RAX,1)

  (283) 0x43d1b0 VBROADCASTSD	(%RDI),%ZMM9

  (283) 0x43d1b6 VMOVUPD	%ZMM9,0xc0(%R11,%RAX,1)

  (283) 0x43d1be VBROADCASTSD	(%RSI),%ZMM10

  (283) 0x43d1c4 VMOVUPD	%ZMM10,0xc0(%R10,%RAX,1)

  (283) 0x43d1cc VBROADCASTSD	(%R13),%ZMM11

  (283) 0x43d1d3 VMOVUPD	%ZMM11,0xc0(%R9,%RAX,1)

  (283) 0x43d1db ADD	$0x100,%RAX

  (283) 0x43d1e1 CMP	%RAX,%R15

  (283) 0x43d1e4 JNE	43d0fb

(282) 0x43d1ea MOV	%R13,0xb8(%RSP)

(282) 0x43d1f2 MOV	0x9c(%RSP),%EBX

(282) 0x43d1f9 MOV	%EDX,%R13D

(282) 0x43d1fc AND	$-0x8,%R13D

(282) 0x43d200 LEA	(%R13,%RBX,1),%R10D

(282) 0x43d205 ADD	%R13D,%R12D

(282) 0x43d208 TEST	$0x7,%DL

(282) 0x43d20b JE	43d426

(282) 0x43d211 SUB	%R13D,%EDX

(282) 0x43d214 LEA	-0x1(%RDX),%R11D

(282) 0x43d218 CMP	$0x2,%R11D

(282) 0x43d21c JBE	43d2d3

(282) 0x43d222 MOVSXD	0x9c(%RSP),%R9

(282) 0x43d22a MOV	0xb8(%RSP),%R15

(282) 0x43d232 MOV	0x68(%RSP),%RAX

(282) 0x43d237 MOV	0x78(%RSP),%R11

(282) 0x43d23c VMOVSD	(%RDI),%XMM12

(282) 0x43d240 VMOVSD	(%R15),%XMM14

(282) 0x43d245 VBROADCASTSD	(%R8),%YMM15

(282) 0x43d24a LEA	(%RAX,%R9,1),%RCX

(282) 0x43d24e LEA	(%R11,%R9,1),%R15

(282) 0x43d252 MOV	0x70(%RSP),%RBX

(282) 0x43d257 MOV	0xa0(%RSP),%RAX

(282) 0x43d25f ADD	%R13,%RCX

(282) 0x43d262 ADD	%R13,%R15

(282) 0x43d265 VBROADCASTSD	%XMM12,%YMM0

(282) 0x43d26a VMOVSD	(%RSI),%XMM13

(282) 0x43d26e VMOVUPD	%YMM15,(%RBX,%RCX,8)

(282) 0x43d273 VMOVUPD	%YMM0,(%RAX,%R15,8)

(282) 0x43d279 MOV	0x80(%RSP),%RCX

(282) 0x43d281 MOV	0x88(%RSP),%R15

(282) 0x43d289 LEA	(%RCX,%R9,1),%R11

(282) 0x43d28d ADD	%R15,%R9

(282) 0x43d290 ADD	%R13,%R9

(282) 0x43d293 ADD	%R13,%R11

(282) 0x43d296 MOV	0xa8(%RSP),%RBX

(282) 0x43d29e MOV	0x90(%RSP),%R13

(282) 0x43d2a6 VBROADCASTSD	%XMM13,%YMM1

(282) 0x43d2ab VBROADCASTSD	%XMM14,%YMM2

(282) 0x43d2b0 VMOVUPD	%YMM1,(%RBX,%R11,8)

(282) 0x43d2b6 VMOVUPD	%YMM2,(%R13,%R9,8)

(282) 0x43d2bd MOV	%EDX,%R9D

(282) 0x43d2c0 AND	$-0x4,%R9D

(282) 0x43d2c4 ADD	%R9D,%R10D

(282) 0x43d2c7 ADD	%R9D,%R12D

(282) 0x43d2ca AND	$0x3,%EDX

(282) 0x43d2cd JE	43d426

(282) 0x43d2d3 MOV	0x68(%RSP),%RBX

(282) 0x43d2d8 VMOVSD	(%R8),%XMM3

(282) 0x43d2dd MOVSXD	%R10D,%RAX

(282) 0x43d2e0 MOV	0x70(%RSP),%R13

(282) 0x43d2e5 LEA	(%RBX,%RAX,1),%RDX

(282) 0x43d2e9 VMOVSD	%XMM3,(%R13,%RDX,8)

(282) 0x43d2f0 MOV	0x78(%RSP),%R9

(282) 0x43d2f5 VMOVSD	(%RDI),%XMM4

(282) 0x43d2f9 MOV	0xa0(%RSP),%R11

(282) 0x43d301 LEA	(%R9,%RAX,1),%RCX

(282) 0x43d305 VMOVSD	%XMM4,(%R11,%RCX,8)

(282) 0x43d30b MOV	0x80(%RSP),%R15

(282) 0x43d313 VMOVSD	(%RSI),%XMM5

(282) 0x43d317 MOV	0xa8(%RSP),%RCX

(282) 0x43d31f LEA	(%R15,%RAX,1),%RDX

(282) 0x43d323 MOV	0xb8(%RSP),%R11

(282) 0x43d32b VMOVSD	%XMM5,(%RCX,%RDX,8)

(282) 0x43d330 VMOVSD	(%R11),%XMM6

(282) 0x43d335 MOV	0x88(%RSP),%R11

(282) 0x43d33d MOV	0x90(%RSP),%RDX

(282) 0x43d345 ADD	%R11,%RAX

(282) 0x43d348 MOV	0x98(%RSP),%ECX

(282) 0x43d34f VMOVSD	%XMM6,(%RDX,%RAX,8)

(282) 0x43d354 LEA	0x1(%R12),%EAX

(282) 0x43d359 CMP	%ECX,%EAX

(282) 0x43d35b JAE	43d426

(282) 0x43d361 LEA	0x1(%R10),%EAX

(282) 0x43d365 VMOVSD	(%R8),%XMM7

(282) 0x43d36a CLTQ

(282) 0x43d36c LEA	(%RBX,%RAX,1),%RDX

(282) 0x43d370 VMOVSD	%XMM7,(%R13,%RDX,8)

(282) 0x43d377 VMOVSD	(%RDI),%XMM8

(282) 0x43d37b MOV	0xa0(%RSP),%RCX

(282) 0x43d383 LEA	(%R9,%RAX,1),%RDX

(282) 0x43d387 VMOVSD	%XMM8,(%RCX,%RDX,8)

(282) 0x43d38c VMOVSD	(%RSI),%XMM9

(282) 0x43d390 MOV	0xa8(%RSP),%RCX

(282) 0x43d398 LEA	(%R15,%RAX,1),%RDX

(282) 0x43d39c VMOVSD	%XMM9,(%RCX,%RDX,8)

(282) 0x43d3a1 MOV	0xb8(%RSP),%RDX

(282) 0x43d3a9 ADD	%R11,%RAX

(282) 0x43d3ac VMOVSD	(%RDX),%XMM10

(282) 0x43d3b0 MOV	%R11,%RDX

(282) 0x43d3b3 MOV	0x90(%RSP),%R11

(282) 0x43d3bb ADD	$0x2,%R12D

(282) 0x43d3bf VMOVSD	%XMM10,(%R11,%RAX,8)

(282) 0x43d3c5 MOV	0x98(%RSP),%EAX

(282) 0x43d3cc CMP	%EAX,%R12D

(282) 0x43d3cf JAE	43d426

(282) 0x43d3d1 ADD	$0x2,%R10D

(282) 0x43d3d5 VMOVSD	(%R8),%XMM11

(282) 0x43d3da MOVSXD	%R10D,%R12

(282) 0x43d3dd ADD	%R12,%RBX

(282) 0x43d3e0 VMOVSD	%XMM11,(%R13,%RBX,8)

(282) 0x43d3e7 VMOVSD	(%RDI),%XMM12

(282) 0x43d3eb MOV	0xa0(%RSP),%R8

(282) 0x43d3f3 ADD	%R12,%R9

(282) 0x43d3f6 VMOVSD	%XMM12,(%R8,%R9,8)

(282) 0x43d3fc VMOVSD	(%RSI),%XMM13

(282) 0x43d400 MOV	0xa8(%RSP),%RDI

(282) 0x43d408 MOV	0xb8(%RSP),%RSI

(282) 0x43d410 ADD	%R12,%R15

(282) 0x43d413 VMOVSD	%XMM13,(%RDI,%R15,8)

(282) 0x43d419 VMOVSD	(%RSI),%XMM14

(282) 0x43d41d ADD	%R12,%RDX

(282) 0x43d420 VMOVSD	%XMM14,(%R11,%RDX,8)

(282) 0x43d426 MOV	0x98(%RSP),%R12D

(282) 0x43d42e INCQ	0xb0(%RSP)

(282) 0x43d436 MOV	0xb0(%RSP),%R10

(282) 0x43d43e CMP	%R10D,0x64(%RSP)

(282) 0x43d443 JLE	43d460

(282) 0x43d445 MOV	0x5c(%RSP),%ECX

(282) 0x43d449 MOVL	$0,0x9c(%RSP)

(282) 0x43d454 MOV	0x60(%RSP),%EDX

(282) 0x43d458 SUB	%R12D,%ECX

(282) 0x43d45b JMP	43cf00

0x43d460 VZEROUPPER

0x43d463 LEA	-0x28(%RBP),%RSP

0x43d467 POP	%RBX

0x43d468 POP	%R12

0x43d46a POP	%R13

0x43d46c POP	%R14

0x43d46e POP	%R15

0x43d470 POP	%RBP

0x43d471 RET

0x43d472 NOPW	(%RAX,%RAX,1)

(282) 0x43d478 MOV	0xb8(%RSP),%R13

(282) 0x43d480 JMP	43d0fb

0x43d485 NOPL	(%RAX)

(282) 0x43d488 MOV	0x9c(%RSP),%R10D

(282) 0x43d490 XOR	%R13D,%R13D

(282) 0x43d493 JMP	43d211

0x43d498 INC	%ECX

0x43d49a XOR	%EDX,%EDX

0x43d49c JMP	43ce94

0x43d4a1 NOPW	%CS:(%RAX,%RAX,1)

0x43d4ac NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.75	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.25	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.17 to 3.00 cycles (4.39x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.17 to 12.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	70
nb uops	79
loop length	259
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.10	8.00	5.00	5.00	8.50	4.07	3.90	8.50	8.50	8.50	3.93	5.00
cycles	4.10	10.33	5.00	5.00	8.50	4.07	3.90	8.50	8.50	8.50	3.93	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.17
Dispatch	10.33
DIV/SQRT	12.00
Overall L1	13.17

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.17 cycles. At this rate:

2% of peak load performance is reached (3.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 43ce30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x2c(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x28(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R14D,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43d498 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x668>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RSI,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R12,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EDI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV 0x8(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R15,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EDX,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43ce94 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x64>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.17 to 12.17 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	70
nb uops	79
loop length	259
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.10	8.00	5.00	5.00	8.50	4.07	3.90	8.50	8.50	8.50	3.93	5.00
cycles	4.10	10.33	5.00	5.00	8.50	4.07	3.90	8.50	8.50	8.50	3.93	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.17
Dispatch	10.33
DIV/SQRT	12.00
Overall L1	13.17

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.17 cycles. At this rate:

2% of peak load performance is reached (3.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 43ce30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0xc0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x2c(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x28(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R14D,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43d498 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x668>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RSI,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R12,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EDI,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43d463 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x633>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV 0x8(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R15,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EDX,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43ce94 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x64>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.04	0.01
▼Loop 282 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 283 - generate_chunk.cpp:77-80 - exec	0.04	0.01

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Expensive FP math instructions/calls

CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code