OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage (incl. loops): 3.92% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x43c200 PUSH	%RBP

0x43c201 MOV	%RSP,%RBP

0x43c204 PUSH	%R15

0x43c206 PUSH	%R14

0x43c208 PUSH	%R13

0x43c20a PUSH	%R12

0x43c20c PUSH	%RBX

0x43c20d MOV	%RDI,%RBX

0x43c210 AND	$-0x40,%RSP

0x43c214 SUB	$0x140,%RSP

0x43c21b MOV	0x50(%RDI),%EAX

0x43c21e MOV	0x54(%RDI),%EDX

0x43c221 MOV	0x48(%RDI),%ECX

0x43c224 ADD	$0x3,%EDX

0x43c227 INC	%ECX

0x43c229 LEA	0x1(%RAX),%R12D

0x43c22d MOV	%EDX,0x80(%RSP)

0x43c234 MOV	%ECX,0x7c(%RSP)

0x43c238 MOV	0x4c(%RDI),%EDI

0x43c23b CMP	%EDX,%R12D

0x43c23e JGE	43cc1b

0x43c244 MOV	%EDX,%R14D

0x43c247 LEA	0x3(%RDI),%R15D

0x43c24b SUB	%R12D,%R14D

0x43c24e CMP	%R15D,%ECX

0x43c251 JGE	43cc1b

0x43c257 MOV	%R15D,%ESI

0x43c25a SUB	%ECX,%ESI

0x43c25c MOV	%ESI,0x84(%RSP)

0x43c263 CALL	404630 <omp_get_num_threads@plt>

0x43c268 MOV	%EAX,%R13D

0x43c26b CALL	404520 <omp_get_thread_num@plt>

0x43c270 MOV	%EAX,%R8D

0x43c273 MOV	0x84(%RSP),%EAX

0x43c27a XOR	%EDX,%EDX

0x43c27c IMUL	%R14D,%EAX

0x43c280 DIV	%R13D

0x43c283 MOV	%EAX,%ECX

0x43c285 CMP	%EDX,%R8D

0x43c288 JB	43cc3f

0x43c28e IMUL	%ECX,%R8D

0x43c292 LEA	(%R8,%RDX,1),%R11D

0x43c296 LEA	(%RCX,%R11,1),%R9D

0x43c29a MOV	%R9D,0x78(%RSP)

0x43c29f CMP	%R9D,%R11D

0x43c2a2 JAE	43cc1b

0x43c2a8 MOV	%R11D,%EAX

0x43c2ab XOR	%EDX,%EDX

0x43c2ad DIVL	0x84(%RSP)

0x43c2b4 VMOVSD	0x334e4(%RIP),%XMM2

0x43c2bc MOV	0x7c(%RSP),%R10D

0x43c2c1 MOV	0x8(%RBX),%RDI

0x43c2c5 MOV	0x28(%RBX),%R14

0x43c2c9 MOV	0x38(%RBX),%RSI

0x43c2cd MOV	0x10(%RBX),%R13

0x43c2d1 MOV	0x20(%RBX),%R8

0x43c2d5 MOV	0x30(%RBX),%R9

0x43c2d9 VMULSD	(%RBX),%XMM2,%XMM5

0x43c2dd MOV	%RDI,0x70(%RSP)

0x43c2e2 MOV	%R14,0x60(%RSP)

0x43c2e7 MOV	%RSI,0x58(%RSP)

0x43c2ec MOV	%R13,0x50(%RSP)

0x43c2f1 MOV	%R8,0x48(%RSP)

0x43c2f6 MOV	%R9,0x40(%RSP)

0x43c2fb VBROADCASTSD	%XMM5,%YMM3

0x43c300 VBROADCASTSD	%XMM5,%ZMM1

0x43c306 ADD	%EDX,%R10D

0x43c309 MOV	%R15D,%EDX

0x43c30c MOV	0x18(%RBX),%R15

0x43c310 MOV	0x40(%RBX),%RBX

0x43c314 ADD	%R12D,%EAX

0x43c317 MOV	%R10D,0xe4(%RSP)

0x43c31f MOV	%RBX,0x38(%RSP)

0x43c324 CLTQ

0x43c326 MOV	%R15,0x68(%RSP)

0x43c32b SUB	%R10D,%EDX

0x43c32e MOV	%R11D,%R15D

0x43c331 MOV	%RAX,%R11

0x43c334 NOPL	(%RAX)

(279) 0x43c338 CMP	%EDX,%ECX

(279) 0x43c33a CMOVBE	%ECX,%EDX

(279) 0x43c33d LEA	(%R15,%RDX,1),%R12D

(279) 0x43c341 MOV	%EDX,0x128(%RSP)

(279) 0x43c348 MOV	%R12D,0xe0(%RSP)

(279) 0x43c350 CMP	%R12D,%R15D

(279) 0x43c353 JAE	43cbe4

(279) 0x43c359 MOV	0x60(%RSP),%R13

(279) 0x43c35e MOV	0x70(%RSP),%RCX

(279) 0x43c363 MOV	(%R13),%R8

(279) 0x43c367 MOV	0x68(%RSP),%R10

(279) 0x43c36c MOV	0x10(%RCX),%RDX

(279) 0x43c370 MOV	(%R10),%RSI

(279) 0x43c373 MOV	(%RCX),%RDI

(279) 0x43c376 MOV	%R8,%RCX

(279) 0x43c379 IMUL	%R11,%RCX

(279) 0x43c37d MOV	%RSI,%RBX

(279) 0x43c380 IMUL	%R11,%RBX

(279) 0x43c384 LEA	(%R8,%RCX,1),%R9

(279) 0x43c388 MOV	0x58(%RSP),%RAX

(279) 0x43c38d MOV	%RDX,0xe8(%RSP)

(279) 0x43c395 MOV	%R9,0xf8(%RSP)

(279) 0x43c39d MOV	0x50(%RSP),%RDX

(279) 0x43c3a2 MOV	0x48(%RSP),%R9

(279) 0x43c3a7 ADD	%RBX,%RSI

(279) 0x43c3aa MOV	0x10(%RAX),%R12

(279) 0x43c3ae MOV	(%RDX),%R8

(279) 0x43c3b1 MOV	%RSI,0xf0(%RSP)

(279) 0x43c3b9 MOV	(%RAX),%RSI

(279) 0x43c3bc MOV	0x10(%R9),%RAX

(279) 0x43c3c0 MOV	(%R9),%R9

(279) 0x43c3c3 IMUL	%R11,%RDI

(279) 0x43c3c7 IMUL	%R11,%RSI

(279) 0x43c3cb IMUL	%R11,%R8

(279) 0x43c3cf IMUL	%R11,%R9

(279) 0x43c3d3 MOV	0x10(%R10),%R14

(279) 0x43c3d7 MOV	0x10(%R13),%R10

(279) 0x43c3db MOV	0x10(%RDX),%R13

(279) 0x43c3df MOV	%RAX,0x138(%RSP)

(279) 0x43c3e7 MOV	%R13,0x108(%RSP)

(279) 0x43c3ef MOV	%RDI,0xb0(%RSP)

(279) 0x43c3f7 MOV	%R14,0x90(%RSP)

(279) 0x43c3ff MOV	%RBX,0xb8(%RSP)

(279) 0x43c407 MOV	%R10,0x98(%RSP)

(279) 0x43c40f MOV	%RCX,0xc0(%RSP)

(279) 0x43c417 MOV	%R12,0x100(%RSP)

(279) 0x43c41f MOV	%RSI,0xc8(%RSP)

(279) 0x43c427 MOV	%R8,0xd0(%RSP)

(279) 0x43c42f MOV	%R9,0xa0(%RSP)

(279) 0x43c437 MOV	0x40(%RSP),%R12

(279) 0x43c43c MOV	0x38(%RSP),%RAX

(279) 0x43c441 MOV	(%R12),%R13

(279) 0x43c445 MOV	0x10(%R12),%RDX

(279) 0x43c44a IMUL	%R11,%R13

(279) 0x43c44e MOV	%RDX,0x130(%RSP)

(279) 0x43c456 MOV	(%RAX),%RDX

(279) 0x43c459 MOV	%R13,0xd8(%RSP)

(279) 0x43c461 IMUL	%R11,%RDX

(279) 0x43c465 MOV	0x128(%RSP),%R13D

(279) 0x43c46d MOV	0x10(%RAX),%R12

(279) 0x43c471 LEA	-0x1(%R13),%EAX

(279) 0x43c475 MOV	%R12,0x110(%RSP)

(279) 0x43c47d MOV	%RDX,0x118(%RSP)

(279) 0x43c485 CMP	$0x6,%EAX

(279) 0x43c488 JBE	43cc30

(279) 0x43c48e MOVSXD	0xe4(%RSP),%RAX

(279) 0x43c496 MOV	0xe8(%RSP),%RDX

(279) 0x43c49e LEA	(%RDI,%RAX,1),%RDI

(279) 0x43c4a2 LEA	(%RDX,%RDI,8),%R13

(279) 0x43c4a6 MOV	0xf0(%RSP),%RDI

(279) 0x43c4ae LEA	(%RBX,%RAX,1),%R12

(279) 0x43c4b2 LEA	(%RDI,%RAX,1),%RDX

(279) 0x43c4b6 MOV	%R14,%RBX

(279) 0x43c4b9 MOV	%R13,0x88(%RSP)

(279) 0x43c4c1 LEA	(%RBX,%RDX,8),%R13

(279) 0x43c4c5 MOV	0xf8(%RSP),%RBX

(279) 0x43c4cd LEA	(%RCX,%RAX,1),%RCX

(279) 0x43c4d1 LEA	(%RBX,%RAX,1),%RDI

(279) 0x43c4d5 LEA	(%R8,%RAX,1),%RDX

(279) 0x43c4d9 LEA	(%R10,%RDI,8),%RBX

(279) 0x43c4dd MOV	0x108(%RSP),%R8

(279) 0x43c4e5 LEA	(%R14,%R12,8),%R14

(279) 0x43c4e9 LEA	(%R10,%RCX,8),%R12

(279) 0x43c4ed LEA	(%RSI,%RAX,1),%R10

(279) 0x43c4f1 MOV	0x100(%RSP),%RSI

(279) 0x43c4f9 LEA	(%R9,%RAX,1),%RDI

(279) 0x43c4fd LEA	(%R8,%RDX,8),%RCX

(279) 0x43c501 LEA	(%RSI,%R10,8),%R10

(279) 0x43c505 MOV	0xd8(%RSP),%RDX

(279) 0x43c50d MOV	0x138(%RSP),%RSI

(279) 0x43c515 SAL	$0x3,%RDI

(279) 0x43c519 LEA	(%RSI,%RDI,1),%R9

(279) 0x43c51d LEA	0x8(%RSI,%RDI,1),%R8

(279) 0x43c522 LEA	(%RDX,%RAX,1),%RDX

(279) 0x43c526 MOV	0x130(%RSP),%RSI

(279) 0x43c52e SAL	$0x3,%RDX

(279) 0x43c532 LEA	(%RSI,%RDX,1),%RDI

(279) 0x43c536 LEA	0x8(%RSI,%RDX,1),%RSI

(279) 0x43c53b MOV	0x118(%RSP),%RDX

(279) 0x43c543 ADD	%RDX,%RAX

(279) 0x43c546 MOV	0x110(%RSP),%RDX

(279) 0x43c54e LEA	(%RDX,%RAX,8),%RDX

(279) 0x43c552 MOV	0x128(%RSP),%EAX

(279) 0x43c559 SHR	$0x3,%EAX

(279) 0x43c55c MOV	%RAX,0xa8(%RSP)

(279) 0x43c564 SAL	$0x6,%RAX

(279) 0x43c568 MOV	%RAX,0x120(%RSP)

(279) 0x43c570 XOR	%EAX,%EAX

(279) 0x43c572 TESTB	$0x1,0xa8(%RSP)

(279) 0x43c57a JE	43c5fa

(279) 0x43c57c VMOVUPD	(%R14),%ZMM0

(279) 0x43c582 VMOVUPD	(%R12),%ZMM4

(279) 0x43c589 MOV	0x88(%RSP),%RAX

(279) 0x43c591 VADDPD	(%R13),%ZMM0,%ZMM6

(279) 0x43c598 VADDPD	(%RBX),%ZMM4,%ZMM7

(279) 0x43c59e VMULPD	(%RAX),%ZMM1,%ZMM9

(279) 0x43c5a4 CMPQ	$0x40,0x120(%RSP)

(279) 0x43c5ad VADDPD	%ZMM7,%ZMM6,%ZMM8

(279) 0x43c5b3 MOV	$0x40,%EAX

(279) 0x43c5b8 VMULPD	%ZMM9,%ZMM8,%ZMM10

(279) 0x43c5be VMOVUPD	%ZMM10,(%R10)

(279) 0x43c5c4 VMOVUPD	(%R9),%ZMM11

(279) 0x43c5ca VMOVUPD	(%RDI),%ZMM13

(279) 0x43c5d0 VADDPD	(%R8),%ZMM11,%ZMM12

(279) 0x43c5d6 VADDPD	(%RSI),%ZMM13,%ZMM14

(279) 0x43c5dc VMULPD	(%RCX),%ZMM1,%ZMM2

(279) 0x43c5e2 VADDPD	%ZMM14,%ZMM12,%ZMM15

(279) 0x43c5e8 VMULPD	%ZMM2,%ZMM15,%ZMM0

(279) 0x43c5ee VMOVUPD	%ZMM0,(%RDX)

(279) 0x43c5f4 JE	43c709

(279) 0x43c5fa MOV	%R15D,0xa8(%RSP)

(279) 0x43c602 MOV	0x88(%RSP),%R15

  (280) 0x43c60a VMOVUPD	(%R14,%RAX,1),%ZMM6

  (280) 0x43c611 VMOVUPD	(%R12,%RAX,1),%ZMM7

  (280) 0x43c618 VADDPD	(%R13,%RAX,1),%ZMM6,%ZMM4

  (280) 0x43c620 VADDPD	(%RBX,%RAX,1),%ZMM7,%ZMM8

  (280) 0x43c627 VMULPD	(%R15,%RAX,1),%ZMM1,%ZMM10

  (280) 0x43c62e VADDPD	%ZMM8,%ZMM4,%ZMM9

  (280) 0x43c634 VMULPD	%ZMM10,%ZMM9,%ZMM11

  (280) 0x43c63a VMOVUPD	%ZMM11,(%R10,%RAX,1)

  (280) 0x43c641 VMOVUPD	(%R9,%RAX,1),%ZMM12

  (280) 0x43c648 VMOVUPD	(%RDI,%RAX,1),%ZMM14

  (280) 0x43c64f VADDPD	(%R8,%RAX,1),%ZMM12,%ZMM13

  (280) 0x43c656 VADDPD	(%RSI,%RAX,1),%ZMM14,%ZMM15

  (280) 0x43c65d VMULPD	(%RCX,%RAX,1),%ZMM1,%ZMM0

  (280) 0x43c664 VADDPD	%ZMM15,%ZMM13,%ZMM2

  (280) 0x43c66a VMULPD	%ZMM0,%ZMM2,%ZMM6

  (280) 0x43c670 VMOVUPD	%ZMM6,(%RDX,%RAX,1)

  (280) 0x43c677 VMOVUPD	0x40(%R14,%RAX,1),%ZMM4

  (280) 0x43c67f VMOVUPD	0x40(%R12,%RAX,1),%ZMM8

  (280) 0x43c687 VADDPD	0x40(%R13,%RAX,1),%ZMM4,%ZMM7

  (280) 0x43c68f VADDPD	0x40(%RBX,%RAX,1),%ZMM8,%ZMM9

  (280) 0x43c697 VMULPD	0x40(%R15,%RAX,1),%ZMM1,%ZMM11

  (280) 0x43c69f VADDPD	%ZMM9,%ZMM7,%ZMM10

  (280) 0x43c6a5 VMULPD	%ZMM11,%ZMM10,%ZMM12

  (280) 0x43c6ab VMOVUPD	%ZMM12,0x40(%R10,%RAX,1)

  (280) 0x43c6b3 VMOVUPD	0x40(%R9,%RAX,1),%ZMM13

  (280) 0x43c6bb VMOVUPD	0x40(%RDI,%RAX,1),%ZMM15

  (280) 0x43c6c3 VADDPD	0x40(%R8,%RAX,1),%ZMM13,%ZMM14

  (280) 0x43c6cb VADDPD	0x40(%RSI,%RAX,1),%ZMM15,%ZMM2

  (280) 0x43c6d3 VMULPD	0x40(%RCX,%RAX,1),%ZMM1,%ZMM6

  (280) 0x43c6db VADDPD	%ZMM2,%ZMM14,%ZMM0

  (280) 0x43c6e1 VMULPD	%ZMM6,%ZMM0,%ZMM4

  (280) 0x43c6e7 VMOVUPD	%ZMM4,0x40(%RDX,%RAX,1)

  (280) 0x43c6ef SUB	$-0x80,%RAX

  (280) 0x43c6f3 CMP	%RAX,0x120(%RSP)

  (280) 0x43c6fb JNE	43c60a

(279) 0x43c701 MOV	0xa8(%RSP),%R15D

(279) 0x43c709 MOV	0x128(%RSP),%R14D

(279) 0x43c711 MOV	0xe4(%RSP),%ECX

(279) 0x43c718 MOV	%R14D,%R12D

(279) 0x43c71b AND	$-0x8,%R12D

(279) 0x43c71f ADD	%R12D,%ECX

(279) 0x43c722 ADD	%R12D,%R15D

(279) 0x43c725 AND	$0x7,%R14D

(279) 0x43c729 JE	43cbdc

(279) 0x43c72f MOV	0x128(%RSP),%R13D

(279) 0x43c737 SUB	%R12D,%R13D

(279) 0x43c73a LEA	-0x1(%R13),%EBX

(279) 0x43c73e CMP	$0x2,%EBX

(279) 0x43c741 JBE	43c893

(279) 0x43c747 MOVSXD	0xe4(%RSP),%R8

(279) 0x43c74f MOV	0xf0(%RSP),%RAX

(279) 0x43c757 MOV	0x90(%RSP),%RBX

(279) 0x43c75f LEA	(%RAX,%R8,1),%R14

(279) 0x43c763 MOV	0xb8(%RSP),%R9

(279) 0x43c76b ADD	%R12,%R14

(279) 0x43c76e VMOVUPD	(%RBX,%R14,8),%YMM7

(279) 0x43c774 LEA	(%R9,%R8,1),%RDX

(279) 0x43c778 ADD	%R12,%RDX

(279) 0x43c77b VADDPD	(%RBX,%RDX,8),%YMM7,%YMM8

(279) 0x43c780 MOV	0xa0(%RSP),%R10

(279) 0x43c788 MOV	0xf8(%RSP),%RDX

(279) 0x43c790 MOV	0x98(%RSP),%R14

(279) 0x43c798 LEA	(%R10,%R8,1),%RSI

(279) 0x43c79c LEA	(%RDX,%R8,1),%RAX

(279) 0x43c7a0 MOV	0xc0(%RSP),%R10

(279) 0x43c7a8 ADD	%R12,%RAX

(279) 0x43c7ab VMOVUPD	(%R14,%RAX,8),%YMM9

(279) 0x43c7b1 LEA	(%R10,%R8,1),%R9

(279) 0x43c7b5 MOV	0xb0(%RSP),%RBX

(279) 0x43c7bd ADD	%R12,%R9

(279) 0x43c7c0 VADDPD	(%R14,%R9,8),%YMM9,%YMM10

(279) 0x43c7c6 LEA	(%RBX,%R8,1),%R10

(279) 0x43c7ca MOV	0xe8(%RSP),%R9

(279) 0x43c7d2 ADD	%R12,%R10

(279) 0x43c7d5 VMULPD	(%R9,%R10,8),%YMM3,%YMM12

(279) 0x43c7db VADDPD	%YMM10,%YMM8,%YMM11

(279) 0x43c7e0 MOV	0xc8(%RSP),%RDX

(279) 0x43c7e8 MOV	0xd8(%RSP),%RDI

(279) 0x43c7f0 LEA	(%RDX,%R8,1),%RAX

(279) 0x43c7f4 VMULPD	%YMM12,%YMM11,%YMM13

(279) 0x43c7f9 MOV	0x100(%RSP),%R14

(279) 0x43c801 ADD	%R8,%RDI

(279) 0x43c804 ADD	%R12,%RAX

(279) 0x43c807 MOV	0x130(%RSP),%RBX

(279) 0x43c80f VMOVUPD	%YMM13,(%R14,%RAX,8)

(279) 0x43c815 ADD	%R12,%RDI

(279) 0x43c818 VMOVUPD	0x8(%RBX,%RDI,8),%YMM14

(279) 0x43c81e VMOVUPD	(%RBX,%RDI,8),%YMM2

(279) 0x43c823 MOV	0x138(%RSP),%R10

(279) 0x43c82b ADD	%R12,%RSI

(279) 0x43c82e VADDPD	0x8(%R10,%RSI,8),%YMM14,%YMM15

(279) 0x43c835 VADDPD	(%R10,%RSI,8),%YMM2,%YMM0

(279) 0x43c83b MOV	0xd0(%RSP),%RSI

(279) 0x43c843 MOV	0x108(%RSP),%RDI

(279) 0x43c84b LEA	(%RSI,%R8,1),%R9

(279) 0x43c84f ADD	%R12,%R9

(279) 0x43c852 VMULPD	(%RDI,%R9,8),%YMM3,%YMM4

(279) 0x43c858 VADDPD	%YMM0,%YMM15,%YMM6

(279) 0x43c85c MOV	0x118(%RSP),%RDX

(279) 0x43c864 ADD	%RDX,%R8

(279) 0x43c867 VMULPD	%YMM4,%YMM6,%YMM7

(279) 0x43c86b ADD	%R12,%R8

(279) 0x43c86e MOV	0x110(%RSP),%R12

(279) 0x43c876 VMOVUPD	%YMM7,(%R12,%R8,8)

(279) 0x43c87c MOV	%R13D,%R8D

(279) 0x43c87f AND	$-0x4,%R8D

(279) 0x43c883 ADD	%R8D,%ECX

(279) 0x43c886 ADD	%R8D,%R15D

(279) 0x43c889 AND	$0x3,%R13D

(279) 0x43c88d JE	43cbdc

(279) 0x43c893 MOV	0xc0(%RSP),%R14

(279) 0x43c89b MOVSXD	%ECX,%RAX

(279) 0x43c89e MOV	0x98(%RSP),%RBX

(279) 0x43c8a6 MOV	0xf0(%RSP),%R9

(279) 0x43c8ae LEA	(%R14,%RAX,1),%R10

(279) 0x43c8b2 MOV	0xc8(%RSP),%R13

(279) 0x43c8ba MOV	0x90(%RSP),%R14

(279) 0x43c8c2 MOV	0xf8(%RSP),%RSI

(279) 0x43c8ca VMOVSD	(%RBX,%R10,8),%XMM8

(279) 0x43c8d0 LEA	(%R9,%RAX,1),%RDI

(279) 0x43c8d4 MOV	0xb8(%RSP),%R12

(279) 0x43c8dc VMOVSD	(%R14,%RDI,8),%XMM10

(279) 0x43c8e2 LEA	(%R13,%RAX,1),%RDX

(279) 0x43c8e7 ADD	%RAX,%RSI

(279) 0x43c8ea MOV	0xb0(%RSP),%R13

(279) 0x43c8f2 VADDSD	(%RBX,%RSI,8),%XMM8,%XMM9

(279) 0x43c8f7 LEA	(%R12,%RAX,1),%R8

(279) 0x43c8fb MOV	0xe8(%RSP),%RSI

(279) 0x43c903 VADDSD	(%R14,%R8,8),%XMM10,%XMM11

(279) 0x43c909 LEA	(%R13,%RAX,1),%R10

(279) 0x43c90e VMULSD	(%RSI,%R10,8),%XMM5,%XMM13

(279) 0x43c914 VADDSD	%XMM11,%XMM9,%XMM12

(279) 0x43c919 MOV	0x100(%RSP),%R9

(279) 0x43c921 MOV	0xa0(%RSP),%R12

(279) 0x43c929 MOV	0x138(%RSP),%RDI

(279) 0x43c931 VMULSD	%XMM13,%XMM12,%XMM14

(279) 0x43c936 MOV	0x130(%RSP),%R10

(279) 0x43c93e VMOVSD	%XMM14,(%R9,%RDX,8)

(279) 0x43c944 LEA	0x1(%RCX),%EDX

(279) 0x43c947 MOVSXD	%EDX,%RDX

(279) 0x43c94a LEA	(%RDX,%R12,1),%R8

(279) 0x43c94e LEA	(%RDI,%R8,8),%R13

(279) 0x43c952 MOV	%R13,0x128(%RSP)

(279) 0x43c95a MOV	0xd8(%RSP),%R13

(279) 0x43c962 MOV	0x118(%RSP),%R9

(279) 0x43c96a LEA	(%R13,%RDX,1),%RSI

(279) 0x43c96f LEA	(%R10,%RSI,8),%RSI

(279) 0x43c973 LEA	(%R12,%RAX,1),%R10

(279) 0x43c977 VMOVSD	(%RDI,%R10,8),%XMM15

(279) 0x43c97d MOV	0x130(%RSP),%R10

(279) 0x43c985 LEA	(%R9,%RAX,1),%R8

(279) 0x43c989 MOV	0x128(%RSP),%RDI

(279) 0x43c991 LEA	(%R13,%RAX,1),%R9

(279) 0x43c996 VMOVSD	(%RSI),%XMM0

(279) 0x43c99a VADDSD	(%R10,%R9,8),%XMM15,%XMM2

(279) 0x43c9a0 MOV	0xd0(%RSP),%R9

(279) 0x43c9a8 VADDSD	(%RDI),%XMM0,%XMM6

(279) 0x43c9ac MOV	0x108(%RSP),%RDI

(279) 0x43c9b4 ADD	%R9,%RAX

(279) 0x43c9b7 VMULSD	(%RDI,%RAX,8),%XMM5,%XMM4

(279) 0x43c9bc VADDSD	%XMM6,%XMM2,%XMM7

(279) 0x43c9c0 MOV	0x110(%RSP),%RAX

(279) 0x43c9c8 LEA	0x1(%R15),%R9D

(279) 0x43c9cc VMULSD	%XMM4,%XMM7,%XMM8

(279) 0x43c9d0 VMOVSD	%XMM8,(%RAX,%R8,8)

(279) 0x43c9d6 MOV	0xe0(%RSP),%R8D

(279) 0x43c9de CMP	%R8D,%R9D

(279) 0x43c9e1 JAE	43cbdc

(279) 0x43c9e7 MOV	0xf0(%RSP),%RDI

(279) 0x43c9ef MOV	0xb8(%RSP),%R8

(279) 0x43c9f7 LEA	(%RDX,%RDI,1),%R9

(279) 0x43c9fb MOV	0xf8(%RSP),%RDI

(279) 0x43ca03 VMOVSD	(%R14,%R9,8),%XMM9

(279) 0x43ca09 ADD	%RDX,%R8

(279) 0x43ca0c ADD	%RDX,%RDI

(279) 0x43ca0f MOV	0xc0(%RSP),%R9

(279) 0x43ca17 VADDSD	(%R14,%R8,8),%XMM9,%XMM10

(279) 0x43ca1d VMOVSD	(%RBX,%RDI,8),%XMM11

(279) 0x43ca22 MOV	0xb0(%RSP),%R8

(279) 0x43ca2a ADD	%RDX,%R9

(279) 0x43ca2d MOV	0xe8(%RSP),%RDI

(279) 0x43ca35 VADDSD	(%RBX,%R9,8),%XMM11,%XMM12

(279) 0x43ca3b LEA	(%RDX,%R8,1),%R9

(279) 0x43ca3f VMULSD	(%RDI,%R9,8),%XMM5,%XMM14

(279) 0x43ca45 VADDSD	%XMM12,%XMM10,%XMM13

(279) 0x43ca4a MOV	0xc8(%RSP),%RAX

(279) 0x43ca52 MOV	0x100(%RSP),%R8

(279) 0x43ca5a ADD	%RDX,%RAX

(279) 0x43ca5d VMULSD	%XMM14,%XMM13,%XMM15

(279) 0x43ca62 MOV	0x138(%RSP),%RDI

(279) 0x43ca6a VMOVSD	%XMM15,(%R8,%RAX,8)

(279) 0x43ca70 LEA	0x2(%RCX),%EAX

(279) 0x43ca73 CLTQ

(279) 0x43ca75 LEA	(%R13,%RAX,1),%R8

(279) 0x43ca7a LEA	(%R10,%R8,8),%R8

(279) 0x43ca7e LEA	(%R12,%RAX,1),%R9

(279) 0x43ca82 VMOVSD	(%R8),%XMM6

(279) 0x43ca87 LEA	(%RDI,%R9,8),%R9

(279) 0x43ca8b VMOVSD	(%R9),%XMM2

(279) 0x43ca90 MOV	0x128(%RSP),%RDI

(279) 0x43ca98 VADDSD	(%RSI),%XMM6,%XMM7

(279) 0x43ca9c MOV	0x118(%RSP),%R10

(279) 0x43caa4 MOV	0xd0(%RSP),%RSI

(279) 0x43caac VADDSD	(%RDI),%XMM2,%XMM0

(279) 0x43cab0 MOV	0x108(%RSP),%RDI

(279) 0x43cab8 LEA	(%R10,%RDX,1),%R10

(279) 0x43cabc ADD	%RSI,%RDX

(279) 0x43cabf VMULSD	(%RDI,%RDX,8),%XMM5,%XMM4

(279) 0x43cac4 VADDSD	%XMM7,%XMM0,%XMM8

(279) 0x43cac8 MOV	0x110(%RSP),%RDX

(279) 0x43cad0 VMULSD	%XMM4,%XMM8,%XMM9

(279) 0x43cad4 VMOVSD	%XMM9,(%RDX,%R10,8)

(279) 0x43cada LEA	0x2(%R15),%R10D

(279) 0x43cade MOV	0xe0(%RSP),%R15D

(279) 0x43cae6 CMP	%R15D,%R10D

(279) 0x43cae9 JAE	43cbdc

(279) 0x43caef MOV	0xb8(%RSP),%RDI

(279) 0x43caf7 MOV	0xf0(%RSP),%RSI

(279) 0x43caff ADD	%RAX,%RDI

(279) 0x43cb02 VMOVSD	(%R14,%RDI,8),%XMM10

(279) 0x43cb08 MOV	0xc0(%RSP),%RDI

(279) 0x43cb10 ADD	%RAX,%RSI

(279) 0x43cb13 VADDSD	(%R14,%RSI,8),%XMM10,%XMM11

(279) 0x43cb19 ADD	%RAX,%RDI

(279) 0x43cb1c MOV	0xf8(%RSP),%R14

(279) 0x43cb24 VMOVSD	(%RBX,%RDI,8),%XMM12

(279) 0x43cb29 ADD	%RAX,%R14

(279) 0x43cb2c MOV	0xb0(%RSP),%R10

(279) 0x43cb34 VADDSD	(%RBX,%R14,8),%XMM12,%XMM13

(279) 0x43cb3a MOV	0xe8(%RSP),%RBX

(279) 0x43cb42 ADD	%RAX,%R10

(279) 0x43cb45 VMULSD	(%RBX,%R10,8),%XMM5,%XMM15

(279) 0x43cb4b VADDSD	%XMM13,%XMM11,%XMM14

(279) 0x43cb50 MOV	0xc8(%RSP),%RDX

(279) 0x43cb58 MOV	0x100(%RSP),%R15

(279) 0x43cb60 ADD	$0x3,%ECX

(279) 0x43cb63 VMULSD	%XMM15,%XMM14,%XMM2

(279) 0x43cb68 ADD	%RAX,%RDX

(279) 0x43cb6b MOVSXD	%ECX,%RCX

(279) 0x43cb6e MOV	0x138(%RSP),%RSI

(279) 0x43cb76 ADD	%RCX,%R12

(279) 0x43cb79 VMOVSD	%XMM2,(%R15,%RDX,8)

(279) 0x43cb7f VMOVSD	(%RSI,%R12,8),%XMM0

(279) 0x43cb85 ADD	%RCX,%R13

(279) 0x43cb88 VADDSD	(%R9),%XMM0,%XMM6

(279) 0x43cb8d MOV	0x130(%RSP),%R9

(279) 0x43cb95 MOV	0x108(%RSP),%RDI

(279) 0x43cb9d VMOVSD	(%R9,%R13,8),%XMM7

(279) 0x43cba3 MOV	0x118(%RSP),%RDX

(279) 0x43cbab VADDSD	(%R8),%XMM7,%XMM8

(279) 0x43cbb0 MOV	0xd0(%RSP),%R8

(279) 0x43cbb8 MOV	0x110(%RSP),%R14

(279) 0x43cbc0 ADD	%RAX,%R8

(279) 0x43cbc3 VMULSD	(%RDI,%R8,8),%XMM5,%XMM9

(279) 0x43cbc9 VADDSD	%XMM8,%XMM6,%XMM4

(279) 0x43cbce ADD	%RAX,%RDX

(279) 0x43cbd1 VMULSD	%XMM9,%XMM4,%XMM10

(279) 0x43cbd6 VMOVSD	%XMM10,(%R14,%RDX,8)

(279) 0x43cbdc MOV	0xe0(%RSP),%R15D

(279) 0x43cbe4 INC	%R11

(279) 0x43cbe7 CMP	%R11D,0x80(%RSP)

(279) 0x43cbef JLE	43cc18

(279) 0x43cbf1 MOV	0x78(%RSP),%ECX

(279) 0x43cbf5 MOV	0x7c(%RSP),%R10D

(279) 0x43cbfa MOV	0x84(%RSP),%EDX

(279) 0x43cc01 MOV	%R10D,0xe4(%RSP)

(279) 0x43cc09 SUB	%R15D,%ECX

(279) 0x43cc0c JMP	43c338

0x43cc11 NOPL	(%RAX)

0x43cc18 VZEROUPPER

0x43cc1b LEA	-0x28(%RBP),%RSP

0x43cc1f POP	%RBX

0x43cc20 POP	%R12

0x43cc22 POP	%R13

0x43cc24 POP	%R14

0x43cc26 POP	%R15

0x43cc28 POP	%RBP

0x43cc29 RET

0x43cc2a NOPW	(%RAX,%RAX,1)

(279) 0x43cc30 MOV	0xe4(%RSP),%ECX

(279) 0x43cc37 XOR	%R12D,%R12D

(279) 0x43cc3a JMP	43c72f

0x43cc3f INC	%ECX

0x43cc41 XOR	%EDX,%EDX

0x43cc43 JMP	43c28e

0x43cc48 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.66	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.34	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.33 to 2.33 cycles (7.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.33 to 3.00 cycles (5.78x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.33 to 16.17 cycles (1.07x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:40

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	104
loop length	360
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	8.00	8.00	8.00	10.50	6.80	6.80	10.50	10.50	10.50	6.60	8.00
cycles	6.80	12.10	8.00	8.00	10.50	6.80	6.80	10.50	10.50	10.50	6.60	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	17.33
Dispatch	12.10
DIV/SQRT	12.00
Overall L1	17.33

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

3% of peak load performance is reached (6.23 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.33 to 12.10 cycles (1.43x speedup).

ASM code

In the binary file, the address of the function is: 43c200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x140,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x54(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x4c(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ECX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x84(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43cc3f <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa3f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R11,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x84(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
VMOVSD 0x334e4(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x7c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RBX),%XMM2,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10D,0xe4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43c28e <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.33 to 2.33 cycles (7.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.33 to 16.17 cycles (1.07x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:40

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	104
loop length	360
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	8.00	8.00	8.00	10.50	6.80	6.80	10.50	10.50	10.50	6.60	8.00
cycles	6.80	12.10	8.00	8.00	10.50	6.80	6.80	10.50	10.50	10.50	6.60	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	17.33
Dispatch	12.10
DIV/SQRT	12.00
Overall L1	17.33

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

3% of peak load performance is reached (6.23 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43c200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x140,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x54(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x4c(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ECX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x84(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 43cc3f <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa3f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R11,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43cc1b <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xa1b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x84(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
VMOVSD 0x334e4(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x7c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RBX),%XMM2,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10D,0xe4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43c28e <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.92	1.13
▼Loop 279 - flux_calc.cpp:38-40 - exec–	0.00	0.01
○Loop 280 - flux_calc.cpp:39-40 - exec	3.92	1.13

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Code clean check

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Expensive FP math instructions/calls

CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code