OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.05% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x438ef0 PUSH	%RBP

0x438ef1 MOV	%RSP,%RBP

0x438ef4 PUSH	%R15

0x438ef6 PUSH	%R14

0x438ef8 PUSH	%R13

0x438efa PUSH	%R12

0x438efc PUSH	%RBX

0x438efd MOV	%RDI,%RBX

0x438f00 AND	$-0x40,%RSP

0x438f04 SUB	$0x6c0,%RSP

0x438f0b MOV	0x80(%RDI),%EAX

0x438f11 MOV	0x84(%RDI),%ECX

0x438f17 MOV	0x78(%RDI),%EDX

0x438f1a ADD	$0x2,%ECX

0x438f1d INC	%EDX

0x438f1f LEA	0x1(%RAX),%R12D

0x438f23 MOV	%ECX,0x34(%RSP)

0x438f27 MOV	%EDX,0x30(%RSP)

0x438f2b MOV	0x7c(%RDI),%ESI

0x438f2e CMP	%ECX,%R12D

0x438f31 JGE	439ea8

0x438f37 MOV	0x30(%RSP),%EDI

0x438f3b MOV	%ECX,%R14D

0x438f3e LEA	0x2(%RSI),%R15D

0x438f42 SUB	%R12D,%R14D

0x438f45 CMP	%R15D,%EDI

0x438f48 JGE	439ea8

0x438f4e MOV	%R15D,%R8D

0x438f51 SUB	%EDI,%R8D

0x438f54 MOV	%R8D,0x2c(%RSP)

0x438f59 CALL	404630 <omp_get_num_threads@plt>

0x438f5e MOV	%EAX,%R13D

0x438f61 CALL	404520 <omp_get_thread_num@plt>

0x438f66 MOV	%EAX,%R9D

0x438f69 MOV	0x2c(%RSP),%EAX

0x438f6d XOR	%EDX,%EDX

0x438f6f IMUL	%R14D,%EAX

0x438f73 DIV	%R13D

0x438f76 MOV	%EAX,%ECX

0x438f78 CMP	%EDX,%R9D

0x438f7b JB	439e9f

0x438f81 IMUL	%ECX,%R9D

0x438f85 VMOVSD	0x36943(%RIP),%XMM15

0x438f8d LEA	(%R9,%RDX,1),%EAX

0x438f91 LEA	(%RCX,%RAX,1),%R10D

0x438f95 MOV	%EAX,0xbc(%RSP)

0x438f9c MOV	%R10D,0x28(%RSP)

0x438fa1 CMP	%R10D,%EAX

0x438fa4 JAE	439e11

0x438faa XOR	%EDX,%EDX

0x438fac DIVL	0x2c(%RSP)

0x438fb0 MOV	0x30(%RSP),%R11D

0x438fb5 MOV	0x30(%RBX),%RSI

0x438fb9 VBROADCASTSD	0x3690d(%RIP),%ZMM3

0x438fc3 MOV	%RSI,0xa0(%RSP)

0x438fcb VMOVSD	0x8(%RBX),%XMM1

0x438fd0 MOV	0x58(%RBX),%R14

0x438fd4 MOV	0x50(%RBX),%RDI

0x438fd8 MOV	0x48(%RBX),%R8

0x438fdc MOV	0x60(%RBX),%R13

0x438fe0 MOV	0x20(%RBX),%R9

0x438fe4 MOV	0x40(%RBX),%R10

0x438fe8 MOV	0x28(%RBX),%RSI

0x438fec VMOVSD	0x10(%RBX),%XMM2

0x438ff1 VMOVSD	(%RBX),%XMM0

0x438ff5 VMOVAPD	%ZMM3,0x640(%RSP)

0x438ffd VMOVAPD	%ZMM3,0x680(%RSP)

0x439005 MOV	%R14,0x90(%RSP)

0x43900d MOV	%RDI,0x88(%RSP)

0x439015 MOV	%R8,0x80(%RSP)

0x43901d MOV	%R13,0x78(%RSP)

0x439022 MOV	%R9,0x70(%RSP)

0x439027 MOV	%R10,0x68(%RSP)

0x43902c ADD	%EDX,%R11D

0x43902f MOV	%R15D,%EDX

0x439032 MOV	%R11D,0xb8(%RSP)

0x43903a SUB	%R11D,%EDX

0x43903d MOV	0x68(%RBX),%R11

0x439041 ADD	%R12D,%EAX

0x439044 MOV	0x38(%RBX),%R15

0x439048 MOV	%R11,0x60(%RSP)

0x43904d MOVSXD	%EAX,%R11

0x439050 LEA	0x1(%R11),%R12

0x439054 MOV	%R15,0x98(%RSP)

0x43905c MOV	%RSI,0x58(%RSP)

0x439061 MOV	%R12,0xa8(%RSP)

0x439069 VMOVSD	0x18(%RBX),%XMM4

0x43906e MOV	$0x10,%EAX

0x439073 MOV	%R12,0xb0(%RSP)

0x43907b MOV	$0x1,%R15D

0x439081 VADDSD	%XMM1,%XMM1,%XMM1

0x439085 MOV	%RBX,0x20(%RSP)

0x43908a VPBROADCASTD	%EAX,%ZMM6

0x439090 VPBROADCASTD	%R15D,%ZMM5

0x439096 VADDSD	%XMM2,%XMM2,%XMM3

0x43909a VMOVDQA32	%ZMM6,0x100(%RSP)

0x4390a2 VMOVDQA32	%ZMM5,0xc0(%RSP)

0x4390aa VMOVAPD	%XMM0,%XMM2

0x4390ae XCHG	%AX,%AX

(257) 0x4390b0 CMP	%EDX,%ECX

(257) 0x4390b2 MOV	%EDX,%R14D

(257) 0x4390b5 CMOVBE	%ECX,%R14D

(257) 0x4390b9 MOV	0xbc(%RSP),%EBX

(257) 0x4390c0 LEA	(%RBX,%R14,1),%R15D

(257) 0x4390c4 CMP	%R15D,%EBX

(257) 0x4390c7 JAE	439e51

(257) 0x4390cd LEA	-0x1(%R14),%ECX

(257) 0x4390d1 LEA	(,%R11,8),%RDX

(257) 0x4390d9 CMP	$0xe,%ECX

(257) 0x4390dc JBE	439ada

(257) 0x4390e2 MOV	0x90(%RSP),%R9

(257) 0x4390ea MOV	0x88(%RSP),%RSI

(257) 0x4390f2 MOV	0x80(%RSP),%RAX

(257) 0x4390fa MOV	0x78(%RSP),%RCX

(257) 0x4390ff MOV	0x98(%RSP),%R8

(257) 0x439107 MOV	(%R9),%R10

(257) 0x43910a MOV	(%RSI),%R12

(257) 0x43910d MOV	(%RAX),%RBX

(257) 0x439110 VPBROADCASTQ	0x8(%R8),%ZMM13

(257) 0x439117 MOV	0xa0(%RSP),%RDI

(257) 0x43911f MOV	(%RCX),%R8

(257) 0x439122 IMUL	%R11,%R10

(257) 0x439126 IMUL	%R11,%R12

(257) 0x43912a IMUL	%R11,%RBX

(257) 0x43912e VPBROADCASTQ	0x8(%RDI),%ZMM12

(257) 0x439135 VPBROADCASTD	0xb8(%RSP),%ZMM7

(257) 0x43913d MOV	%R8,%RDI

(257) 0x439140 VPBROADCASTQ	0x10(%R9),%ZMM14

(257) 0x439147 VPBROADCASTQ	0x10(%RSI),%ZMM0

(257) 0x43914e VPBROADCASTQ	0x10(%RAX),%ZMM5

(257) 0x439155 IMUL	%R11,%RDI

(257) 0x439159 VPBROADCASTQ	%R10,%ZMM15

(257) 0x43915f MOV	0x70(%RSP),%R10

(257) 0x439164 VPADDD	0x36792(%RIP),%ZMM7,%ZMM28

(257) 0x43916e VBROADCASTSD	%XMM2,%ZMM8

(257) 0x439174 VBROADCASTSD	%XMM1,%ZMM9

(257) 0x43917a VBROADCASTSD	%XMM3,%ZMM10

(257) 0x439180 VBROADCASTSD	%XMM4,%ZMM11

(257) 0x439186 VPBROADCASTQ	%R12,%ZMM6

(257) 0x43918c VPBROADCASTQ	%RBX,%ZMM7

(257) 0x439192 MOV	0xb0(%RSP),%R9

(257) 0x43919a VMOVAPD	%ZMM8,0x300(%RSP)

(257) 0x4391a2 VMOVAPD	%ZMM9,0x240(%RSP)

(257) 0x4391aa VMOVAPD	%ZMM10,0x180(%RSP)

(257) 0x4391b2 VMOVAPD	%ZMM11,0x140(%RSP)

(257) 0x4391ba VMOVDQA64	%ZMM12,0x500(%RSP)

(257) 0x4391c2 VMOVDQA64	%ZMM13,0x4c0(%RSP)

(257) 0x4391ca VPBROADCASTQ	0x10(%RCX),%ZMM12

(257) 0x4391d1 VMOVDQA64	%ZMM14,0x480(%RSP)

(257) 0x4391d9 VMOVDQA64	%ZMM15,0x440(%RSP)

(257) 0x4391e1 VMOVDQA64	%ZMM0,0x400(%RSP)

(257) 0x4391e9 VMOVDQA64	%ZMM6,0x3c0(%RSP)

(257) 0x4391f1 VMOVDQA64	%ZMM5,0x380(%RSP)

(257) 0x4391f9 VMOVDQA64	%ZMM7,0x340(%RSP)

(257) 0x439201 VPBROADCASTQ	0x10(%R10),%ZMM26

(257) 0x439208 MOV	(%R10),%RSI

(257) 0x43920b VPBROADCASTQ	%RDI,%ZMM29

(257) 0x439211 MOV	0x58(%RSP),%RDI

(257) 0x439216 IMUL	%R11,%RSI

(257) 0x43921a MOV	0x68(%RSP),%R12

(257) 0x43921f MOV	0x60(%RSP),%RBX

(257) 0x439224 MOV	(%RDI),%R10

(257) 0x439227 IMUL	%R9,%R8

(257) 0x43922b MOV	(%RBX),%RCX

(257) 0x43922e MOV	(%R12),%RAX

(257) 0x439232 VPBROADCASTQ	%RSI,%ZMM31

(257) 0x439238 MOV	%R10,%RSI

(257) 0x43923b IMUL	%R11,%RSI

(257) 0x43923f IMUL	%R9,%R10

(257) 0x439243 IMUL	%R11,%RAX

(257) 0x439247 VPBROADCASTQ	%R8,%ZMM19

(257) 0x43924d MOV	%RCX,%R8

(257) 0x439250 IMUL	%R11,%R8

(257) 0x439254 IMUL	%R9,%RCX

(257) 0x439258 VPBROADCASTQ	%RSI,%ZMM10

(257) 0x43925e VPBROADCASTQ	0x10(%R12),%ZMM8

(257) 0x439266 MOV	%R14D,%R13D

(257) 0x439269 VPBROADCASTQ	%RAX,%ZMM9

(257) 0x43926f VMOVDQA64	%ZMM10,0x200(%RSP)

(257) 0x439277 VPBROADCASTQ	%R10,%ZMM13

(257) 0x43927d VPBROADCASTQ	0x10(%RBX),%ZMM11

(257) 0x439284 VPBROADCASTQ	0x10(%RDI),%ZMM23

(257) 0x43928b VBROADCASTSD	0x35343(%RIP),%ZMM22

(257) 0x439295 VBROADCASTSD	0x35a51(%RIP),%ZMM10

(257) 0x43929f VBROADCASTSD	0x35a9f(%RIP),%ZMM21

(257) 0x4392a9 SHR	$0x4,%R13D

(257) 0x4392ad VMOVDQA64	%ZMM8,0x2c0(%RSP)

(257) 0x4392b5 VMOVDQA64	%ZMM9,0x280(%RSP)

(257) 0x4392bd VPBROADCASTQ	%R8,%ZMM30

(257) 0x4392c3 VPBROADCASTQ	%RCX,%ZMM18

(257) 0x4392c9 VMOVDQA64	%ZMM13,0x1c0(%RSP)

(257) 0x4392d1 XOR	%R9D,%R9D

(257) 0x4392d4 VMOVSD	%XMM3,0x50(%RSP)

(257) 0x4392da VMOVSD	%XMM4,0x48(%RSP)

(257) 0x4392e0 VMOVSD	%XMM2,0x40(%RSP)

(257) 0x4392e6 VMOVSD	%XMM1,0x38(%RSP)

(257) 0x4392ec KXNORB	%K1,%K1,%K1

  (259) 0x4392f0 VMOVDQA32	%ZMM28,%ZMM2

  (259) 0x4392f6 VEXTRACTI32X8	$0x1,%ZMM2,%YMM4

  (259) 0x4392fd VPMOVSXDQ	%YMM2,%ZMM1

  (259) 0x439303 VPMOVSXDQ	%YMM4,%ZMM0

  (259) 0x439309 VMOVDQA64	0x500(%RSP),%ZMM14

  (259) 0x439311 VMOVDQA64	0x440(%RSP),%ZMM4

  (259) 0x439319 VPSLLQ	$0x3,%ZMM1,%ZMM3

  (259) 0x439320 VPSLLQ	$0x3,%ZMM0,%ZMM6

  (259) 0x439327 VPADDQ	%ZMM14,%ZMM3,%ZMM15

  (259) 0x43932d VPADDQ	%ZMM4,%ZMM1,%ZMM13

  (259) 0x439333 VPADDQ	%ZMM14,%ZMM6,%ZMM5

  (259) 0x439339 VMOVDQA64	0x480(%RSP),%ZMM14

  (259) 0x439341 VPSLLQ	$0x3,%ZMM13,%ZMM3

  (259) 0x439348 VMOVDQA64	0x4c0(%RSP),%ZMM8

  (259) 0x439350 KMOVB	%K1,%K3

  (259) 0x439354 VGATHERQPD	(,%ZMM15,1),%ZMM7{%K3}

  (259) 0x43935f VPADDQ	%ZMM14,%ZMM3,%ZMM15

  (259) 0x439365 KMOVB	%K1,%K4

  (259) 0x439369 KMOVB	%K1,%K6

  (259) 0x43936d VGATHERQPD	(,%ZMM5,1),%ZMM6{%K4}

  (259) 0x439378 VGATHERQPD	(,%ZMM15,1),%ZMM13{%K6}

  (259) 0x439383 VPADDQ	%ZMM4,%ZMM0,%ZMM5

  (259) 0x439389 VMOVDQA64	0x3c0(%RSP),%ZMM15

  (259) 0x439391 KMOVB	%K1,%K5

  (259) 0x439395 VGATHERQPD	(%RDX,%ZMM8,1),%ZMM9{%K5}

  (259) 0x43939c VPSLLQ	$0x3,%ZMM5,%ZMM8

  (259) 0x4393a3 VPADDQ	%ZMM14,%ZMM8,%ZMM3

  (259) 0x4393a9 VPADDQ	%ZMM15,%ZMM1,%ZMM14

  (259) 0x4393af VPSLLQ	$0x3,%ZMM14,%ZMM5

  (259) 0x4393b6 VMOVDQA64	0x400(%RSP),%ZMM14

  (259) 0x4393be VPADDQ	%ZMM15,%ZMM0,%ZMM15

  (259) 0x4393c4 VPADDQ	%ZMM14,%ZMM5,%ZMM8

  (259) 0x4393ca VPSLLQ	$0x3,%ZMM15,%ZMM5

  (259) 0x4393d1 VMOVDQA64	0x340(%RSP),%ZMM15

  (259) 0x4393d9 VMOVDQA64	0x380(%RSP),%ZMM24

  (259) 0x4393e1 VPADDQ	%ZMM14,%ZMM5,%ZMM14

  (259) 0x4393e7 KMOVB	%K1,%K7

  (259) 0x4393eb KMOVB	%K1,%K2

  (259) 0x4393ef VGATHERQPD	(,%ZMM3,1),%ZMM4{%K7}

  (259) 0x4393fa VGATHERQPD	(,%ZMM8,1),%ZMM3{%K2}

  (259) 0x439405 VPADDQ	%ZMM15,%ZMM1,%ZMM8

  (259) 0x43940b KMOVB	%K1,%K3

  (259) 0x43940f VGATHERQPD	(,%ZMM14,1),%ZMM5{%K3}

  (259) 0x43941a VPSLLQ	$0x3,%ZMM8,%ZMM14

  (259) 0x439421 VPADDQ	%ZMM24,%ZMM14,%ZMM8

  (259) 0x439427 VPADDQ	%ZMM15,%ZMM0,%ZMM15

  (259) 0x43942d VADDPD	%ZMM5,%ZMM5,%ZMM5

  (259) 0x439433 VADDPD	%ZMM3,%ZMM3,%ZMM3

  (259) 0x439439 KMOVB	%K1,%K4

  (259) 0x43943d VGATHERQPD	(,%ZMM8,1),%ZMM14{%K4}

  (259) 0x439448 VPSLLQ	$0x3,%ZMM15,%ZMM8

  (259) 0x43944f VPADDQ	%ZMM24,%ZMM8,%ZMM8

  (259) 0x439455 KMOVB	%K1,%K5

  (259) 0x439459 VGATHERQPD	(,%ZMM8,1),%ZMM15{%K5}

  (259) 0x439464 VDIVPD	%ZMM15,%ZMM5,%ZMM8

  (259) 0x43946a VMINPD	%ZMM9,%ZMM7,%ZMM7

  (259) 0x439470 VFMADD132PD	%ZMM4,%ZMM8,%ZMM4

  (259) 0x439476 VMINPD	%ZMM9,%ZMM6,%ZMM6

  (259) 0x43947c VDIVPD	%ZMM14,%ZMM3,%ZMM14

  (259) 0x439482 VFMADD231PD	%ZMM13,%ZMM13,%ZMM14

  (259) 0x439488 VMOVAPD	0x300(%RSP),%ZMM15

  (259) 0x439490 VSQRTPD	%ZMM4,%ZMM4

  (259) 0x439496 VMULPD	%ZMM15,%ZMM7,%ZMM5

  (259) 0x43949c VMULPD	%ZMM15,%ZMM6,%ZMM9

  (259) 0x4394a2 VSQRTPD	%ZMM14,%ZMM13

  (259) 0x4394a8 VMAXPD	%ZMM22,%ZMM4,%ZMM14

  (259) 0x4394ae VMAXPD	%ZMM22,%ZMM13,%ZMM8

  (259) 0x4394b4 VPADDQ	%ZMM29,%ZMM1,%ZMM4

  (259) 0x4394ba VPSLLQ	$0x3,%ZMM4,%ZMM7

  (259) 0x4394c1 VDIVPD	%ZMM8,%ZMM5,%ZMM3

  (259) 0x4394c7 VDIVPD	%ZMM14,%ZMM9,%ZMM13

  (259) 0x4394cd VMOVAPD	%ZMM3,0x600(%RSP)

  (259) 0x4394d5 VMOVAPD	%ZMM13,0x5c0(%RSP)

  (259) 0x4394dd VPADDQ	%ZMM12,%ZMM7,%ZMM15

  (259) 0x4394e3 VPADDQ	%ZMM29,%ZMM0,%ZMM5

  (259) 0x4394e9 VPADDQ	%ZMM19,%ZMM1,%ZMM9

  (259) 0x4394ef VPSLLQ	$0x3,%ZMM5,%ZMM8

  (259) 0x4394f6 VPSLLQ	$0x3,%ZMM9,%ZMM13

  (259) 0x4394fd KMOVB	%K1,%K6

  (259) 0x439501 VGATHERQPD	(,%ZMM15,1),%ZMM14{%K6}

  (259) 0x43950c VPADDQ	%ZMM19,%ZMM0,%ZMM15

  (259) 0x439512 VPADDQ	%ZMM12,%ZMM8,%ZMM3

  (259) 0x439518 VPADDQ	%ZMM12,%ZMM13,%ZMM4

  (259) 0x43951e VPSLLQ	$0x3,%ZMM15,%ZMM5

  (259) 0x439525 VPADDD	0xc0(%RSP),%ZMM2,%ZMM2

  (259) 0x43952d VPADDQ	%ZMM12,%ZMM5,%ZMM8

  (259) 0x439533 KMOVB	%K1,%K7

  (259) 0x439537 KMOVB	%K1,%K2

  (259) 0x43953b VGATHERQPD	(,%ZMM3,1),%ZMM6{%K7}

  (259) 0x439546 VGATHERQPD	(,%ZMM4,1),%ZMM7{%K2}

  (259) 0x439551 VPADDQ	%ZMM31,%ZMM1,%ZMM3

  (259) 0x439557 VPSLLQ	$0x3,%ZMM3,%ZMM13

  (259) 0x43955e VPADDQ	%ZMM31,%ZMM0,%ZMM5

  (259) 0x439564 VADDPD	%ZMM7,%ZMM14,%ZMM14

  (259) 0x43956a KMOVB	%K1,%K3

  (259) 0x43956e VGATHERQPD	(,%ZMM8,1),%ZMM9{%K3}

  (259) 0x439579 VPADDQ	%ZMM26,%ZMM13,%ZMM4

  (259) 0x43957f VPSLLQ	$0x3,%ZMM5,%ZMM8

  (259) 0x439586 VADDPD	%ZMM9,%ZMM6,%ZMM6

  (259) 0x43958c VPMOVSXDQ	%YMM2,%ZMM5

  (259) 0x439592 VEXTRACTI32X8	$0x1,%ZMM2,%YMM9

  (259) 0x439599 VPMOVSXDQ	%YMM9,%ZMM2

  (259) 0x43959f VPADDQ	%ZMM26,%ZMM8,%ZMM3

  (259) 0x4395a5 KMOVB	%K1,%K4

  (259) 0x4395a9 VGATHERQPD	(,%ZMM4,1),%ZMM15{%K4}

  (259) 0x4395b4 VPADDQ	%ZMM5,%ZMM29,%ZMM4

  (259) 0x4395ba VMULPD	%ZMM15,%ZMM14,%ZMM7

  (259) 0x4395c0 VPADDQ	%ZMM5,%ZMM19,%ZMM9

  (259) 0x4395c6 VPSLLQ	$0x3,%ZMM4,%ZMM15

  (259) 0x4395cd KMOVB	%K1,%K5

  (259) 0x4395d1 VGATHERQPD	(,%ZMM3,1),%ZMM13{%K5}

  (259) 0x4395dc VPADDQ	%ZMM2,%ZMM29,%ZMM3

  (259) 0x4395e2 VMULPD	%ZMM13,%ZMM6,%ZMM6

  (259) 0x4395e8 VPADDQ	%ZMM12,%ZMM15,%ZMM8

  (259) 0x4395ee VPSLLQ	$0x3,%ZMM3,%ZMM13

  (259) 0x4395f5 VPSLLQ	$0x3,%ZMM9,%ZMM15

  (259) 0x4395fc VPADDQ	%ZMM12,%ZMM13,%ZMM14

  (259) 0x439602 KMOVB	%K1,%K6

  (259) 0x439606 VPADDQ	%ZMM2,%ZMM19,%ZMM13

  (259) 0x43960c VGATHERQPD	(,%ZMM8,1),%ZMM4{%K6}

  (259) 0x439617 VPADDQ	%ZMM12,%ZMM15,%ZMM8

  (259) 0x43961d KMOVB	%K1,%K7

  (259) 0x439621 KMOVB	%K1,%K2

  (259) 0x439625 VGATHERQPD	(,%ZMM14,1),%ZMM3{%K7}

  (259) 0x439630 VGATHERQPD	(,%ZMM8,1),%ZMM15{%K2}

  (259) 0x43963b VPSLLQ	$0x3,%ZMM13,%ZMM14

  (259) 0x439642 VPADDQ	%ZMM5,%ZMM31,%ZMM8

  (259) 0x439648 VPADDQ	%ZMM12,%ZMM14,%ZMM9

  (259) 0x43964e VPSLLQ	$0x3,%ZMM8,%ZMM14

  (259) 0x439655 VADDPD	%ZMM15,%ZMM4,%ZMM4

  (259) 0x43965b KMOVB	%K1,%K3

  (259) 0x43965f VGATHERQPD	(,%ZMM9,1),%ZMM13{%K3}

  (259) 0x43966a VPADDQ	%ZMM26,%ZMM14,%ZMM9

  (259) 0x439670 VPADDQ	%ZMM2,%ZMM31,%ZMM8

  (259) 0x439676 VADDPD	%ZMM13,%ZMM3,%ZMM3

  (259) 0x43967c KMOVB	%K1,%K4

  (259) 0x439680 VPADDD	0x100(%RSP),%ZMM28,%ZMM28

  (259) 0x439688 VGATHERQPD	(,%ZMM9,1),%ZMM14{%K4}

  (259) 0x439693 VMOVDQA64	0x280(%RSP),%ZMM13

  (259) 0x43969b VPSLLQ	$0x3,%ZMM8,%ZMM9

  (259) 0x4396a2 VPADDQ	%ZMM13,%ZMM1,%ZMM15

  (259) 0x4396a8 VMULPD	%ZMM14,%ZMM4,%ZMM4

  (259) 0x4396ae VPADDQ	%ZMM26,%ZMM9,%ZMM8

  (259) 0x4396b4 VMOVDQA64	0x2c0(%RSP),%ZMM14

  (259) 0x4396bc KMOVB	%K1,%K5

  (259) 0x4396c0 VGATHERQPD	(,%ZMM8,1),%ZMM9{%K5}

  (259) 0x4396cb VPSLLQ	$0x3,%ZMM15,%ZMM8

  (259) 0x4396d2 VMULPD	%ZMM9,%ZMM3,%ZMM3

  (259) 0x4396d8 VPADDQ	%ZMM13,%ZMM0,%ZMM13

  (259) 0x4396de VPADDQ	%ZMM14,%ZMM8,%ZMM9

  (259) 0x4396e4 KMOVB	%K1,%K6

  (259) 0x4396e8 VPSLLQ	$0x3,%ZMM13,%ZMM8

  (259) 0x4396ef VGATHERQPD	(,%ZMM9,1),%ZMM15{%K6}

  (259) 0x4396fa VMULPD	%ZMM22,%ZMM15,%ZMM24

  (259) 0x439700 VPADDQ	%ZMM14,%ZMM8,%ZMM9

  (259) 0x439706 VMOVAPD	0x240(%RSP),%ZMM13

  (259) 0x43970e VANDPD	%ZMM10,%ZMM4,%ZMM8

  (259) 0x439714 KMOVB	%K1,%K7

  (259) 0x439718 VGATHERQPD	(,%ZMM9,1),%ZMM14{%K7}

  (259) 0x439723 VANDPD	%ZMM10,%ZMM7,%ZMM9

  (259) 0x439729 VMAXPD	%ZMM9,%ZMM8,%ZMM8

  (259) 0x43972f VMULPD	%ZMM13,%ZMM15,%ZMM16

  (259) 0x439735 VMULPD	%ZMM22,%ZMM14,%ZMM20

  (259) 0x43973b VMAXPD	%ZMM24,%ZMM8,%ZMM9

  (259) 0x439741 VMULPD	%ZMM13,%ZMM14,%ZMM17

  (259) 0x439747 VANDPD	%ZMM10,%ZMM3,%ZMM13

  (259) 0x43974d VDIVPD	%ZMM9,%ZMM16,%ZMM8

  (259) 0x439753 VANDPD	%ZMM10,%ZMM6,%ZMM9

  (259) 0x439759 VMOVAPD	%ZMM8,0x580(%RSP)

  (259) 0x439761 VMAXPD	%ZMM9,%ZMM13,%ZMM8

  (259) 0x439767 VPADDQ	%ZMM30,%ZMM1,%ZMM9

  (259) 0x43976d KMOVB	%K1,%K2

  (259) 0x439771 VMAXPD	%ZMM20,%ZMM8,%ZMM13

  (259) 0x439777 VPSLLQ	$0x3,%ZMM9,%ZMM8

  (259) 0x43977e KMOVB	%K1,%K3

  (259) 0x439782 VDIVPD	%ZMM13,%ZMM17,%ZMM17

  (259) 0x439788 VPADDQ	%ZMM11,%ZMM8,%ZMM13

  (259) 0x43978e VPADDQ	%ZMM30,%ZMM0,%ZMM8

  (259) 0x439794 VGATHERQPD	(,%ZMM13,1),%ZMM9{%K2}

  (259) 0x43979f VPSLLQ	$0x3,%ZMM8,%ZMM13

  (259) 0x4397a6 VPADDQ	%ZMM11,%ZMM13,%ZMM13

  (259) 0x4397ac VGATHERQPD	(,%ZMM13,1),%ZMM8{%K3}

  (259) 0x4397b7 VPADDQ	%ZMM30,%ZMM5,%ZMM13

  (259) 0x4397bd VPSLLQ	$0x3,%ZMM13,%ZMM13

  (259) 0x4397c4 VPADDQ	%ZMM11,%ZMM13,%ZMM13

  (259) 0x4397ca KMOVB	%K1,%K4

  (259) 0x4397ce VGATHERQPD	(,%ZMM13,1),%ZMM27{%K4}

  (259) 0x4397d9 VPADDQ	%ZMM30,%ZMM2,%ZMM13

  (259) 0x4397df VMOVDQA64	0x200(%RSP),%ZMM25

  (259) 0x4397e7 VPSLLQ	$0x3,%ZMM13,%ZMM13

  (259) 0x4397ee VMOVAPD	%ZMM27,0x540(%RSP)

  (259) 0x4397f6 VPADDQ	%ZMM11,%ZMM13,%ZMM13

  (259) 0x4397fc KMOVB	%K1,%K5

  (259) 0x439800 VGATHERQPD	(,%ZMM13,1),%ZMM27{%K5}

  (259) 0x43980b VPADDQ	%ZMM25,%ZMM1,%ZMM13

  (259) 0x439811 VPSLLQ	$0x3,%ZMM13,%ZMM13

  (259) 0x439818 VPADDQ	%ZMM23,%ZMM13,%ZMM13

  (259) 0x43981e KMOVB	%K1,%K6

  (259) 0x439822 VGATHERQPD	(,%ZMM13,1),%ZMM16{%K6}

  (259) 0x43982d VPADDQ	%ZMM25,%ZMM0,%ZMM13

  (259) 0x439833 VADDPD	0x540(%RSP),%ZMM9,%ZMM9

  (259) 0x43983b VPSLLQ	$0x3,%ZMM13,%ZMM13

  (259) 0x439842 VPADDQ	%ZMM23,%ZMM13,%ZMM13

  (259) 0x439848 VADDPD	%ZMM27,%ZMM8,%ZMM8

  (259) 0x43984e KMOVB	%K1,%K7

  (259) 0x439852 VPADDQ	%ZMM18,%ZMM0,%ZMM27

  (259) 0x439858 VGATHERQPD	(,%ZMM13,1),%ZMM25{%K7}

  (259) 0x439863 VPADDQ	%ZMM18,%ZMM5,%ZMM5

  (259) 0x439869 VPADDQ	%ZMM18,%ZMM1,%ZMM13

  (259) 0x43986f VMULPD	%ZMM16,%ZMM9,%ZMM9

  (259) 0x439875 VPSLLQ	$0x3,%ZMM13,%ZMM13

  (259) 0x43987c VPSLLQ	$0x3,%ZMM27,%ZMM16

  (259) 0x439883 VPSLLQ	$0x3,%ZMM5,%ZMM5

  (259) 0x43988a VPADDQ	%ZMM11,%ZMM16,%ZMM27

  (259) 0x439890 VPADDQ	%ZMM11,%ZMM13,%ZMM13

  (259) 0x439896 VMOVDQA64	0x1c0(%RSP),%ZMM16

  (259) 0x43989e VPADDQ	%ZMM11,%ZMM5,%ZMM5

  (259) 0x4398a4 VPADDQ	%ZMM18,%ZMM2,%ZMM2

  (259) 0x4398aa VMULPD	%ZMM25,%ZMM8,%ZMM8

  (259) 0x4398b0 KMOVB	%K1,%K2

  (259) 0x4398b4 KMOVB	%K1,%K3

  (259) 0x4398b8 VGATHERQPD	(,%ZMM13,1),%ZMM25{%K2}

  (259) 0x4398c3 KMOVB	%K1,%K4

  (259) 0x4398c7 VGATHERQPD	(,%ZMM27,1),%ZMM13{%K3}

  (259) 0x4398d2 VGATHERQPD	(,%ZMM5,1),%ZMM27{%K4}

  (259) 0x4398dd VPSLLQ	$0x3,%ZMM2,%ZMM5

  (259) 0x4398e4 VPADDQ	%ZMM11,%ZMM5,%ZMM2

  (259) 0x4398ea VPADDQ	%ZMM16,%ZMM1,%ZMM1

  (259) 0x4398f0 VADDPD	%ZMM27,%ZMM25,%ZMM25

  (259) 0x4398f6 KMOVB	%K1,%K5

  (259) 0x4398fa VGATHERQPD	(,%ZMM2,1),%ZMM5{%K5}

  (259) 0x439905 VPSLLQ	$0x3,%ZMM1,%ZMM2

  (259) 0x43990c VPADDQ	%ZMM23,%ZMM2,%ZMM1

  (259) 0x439912 KMOVB	%K1,%K6

  (259) 0x439916 VGATHERQPD	(,%ZMM1,1),%ZMM2{%K6}

  (259) 0x439921 VMULPD	%ZMM2,%ZMM25,%ZMM27

  (259) 0x439927 VPADDQ	%ZMM16,%ZMM0,%ZMM0

  (259) 0x43992d VPSLLQ	$0x3,%ZMM0,%ZMM1

  (259) 0x439934 VADDPD	%ZMM5,%ZMM13,%ZMM13

  (259) 0x43993a VPADDQ	%ZMM23,%ZMM1,%ZMM0

  (259) 0x439940 VMOVAPD	0x180(%RSP),%ZMM5

  (259) 0x439948 VANDPD	%ZMM10,%ZMM9,%ZMM2

  (259) 0x43994e KMOVB	%K1,%K7

  (259) 0x439952 VGATHERQPD	(,%ZMM0,1),%ZMM1{%K7}

  (259) 0x43995d VANDPD	%ZMM10,%ZMM27,%ZMM0

  (259) 0x439963 VMAXPD	%ZMM2,%ZMM0,%ZMM0

  (259) 0x439969 VMULPD	%ZMM1,%ZMM13,%ZMM13

  (259) 0x43996f VMULPD	%ZMM5,%ZMM15,%ZMM1

  (259) 0x439975 VMAXPD	%ZMM24,%ZMM0,%ZMM2

  (259) 0x43997b VADDPD	%ZMM27,%ZMM4,%ZMM4

  (259) 0x439981 VADDPD	%ZMM9,%ZMM7,%ZMM7

  (259) 0x439987 VADDPD	%ZMM13,%ZMM3,%ZMM3

  (259) 0x43998d VDIVPD	%ZMM2,%ZMM1,%ZMM0

  (259) 0x439993 VMULPD	%ZMM5,%ZMM14,%ZMM2

  (259) 0x439999 VANDPD	%ZMM10,%ZMM13,%ZMM1

  (259) 0x43999f VANDPD	%ZMM10,%ZMM8,%ZMM5

  (259) 0x4399a5 VSUBPD	%ZMM7,%ZMM4,%ZMM9

  (259) 0x4399ab VMAXPD	%ZMM5,%ZMM1,%ZMM1

  (259) 0x4399b1 VADDPD	%ZMM8,%ZMM6,%ZMM6

  (259) 0x4399b7 VMOVAPD	0x140(%RSP),%ZMM7

  (259) 0x4399bf VMAXPD	%ZMM20,%ZMM1,%ZMM5

  (259) 0x4399c5 VMULPD	0x35f71(%RIP),%ZMM9,%ZMM1

  (259) 0x4399cf VSUBPD	%ZMM6,%ZMM3,%ZMM8

  (259) 0x4399d5 VDIVPD	%ZMM5,%ZMM2,%ZMM2

  (259) 0x4399db VBROADCASTSD	0x34beb(%RIP),%ZMM5

  (259) 0x4399e5 VMULPD	0x35f51(%RIP),%ZMM8,%ZMM13

  (259) 0x4399ef VDIVPD	%ZMM15,%ZMM1,%ZMM15

  (259) 0x4399f5 VCMPPD	$0x1,0x35f80(%RIP),%ZMM15,%K2

  (259) 0x439a00 VMOVAPD	%ZMM21,%ZMM9

  (259) 0x439a06 VDIVPD	%ZMM15,%ZMM5,%ZMM4

  (259) 0x439a0c VMULPD	%ZMM7,%ZMM4,%ZMM9{%K2}

  (259) 0x439a12 VDIVPD	%ZMM14,%ZMM13,%ZMM14

  (259) 0x439a18 VCMPPD	$0x1,0x35f5d(%RIP),%ZMM14,%K3

  (259) 0x439a23 VMOVAPD	%ZMM21,%ZMM6

  (259) 0x439a29 INC	%R9D

  (259) 0x439a2c VMINPD	0x600(%RSP),%ZMM9,%ZMM1

  (259) 0x439a34 VBROADCASTSD	0x34b92(%RIP),%ZMM15

  (259) 0x439a3e VMINPD	0x680(%RSP),%ZMM21,%ZMM8

  (259) 0x439a46 VDIVPD	%ZMM14,%ZMM15,%ZMM3

  (259) 0x439a4c VMULPD	%ZMM7,%ZMM3,%ZMM6{%K3}

  (259) 0x439a52 VMINPD	0x640(%RSP),%ZMM21,%ZMM4

  (259) 0x439a5a VMINPD	%ZMM0,%ZMM1,%ZMM0

  (259) 0x439a60 VMINPD	%ZMM17,%ZMM8,%ZMM13

  (259) 0x439a66 VMINPD	0x580(%RSP),%ZMM4,%ZMM9

  (259) 0x439a6e VMINPD	0x5c0(%RSP),%ZMM6,%ZMM14

  (259) 0x439a76 VMINPD	%ZMM0,%ZMM9,%ZMM7

  (259) 0x439a7c VMINPD	%ZMM2,%ZMM14,%ZMM2

  (259) 0x439a82 VMOVAPD	%ZMM7,0x640(%RSP)

  (259) 0x439a8a VMINPD	%ZMM2,%ZMM13,%ZMM5

  (259) 0x439a90 VMOVAPD	%ZMM5,0x680(%RSP)

  (259) 0x439a98 CMP	%R9D,%R13D

  (259) 0x439a9b JNE	4392f0

(257) 0x439aa1 MOV	%R14D,%R13D

(257) 0x439aa4 AND	$-0x10,%R13D

(257) 0x439aa8 ADD	%R13D,0xb8(%RSP)

(257) 0x439ab0 ADD	%R13D,0xbc(%RSP)

(257) 0x439ab8 VMOVSD	0x50(%RSP),%XMM3

(257) 0x439abe VMOVSD	0x48(%RSP),%XMM4

(257) 0x439ac4 VMOVSD	0x40(%RSP),%XMM2

(257) 0x439aca VMOVSD	0x38(%RSP),%XMM1

(257) 0x439ad0 TEST	$0xf,%R14B

(257) 0x439ad4 JE	439e49

(257) 0x439ada MOV	0x60(%RSP),%RDI

(257) 0x439adf MOV	0x98(%RSP),%R8

(257) 0x439ae7 MOV	0x10(%RDI),%R12

(257) 0x439aeb MOV	0x8(%R8),%R9

(257) 0x439aef MOV	0xa0(%RSP),%RAX

(257) 0x439af7 VMOVSD	(%R9,%RDX,1),%XMM12

(257) 0x439afd MOV	0x8(%RAX),%RCX

(257) 0x439b01 MOV	0x90(%RSP),%RDX

(257) 0x439b09 MOV	%R12,0x580(%RSP)

(257) 0x439b11 MOV	0x88(%RSP),%R12

(257) 0x439b19 MOV	0x58(%RSP),%R10

(257) 0x439b1e MOV	(%RDX),%R13

(257) 0x439b21 MOV	%RCX,0x600(%RSP)

(257) 0x439b29 MOV	(%R12),%RCX

(257) 0x439b2d MOV	0x10(%R10),%R14

(257) 0x439b31 MOV	0x78(%RSP),%RBX

(257) 0x439b36 IMUL	%R11,%R13

(257) 0x439b3a IMUL	%R11,%RCX

(257) 0x439b3e MOV	0x10(%RBX),%RSI

(257) 0x439b42 MOV	0x10(%R12),%R8

(257) 0x439b47 MOV	0x80(%RSP),%R9

(257) 0x439b4f MOV	(%RBX),%RBX

(257) 0x439b52 MOV	%R14,0x5c0(%RSP)

(257) 0x439b5a MOV	0x10(%RDX),%R14

(257) 0x439b5e MOV	(%R9),%R12

(257) 0x439b61 MOV	0x10(%R9),%RDX

(257) 0x439b65 LEA	(%R14,%R13,8),%R14

(257) 0x439b69 MOV	0xb0(%RSP),%R9

(257) 0x439b71 LEA	(%R8,%RCX,8),%R13

(257) 0x439b75 LEA	(,%RBX,8),%RCX

(257) 0x439b7d MOV	%RCX,%R8

(257) 0x439b80 IMUL	%R11,%R8

(257) 0x439b84 IMUL	%R9,%RCX

(257) 0x439b88 IMUL	%R11,%R12

(257) 0x439b8c ADD	%RSI,%R8

(257) 0x439b8f ADD	%RSI,%RCX

(257) 0x439b92 MOV	0x70(%RSP),%RSI

(257) 0x439b97 LEA	(%RDX,%R12,8),%R12

(257) 0x439b9b MOV	(%RSI),%RBX

(257) 0x439b9e MOV	0x10(%RSI),%RDX

(257) 0x439ba2 MOV	0x68(%RSP),%RSI

(257) 0x439ba7 IMUL	%R11,%RBX

(257) 0x439bab MOV	%RCX,0x540(%RSP)

(257) 0x439bb3 VMOVSD	0x640(%RSP),%XMM9

(257) 0x439bbc MOVSXD	0xb8(%RSP),%RAX

(257) 0x439bc4 MOV	(%RSI),%RCX

(257) 0x439bc7 LEA	(%RDX,%RBX,8),%R9

(257) 0x439bcb IMUL	%R11,%RCX

(257) 0x439bcf MOV	(%RDI),%RDI

(257) 0x439bd2 MOV	0x10(%RSI),%RBX

(257) 0x439bd6 MOV	(%R10),%R10

(257) 0x439bd9 LEA	(%RBX,%RCX,8),%RBX

(257) 0x439bdd LEA	(,%RDI,8),%RCX

(257) 0x439be5 MOV	0x580(%RSP),%RSI

(257) 0x439bed MOV	%RDI,0x500(%RSP)

(257) 0x439bf5 MOV	%R10,0x580(%RSP)

(257) 0x439bfd MOV	%RCX,%RDI

(257) 0x439c00 SAL	$0x3,%R10

(257) 0x439c04 IMUL	%R11,%RDI

(257) 0x439c08 IMUL	%R10,%R11

(257) 0x439c0c MOV	0x5c0(%RSP),%RDX

(257) 0x439c14 ADD	%RSI,%RDI

(257) 0x439c17 ADD	%R11,%RDX

(257) 0x439c1a MOV	0xb0(%RSP),%R11

(257) 0x439c22 VMOVSD	0x35d16(%RIP),%XMM11

(257) 0x439c2a IMUL	%R11,%RCX

(257) 0x439c2e IMUL	%R11,%R10

(257) 0x439c32 MOV	0xbc(%RSP),%R11D

(257) 0x439c3a ADD	%RSI,%RCX

(257) 0x439c3d MOV	0x5c0(%RSP),%RSI

(257) 0x439c45 VMOVSD	0x35d33(%RIP),%XMM10

(257) 0x439c4d ADD	%RSI,%R10

(257) 0x439c50 MOV	0xb8(%RSP),%ESI

(257) 0x439c57 SUB	%ESI,%R11D

(257) 0x439c5a MOV	%R11D,0x5c0(%RSP)

(257) 0x439c62 MOV	0x540(%RSP),%RSI

(257) 0x439c6a JMP	439c90

0x439c6c NOPL	(%RAX)

  (258) 0x439c70 VMINSD	%XMM13,%XMM6,%XMM6

  (258) 0x439c75 VMINSD	%XMM6,%XMM9,%XMM9

  (258) 0x439c79 MOV	0x5c0(%RSP),%R11D

  (258) 0x439c81 INC	%RAX

  (258) 0x439c84 ADD	%EAX,%R11D

  (258) 0x439c87 CMP	%R15D,%R11D

  (258) 0x439c8a JAE	439e40

  (258) 0x439c90 VMOVSD	(%R13,%RAX,8),%XMM15

  (258) 0x439c97 VMOVSD	(%R14,%RAX,8),%XMM0

  (258) 0x439c9d VADDSD	%XMM15,%XMM15,%XMM6

  (258) 0x439ca2 MOV	0x600(%RSP),%R11

  (258) 0x439caa VDIVSD	(%R12,%RAX,8),%XMM6,%XMM8

  (258) 0x439cb0 VFMADD132SD	%XMM0,%XMM8,%XMM0

  (258) 0x439cb5 VMINSD	(%R11,%RAX,8),%XMM12,%XMM13

  (258) 0x439cbb VMOVSD	0x8(%R8,%RAX,8),%XMM8

  (258) 0x439cc2 VMULSD	%XMM2,%XMM13,%XMM14

  (258) 0x439cc6 VSQRTSD	%XMM0,%XMM0,%XMM0

  (258) 0x439cca VADDSD	0x8(%RSI,%RAX,8),%XMM8,%XMM13

  (258) 0x439cd0 VMOVSD	(%RCX,%RAX,8),%XMM8

  (258) 0x439cd5 VMAXSD	0x348fb(%RIP),%XMM0,%XMM5

  (258) 0x439cdd VMOVSD	(%R8,%RAX,8),%XMM0

  (258) 0x439ce3 VDIVSD	%XMM5,%XMM14,%XMM7

  (258) 0x439ce7 VADDSD	(%RSI,%RAX,8),%XMM0,%XMM15

  (258) 0x439cec VMOVSD	(%RDI,%RAX,8),%XMM14

  (258) 0x439cf1 VMULSD	0x8(%R9,%RAX,8),%XMM13,%XMM0

  (258) 0x439cf8 VADDSD	0x8(%RCX,%RAX,8),%XMM8,%XMM13

  (258) 0x439cfe VMULSD	(%R9,%RAX,8),%XMM15,%XMM5

  (258) 0x439d04 VMOVSD	(%RBX,%RAX,8),%XMM15

  (258) 0x439d09 VMULSD	(%R10,%RAX,8),%XMM13,%XMM8

  (258) 0x439d0f VMULSD	0x348bf(%RIP),%XMM15,%XMM19

  (258) 0x439d19 VMULSD	%XMM15,%XMM1,%XMM13

  (258) 0x439d1e VANDPD	0x34fc8(%RIP),%XMM5,%XMM26

  (258) 0x439d28 VMULSD	%XMM15,%XMM3,%XMM31

  (258) 0x439d2e VMINSD	0x35012(%RIP),%XMM7,%XMM6

  (258) 0x439d36 VADDSD	0x8(%RDI,%RAX,8),%XMM14,%XMM7

  (258) 0x439d3c VANDPD	0x34fac(%RIP),%XMM0,%XMM14

  (258) 0x439d44 VADDSD	%XMM8,%XMM0,%XMM0

  (258) 0x439d49 VMULSD	(%RDX,%RAX,8),%XMM7,%XMM7

  (258) 0x439d4e VMAXSD	%XMM26,%XMM14,%XMM14

  (258) 0x439d54 VMAXSD	%XMM19,%XMM14,%XMM14

  (258) 0x439d5a VADDSD	%XMM7,%XMM5,%XMM5

  (258) 0x439d5e VANDPD	0x34f88(%RIP),%XMM7,%XMM30

  (258) 0x439d68 VDIVSD	%XMM14,%XMM13,%XMM13

  (258) 0x439d6d VSUBSD	%XMM5,%XMM0,%XMM7

  (258) 0x439d71 VANDPD	0x34f77(%RIP),%XMM8,%XMM14

  (258) 0x439d79 VMULSD	%XMM11,%XMM7,%XMM8

  (258) 0x439d7e VMAXSD	%XMM30,%XMM14,%XMM14

  (258) 0x439d84 VMAXSD	%XMM19,%XMM14,%XMM14

  (258) 0x439d8a VDIVSD	%XMM15,%XMM8,%XMM15

  (258) 0x439d8f VDIVSD	%XMM14,%XMM31,%XMM14

  (258) 0x439d95 VCOMISD	%XMM15,%XMM10

  (258) 0x439d9a VMINSD	%XMM14,%XMM13,%XMM13

  (258) 0x439d9f JBE	439c70

  (258) 0x439da5 VMOVSD	0x34823(%RIP),%XMM14

  (258) 0x439dad VDIVSD	%XMM15,%XMM14,%XMM0

  (258) 0x439db2 VMULSD	%XMM4,%XMM0,%XMM5

  (258) 0x439db6 VMINSD	%XMM6,%XMM5,%XMM7

  (258) 0x439dba VMINSD	%XMM13,%XMM7,%XMM13

  (258) 0x439dbf VMINSD	%XMM13,%XMM9,%XMM9

  (258) 0x439dc4 JMP	439c79

0x439dc9 NOPL	(%RAX)

0x439dd0 VMOVAPD	0x640(%RSP),%ZMM3

0x439dd8 MOV	0x20(%RSP),%RBX

0x439ddd VMINPD	0x680(%RSP),%ZMM3,%ZMM4

0x439de5 VEXTRACTF64X4	$0x1,%ZMM4,%YMM2

0x439dec VMINPD	%YMM4,%YMM2,%YMM12

0x439df0 VEXTRACTF64X2	$0x1,%YMM12,%XMM1

0x439df7 VMINPD	%XMM12,%XMM1,%XMM11

0x439dfc VUNPCKHPD	%XMM11,%XMM11,%XMM10

0x439e01 VMINPD	%XMM11,%XMM10,%XMM8

0x439e06 VMINSD	0x35ac2(%RIP),%XMM8,%XMM15

0x439e0e VZEROUPPER

0x439e11 MOV	0x70(%RBX),%RAX

0x439e15 LEA	0x70(%RBX),%R8

(256) 0x439e19 VMOVQ	%RAX,%XMM6

(256) 0x439e1e VMINSD	%XMM6,%XMM15,%XMM14

(256) 0x439e22 VMOVQ	%XMM14,%R12

(256) 0x439e27 LOCK CMPXCHG	%R12,(%R8)

(256) 0x439e2c JNE	439e19

0x439e2e LEA	-0x28(%RBP),%RSP

0x439e32 POP	%RBX

0x439e33 POP	%R12

0x439e35 POP	%R13

0x439e37 POP	%R14

0x439e39 POP	%R15

0x439e3b POP	%RBP

0x439e3c RET

0x439e3d NOPL	(%RAX)

(257) 0x439e40 VMOVSD	%XMM9,0x640(%RSP)

(257) 0x439e49 MOV	%R15D,0xbc(%RSP)

(257) 0x439e51 MOV	0xa8(%RSP),%R15

(257) 0x439e59 INCQ	0xb0(%RSP)

(257) 0x439e61 MOV	%R15,%R11

(257) 0x439e64 CMP	%R15D,0x34(%RSP)

(257) 0x439e69 JLE	439dd0

(257) 0x439e6f MOV	0x28(%RSP),%ECX

(257) 0x439e73 MOV	0xbc(%RSP),%R14D

(257) 0x439e7b MOV	0x30(%RSP),%R13D

(257) 0x439e80 INC	%R15

(257) 0x439e83 MOV	%R13D,0xb8(%RSP)

(257) 0x439e8b MOV	%R15,0xa8(%RSP)

(257) 0x439e93 MOV	0x2c(%RSP),%EDX

(257) 0x439e97 SUB	%R14D,%ECX

(257) 0x439e9a JMP	4390b0

0x439e9f INC	%ECX

0x439ea1 XOR	%EDX,%EDX

0x439ea3 JMP	438f81

0x439ea8 VMOVSD	0x35a20(%RIP),%XMM15

0x439eb0 JMP	439e11

0x439eb5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 6.00 cycles (3.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.17 to 15.20 cycles (1.52x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
17% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
38% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.17 to 22.00 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:75

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 320 bytes (40 double precision FP elements). The binary function is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	139
loop length	583
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	3
used zmm registers	4
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.20	9.20	12.33	12.33	15.50	9.20	9.20	15.50	15.50	15.50	9.20	12.33
cycles	9.20	12.33	12.33	12.33	15.50	9.20	9.20	15.50	15.50	15.50	9.20	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	23.17
Dispatch	15.50
DIV/SQRT	12.00
Overall L1	23.17

Vectorization ratios

INT

all	7%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	47%
load	20%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

INT+FP

all	20%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	38%

Vector efficiency ratios

INT

all	14%
load	11%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	35%
load	30%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	21%
load	23%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

7% of peak load performance is reached (13.81 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.17 to 15.50 cycles (1.49x speedup).

ASM code

In the binary file, the address of the function is: 438ef0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x6c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x84(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x7c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 439ea8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfb8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 439ea8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfb8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R8D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 439e9f <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfaf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0x36943(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R9,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xbc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 439e11 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xf21>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x2c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x30(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VBROADCASTSD 0x3690d(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV %RSI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x10(%RBX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %ZMM3,0x640(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %ZMM3,0x680(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV %R14,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x1(%R11),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x10,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VADDSD %XMM1,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %EAX,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R15D,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VADDSD %XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDQA32 %ZMM6,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVDQA32 %ZMM5,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD 0x640(%RSP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x20(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMINPD 0x680(%RSP),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM4,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMINPD %YMM4,%YMM2,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF64X2 $0x1,%YMM12,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMINPD %XMM12,%XMM1,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VUNPCKHPD %XMM11,%XMM11,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMINPD %XMM11,%XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMINSD 0x35ac2(%RIP),%XMM8,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x70(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x70(%RBX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 438f81 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x91>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x35a20(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 439e11 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xf21>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 6.00 cycles (3.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
17% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
38% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.17 to 22.00 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:75

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 320 bytes (40 double precision FP elements). The binary function is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	139
loop length	583
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	3
used zmm registers	4
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.20	9.20	12.33	12.33	15.50	9.20	9.20	15.50	15.50	15.50	9.20	12.33
cycles	9.20	12.33	12.33	12.33	15.50	9.20	9.20	15.50	15.50	15.50	9.20	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	23.17
Dispatch	15.50
DIV/SQRT	12.00
Overall L1	23.17

Vectorization ratios

INT

all	7%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	47%
load	20%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

INT+FP

all	20%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	38%

Vector efficiency ratios

INT

all	14%
load	11%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	35%
load	30%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	21%
load	23%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

7% of peak load performance is reached (13.81 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 438ef0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x6c0,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x84(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x7c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 439ea8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfb8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x2(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 439ea8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfb8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R8D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 439e9f <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xfaf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0x36943(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R9,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xbc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 439e11 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xf21>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x2c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x30(%RSP),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VBROADCASTSD 0x3690d(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
MOV %RSI,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x10(%RBX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %ZMM3,0x640(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %ZMM3,0x680(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
MOV %R14,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB %R11D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x38(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EAX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x1(%R11),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x10,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VADDSD %XMM1,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %EAX,%ZMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R15D,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VADDSD %XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVDQA32 %ZMM6,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVDQA32 %ZMM5,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD 0x640(%RSP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x20(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMINPD 0x680(%RSP),%ZMM3,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM4,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VMINPD %YMM4,%YMM2,%YMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF64X2 $0x1,%YMM12,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMINPD %XMM12,%XMM1,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VUNPCKHPD %XMM11,%XMM11,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMINPD %XMM11,%XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMINSD 0x35ac2(%RIP),%XMM8,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x70(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x70(%RBX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 438f81 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x91>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD 0x35a20(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 439e11 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0xf21>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.05	0.88
▼Loop 257 - calc_dt.cpp:49-75 - exec–	0.00	0.00
○Loop 259 - calc_dt.cpp:52-75 - exec	3.04	0.88
○Loop 258 - calc_dt.cpp:54-75 - exec	0.00	0.00
○Loop 256 - calc_dt.cpp:49-49 - exec	0.00	0.00

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Expensive FP math instructions/calls

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code