OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 4.23% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x434e50 PUSH	%RBP

0x434e51 MOV	%RSP,%RBP

0x434e54 PUSH	%R15

0x434e56 PUSH	%R14

0x434e58 PUSH	%R13

0x434e5a PUSH	%R12

0x434e5c PUSH	%RBX

0x434e5d AND	$-0x40,%RSP

0x434e61 ADD	$-0x80,%RSP

0x434e65 MOV	0x30(%RDI),%EAX

0x434e68 MOV	0x34(%RDI),%EDX

0x434e6b MOV	0x28(%RDI),%ESI

0x434e6e ADD	$0x3,%EDX

0x434e71 LEA	0x1(%RAX),%R13D

0x434e75 MOV	%ESI,0x3c(%RSP)

0x434e79 MOV	%EDX,0x40(%RSP)

0x434e7d MOV	0x2c(%RDI),%EBX

0x434e80 CMP	%EDX,%R13D

0x434e83 JGE	435773

0x434e89 LEA	0x3(%RBX),%R12D

0x434e8d MOV	%EDX,%EBX

0x434e8f SUB	%R13D,%EBX

0x434e92 CMP	%R12D,%ESI

0x434e95 JGE	435773

0x434e9b MOV	%R12D,%ECX

0x434e9e SUB	%ESI,%ECX

0x434ea0 MOV	%ECX,0x44(%RSP)

0x434ea4 MOV	%RDI,%R15

0x434ea7 CALL	404630 <omp_get_num_threads@plt>

0x434eac MOV	%EAX,%R14D

0x434eaf CALL	404520 <omp_get_thread_num@plt>

0x434eb4 MOV	%EAX,%EDI

0x434eb6 MOV	0x44(%RSP),%EAX

0x434eba XOR	%EDX,%EDX

0x434ebc IMUL	%EBX,%EAX

0x434ebf DIV	%R14D

0x434ec2 MOV	%EAX,%ECX

0x434ec4 CMP	%EDX,%EDI

0x434ec6 JB	4357dc

0x434ecc IMUL	%ECX,%EDI

0x434ecf LEA	(%RDI,%RDX,1),%EBX

0x434ed2 LEA	(%RCX,%RBX,1),%R8D

0x434ed6 MOV	%R8D,0x38(%RSP)

0x434edb CMP	%R8D,%EBX

0x434ede JAE	435773

0x434ee4 MOV	%EBX,%EAX

0x434ee6 XOR	%EDX,%EDX

0x434ee8 DIVL	0x44(%RSP)

0x434eec MOV	0x3c(%RSP),%R9D

0x434ef1 MOV	0x20(%R15),%R14

0x434ef5 MOV	0x8(%R15),%R11

0x434ef9 MOV	0x10(%R15),%RSI

0x434efd MOV	(%R15),%RDI

0x434f00 MOV	0x18(%R15),%R15

0x434f04 MOV	%R11,0x30(%RSP)

0x434f09 MOV	%RSI,0x28(%RSP)

0x434f0e MOV	%RDI,0x18(%RSP)

0x434f13 MOV	%R15,0x10(%RSP)

0x434f18 VMOVQ	0x39dce(%RIP),%XMM26

0x434f22 VMOVSD	0x3a5ac(%RIP),%XMM30

0x434f2c VMOVDQA32	0x3a88a(%RIP),%ZMM31

0x434f36 MOV	%R14,0x20(%RSP)

0x434f3b LEA	(%RDX,%R9,1),%R10D

0x434f3f ADD	%R13D,%EAX

0x434f42 MOV	%R10D,0x68(%RSP)

0x434f47 CLTQ

0x434f49 SUB	%R10D,%R12D

0x434f4c MOV	%RAX,%R14

0x434f4f NOP

(237) 0x434f50 CMP	%R12D,%ECX

(237) 0x434f53 CMOVBE	%ECX,%R12D

(237) 0x434f57 LEA	(%RBX,%R12,1),%R15D

(237) 0x434f5b CMP	%R15D,%EBX

(237) 0x434f5e JAE	4357a3

(237) 0x434f64 MOV	0x28(%RSP),%RCX

(237) 0x434f69 MOV	0x20(%RSP),%R8

(237) 0x434f6e MOV	0x30(%RSP),%R13

(237) 0x434f73 MOV	0x10(%RCX),%R9

(237) 0x434f77 MOV	(%RCX),%R10

(237) 0x434f7a MOV	0x8(%R8),%RCX

(237) 0x434f7e MOV	0x10(%RSP),%R8

(237) 0x434f83 MOV	0x10(%R13),%R11

(237) 0x434f87 MOV	(%R13),%RDX

(237) 0x434f8b MOV	0x10(%R8),%R13

(237) 0x434f8f MOV	(%R8),%R8

(237) 0x434f92 MOV	0x18(%RSP),%RAX

(237) 0x434f97 IMUL	%R14,%RDX

(237) 0x434f9b IMUL	%R14,%R10

(237) 0x434f9f IMUL	%R14,%R8

(237) 0x434fa3 MOV	(%RAX),%RDI

(237) 0x434fa6 MOV	0x10(%RAX),%RSI

(237) 0x434faa LEA	-0x1(%R12),%EAX

(237) 0x434faf MOV	%R11,0x60(%RSP)

(237) 0x434fb4 MOV	%RDX,0x58(%RSP)

(237) 0x434fb9 MOV	%R9,0x78(%RSP)

(237) 0x434fbe MOV	%R10,0x70(%RSP)

(237) 0x434fc3 IMUL	%R14,%RDI

(237) 0x434fc7 MOV	%R13,0x50(%RSP)

(237) 0x434fcc MOV	%R8,0x48(%RSP)

(237) 0x434fd1 CMP	$0xe,%EAX

(237) 0x434fd4 JBE	4357d0

(237) 0x434fda MOVSXD	0x68(%RSP),%RAX

(237) 0x434fdf LEA	(%R9,%R10,8),%R10

(237) 0x434fe3 ADD	%RAX,%RDX

(237) 0x434fe6 LEA	(%RCX,%RAX,8),%R9

(237) 0x434fea ADD	%R8,%RAX

(237) 0x434fed LEA	(%R13,%RAX,8),%R8

(237) 0x434ff2 MOV	$0x10,%EAX

(237) 0x434ff7 VPBROADCASTD	0x68(%RSP),%ZMM11

(237) 0x434fff MOV	%R12D,%R13D

(237) 0x435002 VPBROADCASTD	%EAX,%ZMM18

(237) 0x435008 MOV	$0x1,%EAX

(237) 0x43500d SHR	$0x4,%R13D

(237) 0x435011 VPBROADCASTD	%EAX,%ZMM17

(237) 0x435017 VPXOR	%XMM12,%XMM12,%XMM12

(237) 0x43501c MOV	$0x2,%EAX

(237) 0x435021 VBROADCASTSD	0x39cc5(%RIP),%ZMM9

(237) 0x43502b VBROADCASTSD	0x3a4a3(%RIP),%ZMM8

(237) 0x435035 VBROADCASTSD	0x39591(%RIP),%ZMM15

(237) 0x43503f VBROADCASTSD	0x3a5cf(%RIP),%ZMM14

(237) 0x435049 VBROADCASTSD	0x3a755(%RIP),%ZMM13

(237) 0x435053 LEA	(%R11,%RDX,8),%R11

(237) 0x435057 VPBROADCASTD	%EAX,%ZMM16

(237) 0x43505d VPADDD	%ZMM31,%ZMM11,%ZMM11

(237) 0x435063 LEA	(%RSI,%RDI,8),%RDX

(237) 0x435067 SAL	$0x7,%R13

(237) 0x43506b VXORPD	%XMM6,%XMM6,%XMM6

(237) 0x43506f VPTERNLOGD	$-0x1,%ZMM12,%ZMM12,%ZMM12

(237) 0x435076 XOR	%EAX,%EAX

(237) 0x435078 KXNORB	%K1,%K1,%K1

(237) 0x43507c NOPL	(%RAX)

  (239) 0x435080 VMOVUPD	(%R11,%RAX,1),%ZMM19

  (239) 0x435087 VMOVUPD	0x40(%R11,%RAX,1),%ZMM10

  (239) 0x43508f VMOVDQA32	%ZMM11,%ZMM0

  (239) 0x435095 VCMPPD	$0x1,%ZMM6,%ZMM10,%K3

  (239) 0x43509c VCMPPD	$0x1,%ZMM6,%ZMM19,%K4

  (239) 0x4350a3 VPADDD	%ZMM17,%ZMM0,%ZMM1

  (239) 0x4350a9 VPMOVSXDQ	%YMM0,%ZMM4

  (239) 0x4350af VEXTRACTI32X8	$0x1,%ZMM0,%YMM3

  (239) 0x4350b6 VPMOVSXDQ	%YMM3,%ZMM3

  (239) 0x4350bc VMOVDQA	%YMM1,%YMM5

  (239) 0x4350c0 VPADDD	%ZMM12,%ZMM0,%ZMM2

  (239) 0x4350c6 VMOVDQA64	%ZMM4,%ZMM7

  (239) 0x4350cc VPMOVSXDQ	%YMM5,%ZMM7{%K4}

  (239) 0x4350d2 KUNPCKBW	%K4,%K3,%K2

  (239) 0x4350d6 VEXTRACTI32X8	$0x1,%ZMM1,%YMM20

  (239) 0x4350dd VPADDD	%ZMM16,%ZMM0,%ZMM2{%K2}

  (239) 0x4350e3 VPMOVSXDQ	%YMM1,%ZMM23

  (239) 0x4350e9 VMOVDQA64	%ZMM3,%ZMM5

  (239) 0x4350ef VPMOVSXDQ	%YMM20,%ZMM5{%K3}

  (239) 0x4350f5 VMOVDQA64	%ZMM4,%ZMM23{%K4}

  (239) 0x4350fb KNOTW	%K2,%K5

  (239) 0x4350ff VPMOVSXDQ	%YMM20,%ZMM21

  (239) 0x435105 KMOVB	%K1,%K2

  (239) 0x435109 VGATHERDPD	(%RDX,%YMM2,8),%ZMM4{%K2}

  (239) 0x435110 VSHUFI32X4	$-0x12,%ZMM2,%ZMM2,%ZMM2

  (239) 0x435117 VPADDD	%ZMM12,%ZMM0,%ZMM1{%K5}

  (239) 0x43511d VMOVDQA64	%ZMM3,%ZMM21{%K3}

  (239) 0x435123 KMOVB	%K1,%K6

  (239) 0x435127 KMOVB	%K1,%K7

  (239) 0x43512b VGATHERQPD	(%R10,%ZMM7,8),%ZMM24{%K6}

  (239) 0x435132 VGATHERQPD	(%R10,%ZMM5,8),%ZMM0{%K7}

  (239) 0x435139 KMOVB	%K1,%K4

  (239) 0x43513d KMOVB	%K1,%K3

  (239) 0x435141 VGATHERQPD	(%RDX,%ZMM7,8),%ZMM20{%K4}

  (239) 0x435148 KMOVB	%K1,%K5

  (239) 0x43514c VGATHERQPD	(%RDX,%ZMM5,8),%ZMM7{%K3}

  (239) 0x435153 KMOVB	%K1,%K6

  (239) 0x435157 VGATHERDPD	(%RDX,%YMM2,8),%ZMM5{%K5}

  (239) 0x43515e VGATHERQPD	(%RDX,%ZMM23,8),%ZMM2{%K6}

  (239) 0x435165 VSUBPD	%ZMM20,%ZMM2,%ZMM2

  (239) 0x43516b VSUBPD	%ZMM4,%ZMM20,%ZMM4

  (239) 0x435171 KMOVB	%K1,%K7

  (239) 0x435175 VGATHERQPD	(%RDX,%ZMM21,8),%ZMM3{%K7}

  (239) 0x43517c VSUBPD	%ZMM7,%ZMM3,%ZMM3

  (239) 0x435182 VSUBPD	%ZMM5,%ZMM7,%ZMM5

  (239) 0x435188 VMULPD	%ZMM2,%ZMM4,%ZMM27

  (239) 0x43518e VANDPD	%ZMM9,%ZMM2,%ZMM23

  (239) 0x435194 VMULPD	%ZMM3,%ZMM5,%ZMM28

  (239) 0x43519a VMOVAPD	%ZMM6,%ZMM29

  (239) 0x4351a0 VMOVUPD	0x40(%R9,%RAX,1),%ZMM25

  (239) 0x4351a8 VCMPPD	$0xe,%ZMM6,%ZMM27,%K3

  (239) 0x4351af VANDPD	%ZMM9,%ZMM5,%ZMM5

  (239) 0x4351b5 VCMPPD	$0xe,%ZMM6,%ZMM28,%K2

  (239) 0x4351bc VCMPPD	$0xe,%ZMM6,%ZMM2,%K5{%K3}

  (239) 0x4351c3 VANDPD	%ZMM9,%ZMM19,%ZMM2

  (239) 0x4351c9 VANDPD	%ZMM9,%ZMM3,%ZMM28

  (239) 0x4351cf VCMPPD	$0xe,%ZMM6,%ZMM3,%K4{%K2}

  (239) 0x4351d6 VDIVPD	%ZMM24,%ZMM2,%ZMM3

  (239) 0x4351dc VANDPD	%ZMM9,%ZMM10,%ZMM2

  (239) 0x4351e2 VDIVPD	%ZMM0,%ZMM2,%ZMM2

  (239) 0x4351e8 VSUBPD	%ZMM2,%ZMM14,%ZMM0

  (239) 0x4351ee VMOVAPD	%ZMM6,%ZMM24

  (239) 0x4351f4 KMOVB	%K3,%K6

  (239) 0x4351f8 VGATHERDPD	(%RCX,%YMM1,8),%ZMM24{%K6}

  (239) 0x4351ff VSHUFI32X4	$-0x12,%ZMM1,%ZMM1,%ZMM1

  (239) 0x435206 KMOVB	%K2,%K7

  (239) 0x43520a VGATHERDPD	(%RCX,%YMM1,8),%ZMM29{%K7}

  (239) 0x435211 VMULPD	%ZMM28,%ZMM0,%ZMM1

  (239) 0x435217 VMOVUPD	(%R9,%RAX,1),%ZMM22

  (239) 0x43521e VANDPD	%ZMM9,%ZMM4,%ZMM4

  (239) 0x435224 VBLENDMPD	%ZMM8,%ZMM15,%ZMM21{%K5}

  (239) 0x43522a VBLENDMPD	%ZMM8,%ZMM15,%ZMM27{%K4}

  (239) 0x435230 VDIVPD	%ZMM25,%ZMM1,%ZMM0

  (239) 0x435236 VADDPD	%ZMM8,%ZMM2,%ZMM1

  (239) 0x43523c VMULPD	%ZMM13,%ZMM25,%ZMM25

  (239) 0x435242 VSUBPD	%ZMM2,%ZMM8,%ZMM2

  (239) 0x435248 VMULPD	%ZMM5,%ZMM1,%ZMM1

  (239) 0x43524e VMINPD	%ZMM28,%ZMM5,%ZMM5

  (239) 0x435254 VMULPD	%ZMM27,%ZMM2,%ZMM2

  (239) 0x43525a VPADDD	%ZMM18,%ZMM11,%ZMM11

  (239) 0x435260 VDIVPD	%ZMM29,%ZMM1,%ZMM1

  (239) 0x435266 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (239) 0x43526c VMULPD	%ZMM25,%ZMM0,%ZMM1

  (239) 0x435272 VMINPD	%ZMM5,%ZMM1,%ZMM0

  (239) 0x435278 VSUBPD	%ZMM3,%ZMM14,%ZMM1

  (239) 0x43527e VFMADD231PD	%ZMM2,%ZMM0,%ZMM7{%K2}

  (239) 0x435284 VMULPD	%ZMM23,%ZMM1,%ZMM5

  (239) 0x43528a VMULPD	%ZMM7,%ZMM10,%ZMM10

  (239) 0x435290 VDIVPD	%ZMM22,%ZMM5,%ZMM1

  (239) 0x435296 VADDPD	%ZMM8,%ZMM3,%ZMM5

  (239) 0x43529c VMULPD	%ZMM13,%ZMM22,%ZMM22

  (239) 0x4352a2 VSUBPD	%ZMM3,%ZMM8,%ZMM3

  (239) 0x4352a8 VMULPD	%ZMM4,%ZMM5,%ZMM5

  (239) 0x4352ae VMINPD	%ZMM23,%ZMM4,%ZMM4

  (239) 0x4352b4 VMOVUPD	%ZMM10,0x40(%R8,%RAX,1)

  (239) 0x4352bc VDIVPD	%ZMM24,%ZMM5,%ZMM5

  (239) 0x4352c2 VADDPD	%ZMM5,%ZMM1,%ZMM1

  (239) 0x4352c8 VMULPD	%ZMM22,%ZMM1,%ZMM5

  (239) 0x4352ce VMINPD	%ZMM4,%ZMM5,%ZMM1

  (239) 0x4352d4 VMULPD	%ZMM21,%ZMM3,%ZMM5

  (239) 0x4352da VMOVAPD	%ZMM20,%ZMM4

  (239) 0x4352e0 VFMADD231PD	%ZMM5,%ZMM1,%ZMM4{%K3}

  (239) 0x4352e6 VMULPD	%ZMM19,%ZMM4,%ZMM0

  (239) 0x4352ec VMOVUPD	%ZMM0,(%R8,%RAX,1)

  (239) 0x4352f3 SUB	$-0x80,%RAX

  (239) 0x4352f7 CMP	%RAX,%R13

  (239) 0x4352fa JNE	435080

(237) 0x435300 MOV	0x68(%RSP),%R11D

(237) 0x435305 MOV	%R12D,%EAX

(237) 0x435308 AND	$-0x10,%EAX

(237) 0x43530b LEA	(%RAX,%R11,1),%R8D

(237) 0x43530f ADD	%EAX,%EBX

(237) 0x435311 TEST	$0xf,%R12B

(237) 0x435315 JE	4357a0

(237) 0x43531b SUB	%EAX,%R12D

(237) 0x43531e LEA	-0x1(%R12),%R10D

(237) 0x435323 CMP	$0x6,%R10D

(237) 0x435327 JBE	435626

(237) 0x43532d MOVSXD	0x68(%RSP),%RDX

(237) 0x435332 MOV	0x58(%RSP),%R9

(237) 0x435337 MOV	0x60(%RSP),%R11

(237) 0x43533c MOV	0x70(%RSP),%R10

(237) 0x435341 LEA	(%R9,%RDX,1),%R13

(237) 0x435345 MOV	0x78(%RSP),%R9

(237) 0x43534a ADD	%RAX,%R13

(237) 0x43534d LEA	(%R11,%R13,8),%R13

(237) 0x435351 LEA	(%R9,%R10,8),%R11

(237) 0x435355 LEA	(%RDX,%RAX,1),%R9

(237) 0x435359 LEA	(%RCX,%R9,8),%R10

(237) 0x43535d MOV	%R10,0x68(%RSP)

(237) 0x435362 MOV	0x48(%RSP),%R10

(237) 0x435367 VMOVUPD	(%R13),%YMM5

(237) 0x43536d VMOVUPD	0x20(%R13),%YMM4

(237) 0x435373 VXORPD	%XMM2,%XMM2,%XMM2

(237) 0x435377 VPBROADCASTD	%R8D,%YMM15

(237) 0x43537d ADD	%R10,%RDX

(237) 0x435380 VCMPPD	$0x1,%YMM2,%YMM5,%K3

(237) 0x435387 VCMPPD	$0x1,%YMM2,%YMM4,%K2

(237) 0x43538e VPADDD	0x3a42a(%RIP),%YMM15,%YMM9

(237) 0x435396 ADD	%RAX,%RDX

(237) 0x435399 MOV	0x50(%RSP),%RAX

(237) 0x43539e VPADDD	0x3a3da(%RIP),%YMM15,%YMM0

(237) 0x4353a6 VPADDD	0x3a392(%RIP),%YMM15,%YMM1

(237) 0x4353ae LEA	(%RAX,%RDX,8),%R10

(237) 0x4353b2 VEXTRACTI32X4	$0x1,%YMM9,%XMM8

(237) 0x4353b9 MOV	$0xf,%EDX

(237) 0x4353be VPMOVSXDQ	%XMM9,%YMM14

(237) 0x4353c3 VPMOVSXDQ	%XMM8,%YMM13

(237) 0x4353c8 VEXTRACTI32X4	$0x1,%YMM0,%XMM7

(237) 0x4353cf KSHIFTLB	$0x4,%K2,%K4

(237) 0x4353d5 KMOVB	%EDX,%K0

(237) 0x4353d9 KANDB	%K0,%K3,%K1

(237) 0x4353dd KORB	%K4,%K1,%K5

(237) 0x4353e1 VPADDD	0x3a415(%RIP),%YMM15,%YMM1{%K5}

(237) 0x4353eb VMOVDQA	%XMM0,%XMM12

(237) 0x4353ef VPMOVSXDQ	%XMM0,%YMM8

(237) 0x4353f4 VPMOVSXDQ	%XMM7,%YMM11

(237) 0x4353f9 VMOVDQA	%YMM14,%YMM6

(237) 0x4353fd VMOVDQA	%YMM13,%YMM3

(237) 0x435401 LEA	(%RSI,%RDI,8),%R9

(237) 0x435405 VPMOVSXDQ	%XMM12,%YMM6{%K3}

(237) 0x43540b VPMOVSXDQ	%XMM7,%YMM3{%K2}

(237) 0x435411 VMOVDQA64	%YMM14,%YMM8{%K3}

(237) 0x435417 VMOVDQA64	%YMM13,%YMM11{%K2}

(237) 0x43541d VPERM2I128	$0x11,%YMM1,%YMM1,%YMM12

(237) 0x435423 KXNORB	%K3,%K3,%K3

(237) 0x435427 KNOTB	%K5,%K6

(237) 0x43542b KMOVB	%K3,%K7

(237) 0x43542f VPADDD	0x3a307(%RIP),%YMM15,%YMM0{%K6}

(237) 0x435439 VGATHERQPD	(%R11,%YMM6,8),%YMM19{%K7}

(237) 0x435440 KMOVB	%K3,%K2

(237) 0x435444 KMOVB	%K3,%K1

(237) 0x435448 VGATHERQPD	(%R11,%YMM3,8),%YMM13{%K2}

(237) 0x43544f VGATHERQPD	(%R9,%YMM6,8),%YMM7{%K1}

(237) 0x435456 KMOVB	%K3,%K4

(237) 0x43545a KMOVB	%K3,%K5

(237) 0x43545e VGATHERQPD	(%R9,%YMM3,8),%YMM6{%K4}

(237) 0x435465 VGATHERDPD	(%R9,%XMM1,8),%YMM10{%K5}

(237) 0x43546c KMOVB	%K3,%K6

(237) 0x435470 KMOVB	%K3,%K7

(237) 0x435474 VGATHERDPD	(%R9,%XMM12,8),%YMM1{%K6}

(237) 0x43547b VGATHERQPD	(%R9,%YMM8,8),%YMM3{%K7}

(237) 0x435482 VGATHERQPD	(%R9,%YMM11,8),%YMM8{%K3}

(237) 0x435489 VSUBPD	%YMM7,%YMM3,%YMM12

(237) 0x43548d VSUBPD	%YMM1,%YMM6,%YMM14

(237) 0x435491 VSUBPD	%YMM6,%YMM8,%YMM3

(237) 0x435495 VSUBPD	%YMM10,%YMM7,%YMM10

(237) 0x43549a MOV	0x68(%RSP),%R13

(237) 0x43549f VMULPD	%YMM3,%YMM14,%YMM1

(237) 0x4354a3 VMULPD	%YMM12,%YMM10,%YMM11

(237) 0x4354a8 VMOVUPD	0x20(%R13),%YMM15

(237) 0x4354ae VMOVUPD	(%R13),%YMM9

(237) 0x4354b4 VBROADCASTSD	0x39112(%RIP),%YMM17

(237) 0x4354be VCMPPD	$0xe,%YMM2,%YMM1,%K1

(237) 0x4354c5 VBROADCASTSD	0x39822(%RIP),%YMM1

(237) 0x4354ce VCMPPD	$0xe,%YMM2,%YMM11,%K2

(237) 0x4354d5 VANDPD	%YMM1,%YMM3,%YMM18

(237) 0x4354db VCMPPD	$0xe,%YMM2,%YMM3,%K3{%K1}

(237) 0x4354e2 VANDPD	%YMM1,%YMM4,%YMM3

(237) 0x4354e6 VDIVPD	%YMM13,%YMM3,%YMM3

(237) 0x4354eb VMOVAPD	%YMM2,%YMM13

(237) 0x4354ef KMOVB	%K2,%K5

(237) 0x4354f3 VGATHERDPD	(%RCX,%XMM0,8),%YMM13{%K5}

(237) 0x4354fa VPERM2I128	$0x11,%YMM0,%YMM0,%YMM0

(237) 0x435500 VANDPD	%YMM1,%YMM12,%YMM11

(237) 0x435504 VCMPPD	$0xe,%YMM2,%YMM12,%K4{%K2}

(237) 0x43550b KMOVB	%K1,%K6

(237) 0x43550f VBROADCASTSD	0x39fc0(%RIP),%YMM12

(237) 0x435518 VGATHERDPD	(%RCX,%XMM0,8),%YMM2{%K6}

(237) 0x43551f VBROADCASTSD	0x3a0f0(%RIP),%YMM0

(237) 0x435528 VANDPD	%YMM1,%YMM10,%YMM10

(237) 0x43552c VANDPD	%YMM1,%YMM14,%YMM14

(237) 0x435530 VANDPD	%YMM1,%YMM5,%YMM8

(237) 0x435534 VBROADCASTSD	0x3a26a(%RIP),%YMM28

(237) 0x43553e VBLENDMPD	%YMM12,%YMM17,%YMM16{%K4}

(237) 0x435544 VMOVAPD	%YMM12,%YMM17{%K3}

(237) 0x43554a KMOVB	%K2,%R11D

(237) 0x43554e KMOVB	%K1,%R9D

(237) 0x435552 AND	$0xf,%R11D

(237) 0x435556 VDIVPD	%YMM19,%YMM8,%YMM8

(237) 0x43555c AND	$0xf,%R9D

(237) 0x435560 KMOVB	%R11D,%K7

(237) 0x435565 KMOVB	%R9D,%K2

(237) 0x43556a MOV	%R12D,%EAX

(237) 0x43556d AND	$-0x8,%EAX

(237) 0x435570 ADD	%EAX,%R8D

(237) 0x435573 ADD	%EAX,%EBX

(237) 0x435575 VSUBPD	%YMM3,%YMM0,%YMM1

(237) 0x435579 VADDPD	%YMM12,%YMM3,%YMM20

(237) 0x43557f VSUBPD	%YMM3,%YMM12,%YMM3

(237) 0x435583 VMULPD	%YMM18,%YMM1,%YMM1

(237) 0x435589 VMULPD	%YMM14,%YMM20,%YMM23

(237) 0x43558f VMINPD	%YMM18,%YMM14,%YMM14

(237) 0x435595 AND	$0x7,%R12D

(237) 0x435599 VDIVPD	%YMM15,%YMM1,%YMM1

(237) 0x43559e VMULPD	%YMM28,%YMM15,%YMM15

(237) 0x4355a4 VSUBPD	%YMM8,%YMM0,%YMM0

(237) 0x4355a9 VDIVPD	%YMM2,%YMM23,%YMM2

(237) 0x4355af VADDPD	%YMM2,%YMM1,%YMM1

(237) 0x4355b3 VMULPD	%YMM15,%YMM1,%YMM2

(237) 0x4355b8 VMULPD	%YMM17,%YMM3,%YMM15

(237) 0x4355be VMULPD	%YMM11,%YMM0,%YMM3

(237) 0x4355c3 VMINPD	%YMM14,%YMM2,%YMM1

(237) 0x4355c8 VSUBPD	%YMM8,%YMM12,%YMM2

(237) 0x4355cd VADDPD	%YMM12,%YMM8,%YMM12

(237) 0x4355d2 VDIVPD	%YMM9,%YMM3,%YMM0

(237) 0x4355d7 VMULPD	%YMM28,%YMM9,%YMM9

(237) 0x4355dd VMULPD	%YMM10,%YMM12,%YMM8

(237) 0x4355e2 VMULPD	%YMM16,%YMM2,%YMM14

(237) 0x4355e8 VMINPD	%YMM11,%YMM10,%YMM10

(237) 0x4355ed VFMADD231PD	%YMM1,%YMM15,%YMM6{%K2}

(237) 0x4355f3 VMULPD	%YMM6,%YMM4,%YMM4

(237) 0x4355f7 VMOVUPD	%YMM4,0x20(%R10)

(237) 0x4355fd VDIVPD	%YMM13,%YMM8,%YMM13

(237) 0x435602 VADDPD	%YMM13,%YMM0,%YMM2

(237) 0x435607 VMULPD	%YMM9,%YMM2,%YMM3

(237) 0x43560c VMINPD	%YMM10,%YMM3,%YMM11

(237) 0x435611 VFMADD231PD	%YMM11,%YMM14,%YMM7{%K7}

(237) 0x435617 VMULPD	%YMM5,%YMM7,%YMM5

(237) 0x43561b VMOVUPD	%YMM5,(%R10)

(237) 0x435620 JE	4357a0

(237) 0x435626 MOV	0x60(%RSP),%R12

(237) 0x43562b MOV	0x58(%RSP),%R10

(237) 0x435630 MOV	0x50(%RSP),%RDX

(237) 0x435635 MOV	0x48(%RSP),%R11

(237) 0x43563a LEA	0x1(%R8),%EAX

(237) 0x43563e DEC	%EBX

(237) 0x435640 LEA	(%R12,%R10,8),%R13

(237) 0x435644 VMOVSD	0x39fcc(%RIP),%XMM11

(237) 0x43564c VMOVSD	0x3a154(%RIP),%XMM10

(237) 0x435654 CLTQ

(237) 0x435656 LEA	(%RDX,%R11,8),%R12

(237) 0x43565a VXORPD	%XMM8,%XMM8,%XMM8

(237) 0x43565f SUB	%R8D,%EBX

(237) 0x435662 JMP	435744

0x435667 NOPW	(%RAX,%RAX,1)

  (238) 0x435670 LEA	-0x2(%RAX),%EDX

  (238) 0x435673 MOV	%RAX,%R9

  (238) 0x435676 MOVSXD	%EDX,%R10

  (238) 0x435679 ADD	%RDI,%R9

  (238) 0x43567c LEA	(%RDI,%R8,1),%R11

  (238) 0x435680 VMOVSD	(%RSI,%R11,8),%XMM3

  (238) 0x435686 VMOVSD	(%RSI,%R9,8),%XMM15

  (238) 0x43568c MOVSXD	%EDX,%RDX

  (238) 0x43568f ADD	%RDI,%RDX

  (238) 0x435692 VSUBSD	(%RSI,%RDX,8),%XMM3,%XMM6

  (238) 0x435697 VSUBSD	%XMM3,%XMM15,%XMM14

  (238) 0x43569b VMULSD	%XMM14,%XMM6,%XMM0

  (238) 0x4356a0 VCOMISD	%XMM8,%XMM0

  (238) 0x4356a5 JBE	43572d

  (238) 0x4356ab VCOMISD	%XMM14,%XMM8

  (238) 0x4356b0 VANDPD	%XMM26,%XMM6,%XMM13

  (238) 0x4356b6 VANDPD	%XMM26,%XMM14,%XMM2

  (238) 0x4356bc JAE	435788

  (238) 0x4356c2 VMOVAPD	%XMM30,%XMM9

  (238) 0x4356c8 VMOVAPD	%XMM30,%XMM12

  (238) 0x4356ce MOV	0x70(%RSP),%R9

  (238) 0x4356d3 MOV	0x78(%RSP),%R11

  (238) 0x4356d8 VANDPD	%XMM26,%XMM1,%XMM5

  (238) 0x4356de ADD	%R9,%R8

  (238) 0x4356e1 VDIVSD	(%R11,%R8,8),%XMM5,%XMM4

  (238) 0x4356e7 VSUBSD	%XMM4,%XMM11,%XMM0

  (238) 0x4356eb VADDSD	%XMM9,%XMM4,%XMM6

  (238) 0x4356f0 VMOVSD	-0x8(%RCX,%RAX,8),%XMM7

  (238) 0x4356f6 VMULSD	%XMM2,%XMM0,%XMM5

  (238) 0x4356fa VMULSD	%XMM13,%XMM6,%XMM15

  (238) 0x4356ff VMINSD	%XMM2,%XMM13,%XMM13

  (238) 0x435703 VSUBSD	%XMM4,%XMM9,%XMM9

  (238) 0x435707 VDIVSD	%XMM7,%XMM5,%XMM6

  (238) 0x43570b VMULSD	%XMM10,%XMM7,%XMM7

  (238) 0x435710 VDIVSD	(%RCX,%R10,8),%XMM15,%XMM14

  (238) 0x435716 VADDSD	%XMM6,%XMM14,%XMM15

  (238) 0x43571a VMULSD	%XMM7,%XMM15,%XMM14

  (238) 0x43571e VMINSD	%XMM13,%XMM14,%XMM2

  (238) 0x435723 VMULSD	%XMM9,%XMM2,%XMM4

  (238) 0x435728 VFMADD231SD	%XMM12,%XMM4,%XMM3

  (238) 0x43572d VMULSD	%XMM3,%XMM1,%XMM1

  (238) 0x435731 VMOVSD	%XMM1,-0x8(%R12,%RAX,8)

  (238) 0x435738 INC	%RAX

  (238) 0x43573b LEA	(%RBX,%RAX,1),%R8D

  (238) 0x43573f CMP	%R15D,%R8D

  (238) 0x435742 JAE	4357a0

  (238) 0x435744 VMOVSD	-0x8(%R13,%RAX,8),%XMM1

  (238) 0x43574b LEA	-0x1(%RAX),%R8

  (238) 0x43574f VCOMISD	%XMM1,%XMM8

  (238) 0x435753 JBE	435670

  (238) 0x435759 MOV	%R8,%R9

  (238) 0x43575c MOVSXD	%EAX,%R10

  (238) 0x43575f LEA	0x1(%RAX),%EDX

  (238) 0x435762 MOV	%RAX,%R8

  (238) 0x435765 JMP	435679

0x43576a NOPW	(%RAX,%RAX,1)

0x435770 VZEROUPPER

0x435773 LEA	-0x28(%RBP),%RSP

0x435777 POP	%RBX

0x435778 POP	%R12

0x43577a POP	%R13

0x43577c POP	%R14

0x43577e POP	%R15

0x435780 POP	%RBP

0x435781 RET

0x435782 NOPW	(%RAX,%RAX,1)

  (238) 0x435788 VMOVSD	0x38e40(%RIP),%XMM12

  (238) 0x435790 VMOVSD	0x39d40(%RIP),%XMM9

  (238) 0x435798 JMP	4356ce

0x43579d NOPL	(%RAX)

(237) 0x4357a0 MOV	%R15D,%EBX

(237) 0x4357a3 INC	%R14

(237) 0x4357a6 CMP	%R14D,0x40(%RSP)

(237) 0x4357ab JLE	435770

(237) 0x4357ad MOV	0x38(%RSP),%ECX

(237) 0x4357b1 MOV	0x3c(%RSP),%R10D

(237) 0x4357b6 MOV	0x44(%RSP),%R12D

(237) 0x4357bb MOV	%R10D,0x68(%RSP)

(237) 0x4357c0 SUB	%EBX,%ECX

(237) 0x4357c2 JMP	434f50

0x4357c7 NOPW	(%RAX,%RAX,1)

(237) 0x4357d0 MOV	0x68(%RSP),%R8D

(237) 0x4357d5 XOR	%EAX,%EAX

(237) 0x4357d7 JMP	43531b

0x4357dc INC	%ECX

0x4357de XOR	%EDX,%EDX

0x4357e0 JMP	434ecc

0x4357e5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.67	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.33	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.17 to 2.17 cycles (7.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.17 to 11.97 cycles (1.35x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.17 to 15.00 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:125

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	87
nb uops	97
loop length	327
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	1
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	8.00	7.33	7.33	9.00	5.60	5.50	9.00	9.00	9.00	5.40	7.33
cycles	5.50	11.70	7.33	7.33	9.00	5.60	5.50	9.00	9.00	9.00	5.40	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.17
Dispatch	11.70
DIV/SQRT	12.00
Overall L1	16.17

Vectorization ratios

INT

all	7%
load	14%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	12%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	12%
load	23%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	21%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

4% of peak load performance is reached (9.15 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RBX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R12D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x44(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4357dc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x98c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RBX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x44(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x3c(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ 0x39dce(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3a5ac(%RIP),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQA32 0x3a88a(%RIP),%ZMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB %R10D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 434ecc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x7c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.17 to 2.17 cycles (7.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.17 to 15.00 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:125

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 148 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	87
nb uops	97
loop length	327
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	1
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	8.00	7.33	7.33	9.00	5.60	5.50	9.00	9.00	9.00	5.40	7.33
cycles	5.50	11.70	7.33	7.33	9.00	5.60	5.50	9.00	9.00	9.00	5.40	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	16.17
Dispatch	11.70
DIV/SQRT	12.00
Overall L1	16.17

Vectorization ratios

INT

all	7%
load	14%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	12%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	12%
load	23%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	21%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

4% of peak load performance is reached (9.15 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RBX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R12D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x44(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R14D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4357dc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x98c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RBX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 435773 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x923>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x44(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x3c(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ 0x39dce(%RIP),%XMM26	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3a5ac(%RIP),%XMM30	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQA32 0x3a88a(%RIP),%ZMM31	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV %R14,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R9,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB %R10D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 434ecc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x7c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.23	1.22
▼Loop 237 - advec_mom.cpp:110-139 - exec–	0.00	0.01
○Loop 239 - advec_mom.cpp:114-139 - exec	4.23	1.22
○Loop 238 - advec_mom.cpp:114-139 - exec	0.00	0.00

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Code clean check

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code