OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:218-221 [...]	Coverage (incl. loops): 4.35% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 218 - 221

--------------------------------------------------------------------------------

218: #pragma omp parallel for simd collapse(2)

219:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

220:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

221:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x434900 PUSH	%RBP

0x434901 MOV	%RSP,%RBP

0x434904 PUSH	%R15

0x434906 PUSH	%R14

0x434908 MOV	%RDI,%R14

0x43490b PUSH	%R13

0x43490d PUSH	%R12

0x43490f PUSH	%RBX

0x434910 AND	$-0x40,%RSP

0x434914 ADD	$-0x80,%RSP

0x434918 MOV	0x28(%RDI),%EAX

0x43491b MOV	0x2c(%RDI),%EDX

0x43491e MOV	0x20(%RDI),%ECX

0x434921 ADD	$0x3,%EDX

0x434924 LEA	0x1(%RCX),%EDI

0x434927 LEA	0x1(%RAX),%R12D

0x43492b MOV	%EDX,0x34(%RSP)

0x43492f MOV	%EDI,0x30(%RSP)

0x434933 MOV	0x24(%R14),%EBX

0x434937 CMP	%EDX,%R12D

0x43493a JGE	434e23

0x434940 LEA	0x3(%RBX),%R15D

0x434944 MOV	%EDX,%EBX

0x434946 SUB	%R12D,%EBX

0x434949 CMP	%R15D,%EDI

0x43494c JGE	434e23

0x434952 MOV	%R15D,%ESI

0x434955 SUB	%EDI,%ESI

0x434957 MOV	%ESI,0x78(%RSP)

0x43495b CALL	404630 <omp_get_num_threads@plt>

0x434960 MOV	%EAX,%R13D

0x434963 CALL	404520 <omp_get_thread_num@plt>

0x434968 MOV	%EAX,%R8D

0x43496b MOV	0x78(%RSP),%EAX

0x43496f XOR	%EDX,%EDX

0x434971 IMUL	%EBX,%EAX

0x434974 DIV	%R13D

0x434977 MOV	%EAX,%ESI

0x434979 CMP	%EDX,%R8D

0x43497c JB	434e42

0x434982 IMUL	%ESI,%R8D

0x434986 LEA	(%R8,%RDX,1),%R11D

0x43498a LEA	(%RSI,%R11,1),%R9D

0x43498e MOV	%R9D,0x2c(%RSP)

0x434993 CMP	%R9D,%R11D

0x434996 JAE	434e23

0x43499c MOV	%R11D,%EAX

0x43499f XOR	%EDX,%EDX

0x4349a1 DIVL	0x78(%RSP)

0x4349a5 MOV	0x10(%R14),%RBX

0x4349a9 MOV	0x18(%R14),%R13

0x4349ad MOV	0x30(%RSP),%R10D

0x4349b2 MOV	%RBX,0x18(%RSP)

0x4349b7 MOV	%R13,0x10(%RSP)

0x4349bc MOV	%R15D,%ECX

0x4349bf MOV	(%R14),%R15

0x4349c2 MOV	0x8(%R14),%R14

0x4349c6 MOV	%R15,0x20(%RSP)

0x4349cb MOV	%R14,0x8(%RSP)

0x4349d0 LEA	(%RDX,%R10,1),%EDI

0x4349d4 ADD	%R12D,%EAX

0x4349d7 SUB	%EDI,%ECX

0x4349d9 MOVSXD	%EAX,%R12

0x4349dc NOPL	(%RAX)

(235) 0x4349e0 CMP	%ECX,%ESI

(235) 0x4349e2 CMOVBE	%ESI,%ECX

(235) 0x4349e5 LEA	(%R11,%RCX,1),%ESI

(235) 0x4349e9 MOV	%ESI,0x7c(%RSP)

(235) 0x4349ed CMP	%ESI,%R11D

(235) 0x4349f0 JAE	434dfd

(235) 0x4349f6 MOV	0x20(%RSP),%R8

(235) 0x4349fb MOV	0x18(%RSP),%R9

(235) 0x434a00 MOV	0x10(%RSP),%RAX

(235) 0x434a05 MOV	0x8(%RSP),%R15

(235) 0x434a0a MOV	(%RAX),%R13

(235) 0x434a0d MOV	(%R8),%RBX

(235) 0x434a10 MOV	(%R9),%RSI

(235) 0x434a13 MOV	0x10(%RAX),%R14

(235) 0x434a17 LEA	-0x1(%R12),%EDX

(235) 0x434a1c MOV	0x10(%R15),%RAX

(235) 0x434a20 MOV	(%R15),%R15

(235) 0x434a23 MOV	0x10(%R8),%R10

(235) 0x434a27 MOV	0x10(%R9),%R8

(235) 0x434a2b MOVSXD	%EDX,%R9

(235) 0x434a2e IMUL	%R13,%R9

(235) 0x434a32 IMUL	%R12,%RBX

(235) 0x434a36 IMUL	%R12,%RSI

(235) 0x434a3a IMUL	%R12,%R13

(235) 0x434a3e IMUL	%R12,%R15

(235) 0x434a42 MOV	%RAX,0x70(%RSP)

(235) 0x434a47 LEA	-0x1(%RCX),%EAX

(235) 0x434a4a MOV	%R10,0x68(%RSP)

(235) 0x434a4f MOV	%RBX,0x38(%RSP)

(235) 0x434a54 MOV	%R8,0x48(%RSP)

(235) 0x434a59 MOV	%RSI,0x40(%RSP)

(235) 0x434a5e MOV	%R9,0x50(%RSP)

(235) 0x434a63 MOV	%R13,0x58(%RSP)

(235) 0x434a68 MOV	%R15,0x60(%RSP)

(235) 0x434a6d CMP	$0x6,%EAX

(235) 0x434a70 JBE	434e38

(235) 0x434a76 MOVSXD	%EDI,%RAX

(235) 0x434a79 LEA	(%RBX,%RAX,1),%RBX

(235) 0x434a7d ADD	%RAX,%RSI

(235) 0x434a80 LEA	(%R10,%RBX,8),%RDX

(235) 0x434a84 LEA	(%R8,%RSI,8),%R10

(235) 0x434a88 LEA	(%R13,%RAX,1),%RSI

(235) 0x434a8d MOV	0x70(%RSP),%R13

(235) 0x434a92 LEA	(%R9,%RAX,1),%R8

(235) 0x434a96 ADD	%R15,%RAX

(235) 0x434a99 LEA	(%R14,%RSI,8),%R9

(235) 0x434a9d LEA	(%R13,%RAX,8),%RSI

(235) 0x434aa2 MOV	%ECX,%R13D

(235) 0x434aa5 SHR	$0x3,%R13D

(235) 0x434aa9 SAL	$0x6,%R13

(235) 0x434aad LEA	-0x40(%R13),%RBX

(235) 0x434ab1 SHR	$0x6,%RBX

(235) 0x434ab5 INC	%RBX

(235) 0x434ab8 LEA	(%R14,%R8,8),%R8

(235) 0x434abc XOR	%EAX,%EAX

(235) 0x434abe AND	$0x3,%EBX

(235) 0x434ac1 JE	434b61

(235) 0x434ac7 CMP	$0x1,%RBX

(235) 0x434acb JE	434b2a

(235) 0x434acd CMP	$0x2,%RBX

(235) 0x434ad1 JE	434afc

(235) 0x434ad3 VMOVUPD	(%R10),%ZMM0

(235) 0x434ad9 VMOVUPD	(%R9),%ZMM5

(235) 0x434adf MOV	$0x40,%EAX

(235) 0x434ae4 VFMSUB132PD	(%RDX),%ZMM5,%ZMM0

(235) 0x434aea VADDPD	(%R8),%ZMM0,%ZMM1

(235) 0x434af0 VDIVPD	(%RSI),%ZMM1,%ZMM2

(235) 0x434af6 VMOVUPD	%ZMM2,(%RDX)

(235) 0x434afc VMOVUPD	(%R10,%RAX,1),%ZMM3

(235) 0x434b03 VMOVUPD	(%R9,%RAX,1),%ZMM6

(235) 0x434b0a VFMSUB132PD	(%RDX,%RAX,1),%ZMM6,%ZMM3

(235) 0x434b11 VADDPD	(%R8,%RAX,1),%ZMM3,%ZMM4

(235) 0x434b18 VDIVPD	(%RSI,%RAX,1),%ZMM4,%ZMM7

(235) 0x434b1f VMOVUPD	%ZMM7,(%RDX,%RAX,1)

(235) 0x434b26 ADD	$0x40,%RAX

(235) 0x434b2a VMOVUPD	(%R10,%RAX,1),%ZMM8

(235) 0x434b31 VMOVUPD	(%R9,%RAX,1),%ZMM9

(235) 0x434b38 VFMSUB132PD	(%RDX,%RAX,1),%ZMM9,%ZMM8

(235) 0x434b3f VADDPD	(%R8,%RAX,1),%ZMM8,%ZMM10

(235) 0x434b46 VDIVPD	(%RSI,%RAX,1),%ZMM10,%ZMM11

(235) 0x434b4d VMOVUPD	%ZMM11,(%RDX,%RAX,1)

(235) 0x434b54 ADD	$0x40,%RAX

(235) 0x434b58 CMP	%RAX,%R13

(235) 0x434b5b JE	434c34

(235) 0x434b61 MOV	0x7c(%RSP),%R15D

  (236) 0x434b66 VMOVUPD	(%R10,%RAX,1),%ZMM12

  (236) 0x434b6d VMOVUPD	(%R9,%RAX,1),%ZMM13

  (236) 0x434b74 VFMSUB132PD	(%RDX,%RAX,1),%ZMM13,%ZMM12

  (236) 0x434b7b VADDPD	(%R8,%RAX,1),%ZMM12,%ZMM14

  (236) 0x434b82 VDIVPD	(%RSI,%RAX,1),%ZMM14,%ZMM15

  (236) 0x434b89 VMOVUPD	%ZMM15,(%RDX,%RAX,1)

  (236) 0x434b90 VMOVUPD	0x40(%R10,%RAX,1),%ZMM0

  (236) 0x434b98 VMOVUPD	0x40(%R9,%RAX,1),%ZMM5

  (236) 0x434ba0 VFMSUB132PD	0x40(%RDX,%RAX,1),%ZMM5,%ZMM0

  (236) 0x434ba8 VADDPD	0x40(%R8,%RAX,1),%ZMM0,%ZMM1

  (236) 0x434bb0 VDIVPD	0x40(%RSI,%RAX,1),%ZMM1,%ZMM2

  (236) 0x434bb8 VMOVUPD	%ZMM2,0x40(%RDX,%RAX,1)

  (236) 0x434bc0 VMOVUPD	0x80(%R10,%RAX,1),%ZMM6

  (236) 0x434bc8 VMOVUPD	0x80(%R9,%RAX,1),%ZMM3

  (236) 0x434bd0 VFMSUB132PD	0x80(%RDX,%RAX,1),%ZMM3,%ZMM6

  (236) 0x434bd8 VADDPD	0x80(%R8,%RAX,1),%ZMM6,%ZMM4

  (236) 0x434be0 VDIVPD	0x80(%RSI,%RAX,1),%ZMM4,%ZMM7

  (236) 0x434be8 VMOVUPD	%ZMM7,0x80(%RDX,%RAX,1)

  (236) 0x434bf0 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM8

  (236) 0x434bf8 VMOVUPD	0xc0(%R9,%RAX,1),%ZMM9

  (236) 0x434c00 VFMSUB132PD	0xc0(%RDX,%RAX,1),%ZMM9,%ZMM8

  (236) 0x434c08 VADDPD	0xc0(%R8,%RAX,1),%ZMM8,%ZMM10

  (236) 0x434c10 VDIVPD	0xc0(%RSI,%RAX,1),%ZMM10,%ZMM11

  (236) 0x434c18 VMOVUPD	%ZMM11,0xc0(%RDX,%RAX,1)

  (236) 0x434c20 ADD	$0x100,%RAX

  (236) 0x434c26 CMP	%RAX,%R13

  (236) 0x434c29 JNE	434b66

(235) 0x434c2f MOV	%R15D,0x7c(%RSP)

(235) 0x434c34 MOV	%ECX,%R13D

(235) 0x434c37 AND	$-0x8,%R13D

(235) 0x434c3b LEA	(%R13,%RDI,1),%EDX

(235) 0x434c40 ADD	%R13D,%R11D

(235) 0x434c43 TEST	$0x7,%CL

(235) 0x434c46 JE	434df8

(235) 0x434c4c SUB	%R13D,%ECX

(235) 0x434c4f LEA	-0x1(%RCX),%R10D

(235) 0x434c53 CMP	$0x2,%R10D

(235) 0x434c57 JBE	434ce7

(235) 0x434c5d MOV	0x38(%RSP),%R8

(235) 0x434c62 MOVSXD	%EDI,%RDI

(235) 0x434c65 LEA	(%R8,%RDI,1),%R9

(235) 0x434c69 MOV	0x68(%RSP),%RSI

(235) 0x434c6e MOV	0x60(%RSP),%RBX

(235) 0x434c73 ADD	%R13,%R9

(235) 0x434c76 LEA	(%RSI,%R9,8),%R15

(235) 0x434c7a LEA	(%RBX,%RDI,1),%R10

(235) 0x434c7e MOV	0x50(%RSP),%RAX

(235) 0x434c83 MOV	0x40(%RSP),%R9

(235) 0x434c88 MOV	0x58(%RSP),%RBX

(235) 0x434c8d LEA	(%RAX,%RDI,1),%R8

(235) 0x434c91 LEA	(%R9,%RDI,1),%RSI

(235) 0x434c95 ADD	%RBX,%RDI

(235) 0x434c98 ADD	%R13,%RDI

(235) 0x434c9b VMOVUPD	(%R15),%YMM12

(235) 0x434ca0 VMOVUPD	(%R14,%RDI,8),%YMM13

(235) 0x434ca6 ADD	%R13,%R10

(235) 0x434ca9 ADD	%R13,%R8

(235) 0x434cac ADD	%R13,%RSI

(235) 0x434caf MOV	0x48(%RSP),%R13

(235) 0x434cb4 MOV	0x70(%RSP),%RDI

(235) 0x434cb9 VFMSUB132PD	(%R13,%RSI,8),%YMM13,%YMM12

(235) 0x434cc0 VADDPD	(%R14,%R8,8),%YMM12,%YMM14

(235) 0x434cc6 VDIVPD	(%RDI,%R10,8),%YMM14,%YMM15

(235) 0x434ccc VMOVUPD	%YMM15,(%R15)

(235) 0x434cd1 MOV	%ECX,%R15D

(235) 0x434cd4 AND	$-0x4,%R15D

(235) 0x434cd8 ADD	%R15D,%EDX

(235) 0x434cdb ADD	%R15D,%R11D

(235) 0x434cde AND	$0x3,%ECX

(235) 0x434ce1 JE	434df8

(235) 0x434ce7 MOV	0x38(%RSP),%RBX

(235) 0x434cec MOVSXD	%EDX,%RAX

(235) 0x434cef MOV	0x68(%RSP),%R10

(235) 0x434cf4 LEA	(%RBX,%RAX,1),%RCX

(235) 0x434cf8 LEA	(%R10,%RCX,8),%RCX

(235) 0x434cfc MOV	0x58(%RSP),%R13

(235) 0x434d01 MOV	0x40(%RSP),%R10

(235) 0x434d06 MOV	0x48(%RSP),%R15

(235) 0x434d0b LEA	(%R10,%RAX,1),%R8

(235) 0x434d0f LEA	(%R13,%RAX,1),%RDI

(235) 0x434d14 VMOVSD	(%R15,%R8,8),%XMM0

(235) 0x434d1a VMOVSD	(%R14,%RDI,8),%XMM5

(235) 0x434d20 MOV	0x50(%RSP),%R9

(235) 0x434d25 VFMSUB132SD	(%RCX),%XMM5,%XMM0

(235) 0x434d2a LEA	(%R9,%RAX,1),%RSI

(235) 0x434d2e MOV	0x70(%RSP),%R8

(235) 0x434d33 VADDSD	(%R14,%RSI,8),%XMM0,%XMM1

(235) 0x434d39 MOV	0x60(%RSP),%RSI

(235) 0x434d3e ADD	%RSI,%RAX

(235) 0x434d41 VDIVSD	(%R8,%RAX,8),%XMM1,%XMM2

(235) 0x434d47 VMOVSD	%XMM2,(%RCX)

(235) 0x434d4b MOV	0x7c(%RSP),%ECX

(235) 0x434d4f LEA	0x1(%R11),%EAX

(235) 0x434d53 CMP	%ECX,%EAX

(235) 0x434d55 JAE	434df8

(235) 0x434d5b LEA	0x1(%RDX),%EAX

(235) 0x434d5e CLTQ

(235) 0x434d60 MOV	0x68(%RSP),%RDI

(235) 0x434d65 LEA	(%RBX,%RAX,1),%RSI

(235) 0x434d69 LEA	(%RDI,%RSI,8),%RCX

(235) 0x434d6d LEA	(%R10,%RAX,1),%R8

(235) 0x434d71 LEA	(%R13,%RAX,1),%RDI

(235) 0x434d76 VMOVSD	(%R15,%R8,8),%XMM6

(235) 0x434d7c VMOVSD	(%R14,%RDI,8),%XMM3

(235) 0x434d82 LEA	(%R9,%RAX,1),%RSI

(235) 0x434d86 VFMSUB132SD	(%RCX),%XMM3,%XMM6

(235) 0x434d8b MOV	0x60(%RSP),%R8

(235) 0x434d90 ADD	$0x2,%R11D

(235) 0x434d94 ADD	%R8,%RAX

(235) 0x434d97 VADDSD	(%R14,%RSI,8),%XMM6,%XMM4

(235) 0x434d9d MOV	0x70(%RSP),%RSI

(235) 0x434da2 VDIVSD	(%RSI,%RAX,8),%XMM4,%XMM7

(235) 0x434da7 MOV	0x7c(%RSP),%EAX

(235) 0x434dab VMOVSD	%XMM7,(%RCX)

(235) 0x434daf CMP	%EAX,%R11D

(235) 0x434db2 JAE	434df8

(235) 0x434db4 ADD	$0x2,%EDX

(235) 0x434db7 MOVSXD	%EDX,%R11

(235) 0x434dba ADD	%R11,%R10

(235) 0x434dbd MOV	0x68(%RSP),%RDX

(235) 0x434dc2 ADD	%R11,%R13

(235) 0x434dc5 VMOVSD	(%R14,%R13,8),%XMM9

(235) 0x434dcb VMOVSD	(%R15,%R10,8),%XMM8

(235) 0x434dd1 ADD	%R11,%RBX

(235) 0x434dd4 LEA	(%RDX,%RBX,8),%RAX

(235) 0x434dd8 VFMSUB132SD	(%RAX),%XMM9,%XMM8

(235) 0x434ddd ADD	%R11,%R9

(235) 0x434de0 ADD	%R11,%R8

(235) 0x434de3 VADDSD	(%R14,%R9,8),%XMM8,%XMM10

(235) 0x434de9 MOV	0x70(%RSP),%R14

(235) 0x434dee VDIVSD	(%R14,%R8,8),%XMM10,%XMM11

(235) 0x434df4 VMOVSD	%XMM11,(%RAX)

(235) 0x434df8 MOV	0x7c(%RSP),%R11D

(235) 0x434dfd INC	%R12

(235) 0x434e00 CMP	%R12D,0x34(%RSP)

(235) 0x434e05 JLE	434e20

(235) 0x434e07 MOV	0x2c(%RSP),%ESI

(235) 0x434e0b MOV	0x78(%RSP),%ECX

(235) 0x434e0f MOV	0x30(%RSP),%EDI

(235) 0x434e13 SUB	%R11D,%ESI

(235) 0x434e16 JMP	4349e0

0x434e1b NOPL	(%RAX,%RAX,1)

0x434e20 VZEROUPPER

0x434e23 LEA	-0x28(%RBP),%RSP

0x434e27 POP	%RBX

0x434e28 POP	%R12

0x434e2a POP	%R13

0x434e2c POP	%R14

0x434e2e POP	%R15

0x434e30 POP	%RBP

0x434e31 RET

0x434e32 NOPW	(%RAX,%RAX,1)

(235) 0x434e38 MOV	%EDI,%EDX

(235) 0x434e3a XOR	%R13D,%R13D

(235) 0x434e3d JMP	434c4c

0x434e42 INC	%ESI

0x434e44 XOR	%EDX,%EDX

0x434e46 JMP	434982

0x434e4b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.83 to 3.00 cycles (4.94x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.83 to 13.67 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	79
nb uops	89
loop length	267
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RCX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RBX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 434e42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x542>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R11,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 434982 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.83 to 13.67 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	79
nb uops	89
loop length	267
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RCX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x34(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RBX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 434e42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x542>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R11,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 434e23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 434982 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.35	1.26
▼Loop 235 - advec_mom.cpp:220-221 - exec–	0.00	0.01
○Loop 236 - advec_mom.cpp:221-221 - exec	4.35	1.25

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Vectorization

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code