OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:157-160 [...]	Coverage (incl. loops): 0.99% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 157 - 160

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

159:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

160:           node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x434440 PUSH	%RBP

0x434441 MOV	%RSP,%RBP

0x434444 PUSH	%R15

0x434446 PUSH	%R14

0x434448 MOV	%RDI,%R14

0x43444b PUSH	%R13

0x43444d PUSH	%R12

0x43444f PUSH	%RBX

0x434450 AND	$-0x40,%RSP

0x434454 SUB	$0x40,%RSP

0x434458 MOV	0x18(%RDI),%EAX

0x43445b MOV	0x1c(%RDI),%EDX

0x43445e MOV	0x10(%RDI),%EBX

0x434461 ADD	$0x4,%EDX

0x434464 LEA	0x1(%RBX),%EDI

0x434467 LEA	-0x1(%RAX),%R13D

0x43446b MOV	%EDX,0x20(%RSP)

0x43446f MOV	%EDI,0x1c(%RSP)

0x434473 MOV	0x14(%R14),%ECX

0x434477 CMP	%EDX,%R13D

0x43447a JGE	4348d3

0x434480 MOV	%EDX,%EBX

0x434482 LEA	0x3(%RCX),%R15D

0x434486 SUB	%R13D,%EBX

0x434489 CMP	%R15D,%EDI

0x43448c JGE	4348d3

0x434492 MOV	%R15D,%ESI

0x434495 SUB	%EDI,%ESI

0x434497 MOV	%ESI,0x24(%RSP)

0x43449b CALL	404630 <omp_get_num_threads@plt>

0x4344a0 MOV	%EAX,%R12D

0x4344a3 CALL	404520 <omp_get_thread_num@plt>

0x4344a8 MOV	%EAX,%R8D

0x4344ab MOV	0x24(%RSP),%EAX

0x4344af XOR	%EDX,%EDX

0x4344b1 IMUL	%EBX,%EAX

0x4344b4 DIV	%R12D

0x4344b7 MOV	%EAX,%EDI

0x4344b9 CMP	%EDX,%R8D

0x4344bc JB	4348f3

0x4344c2 IMUL	%EDI,%R8D

0x4344c6 LEA	(%R8,%RDX,1),%R12D

0x4344ca LEA	(%RDI,%R12,1),%R9D

0x4344ce MOV	%R9D,0x18(%RSP)

0x4344d3 CMP	%R9D,%R12D

0x4344d6 JAE	4348d3

0x4344dc MOV	%R12D,%EAX

0x4344df XOR	%EDX,%EDX

0x4344e1 DIVL	0x24(%RSP)

0x4344e5 MOV	0x1c(%RSP),%R10D

0x4344ea MOV	(%R14),%R11

0x4344ed VMOVSD	0x3b2ab(%RIP),%XMM3

0x4344f5 MOV	0x8(%R14),%R14

0x4344f9 MOV	%R11,0x10(%RSP)

0x4344fe MOV	%R14,0x8(%RSP)

0x434503 VBROADCASTSD	%XMM3,%YMM4

0x434508 VBROADCASTSD	%XMM3,%ZMM1

0x43450e ADD	%EDX,%R10D

0x434511 MOV	%R10D,0x3c(%RSP)

0x434516 ADD	%R13D,%EAX

0x434519 SUB	%R10D,%R15D

0x43451c MOVSXD	%EAX,%R14

0x43451f NOP

(233) 0x434520 CMP	%R15D,%EDI

(233) 0x434523 MOV	%R15D,%EDX

(233) 0x434526 CMOVBE	%EDI,%EDX

(233) 0x434529 LEA	(%R12,%RDX,1),%R15D

(233) 0x43452d MOV	%R15D,0x38(%RSP)

(233) 0x434532 CMP	%R15D,%R12D

(233) 0x434535 JAE	4348a4

(233) 0x43453b MOV	0x10(%RSP),%R13

(233) 0x434540 MOV	0x8(%RSP),%RCX

(233) 0x434545 MOV	(%R13),%RBX

(233) 0x434549 MOV	(%RCX),%R11

(233) 0x43454c MOV	%RBX,%R15

(233) 0x43454f IMUL	%R14,%R15

(233) 0x434553 IMUL	%R14,%R11

(233) 0x434557 MOV	0x10(%RCX),%R8

(233) 0x43455b LEA	-0x1(%RDX),%ESI

(233) 0x43455e MOV	%R8,0x28(%RSP)

(233) 0x434563 MOV	%R11,0x30(%RSP)

(233) 0x434568 MOV	0x10(%R13),%RDI

(233) 0x43456c ADD	%R15,%RBX

(233) 0x43456f CMP	$0x6,%ESI

(233) 0x434572 JBE	4348e8

(233) 0x434578 MOVSXD	0x3c(%RSP),%R13

(233) 0x43457d XOR	%EAX,%EAX

(233) 0x43457f LEA	(%R15,%R13,1),%RSI

(233) 0x434583 LEA	(%RBX,%R13,1),%RCX

(233) 0x434587 ADD	%R11,%R13

(233) 0x43458a LEA	(%R8,%R13,8),%R8

(233) 0x43458e MOV	%EDX,%R13D

(233) 0x434591 SHR	$0x3,%R13D

(233) 0x434595 SAL	$0x6,%R13

(233) 0x434599 LEA	-0x40(%R13),%R11

(233) 0x43459d SHR	$0x6,%R11

(233) 0x4345a1 SAL	$0x3,%RSI

(233) 0x4345a5 SAL	$0x3,%RCX

(233) 0x4345a9 INC	%R11

(233) 0x4345ac LEA	-0x8(%RDI,%RSI,1),%R10

(233) 0x4345b1 LEA	-0x8(%RDI,%RCX,1),%R9

(233) 0x4345b6 ADD	%RDI,%RSI

(233) 0x4345b9 ADD	%RDI,%RCX

(233) 0x4345bc AND	$0x3,%R11D

(233) 0x4345c0 JE	434670

(233) 0x4345c6 CMP	$0x1,%R11

(233) 0x4345ca JE	434634

(233) 0x4345cc CMP	$0x2,%R11

(233) 0x4345d0 JE	434601

(233) 0x4345d2 VMOVUPD	(%R10),%ZMM0

(233) 0x4345d8 VMOVUPD	(%R9),%ZMM2

(233) 0x4345de VADDPD	(%RSI),%ZMM0,%ZMM5

(233) 0x4345e4 VADDPD	(%RCX),%ZMM2,%ZMM6

(233) 0x4345ea MOV	$0x40,%EAX

(233) 0x4345ef VADDPD	%ZMM6,%ZMM5,%ZMM7

(233) 0x4345f5 VMULPD	%ZMM1,%ZMM7,%ZMM8

(233) 0x4345fb VMOVUPD	%ZMM8,(%R8)

(233) 0x434601 VMOVUPD	(%R10,%RAX,1),%ZMM9

(233) 0x434608 VMOVUPD	(%R9,%RAX,1),%ZMM11

(233) 0x43460f VADDPD	(%RSI,%RAX,1),%ZMM9,%ZMM10

(233) 0x434616 VADDPD	(%RCX,%RAX,1),%ZMM11,%ZMM12

(233) 0x43461d VADDPD	%ZMM12,%ZMM10,%ZMM13

(233) 0x434623 VMULPD	%ZMM1,%ZMM13,%ZMM14

(233) 0x434629 VMOVUPD	%ZMM14,(%R8,%RAX,1)

(233) 0x434630 ADD	$0x40,%RAX

(233) 0x434634 VMOVUPD	(%R10,%RAX,1),%ZMM15

(233) 0x43463b VMOVUPD	(%R9,%RAX,1),%ZMM5

(233) 0x434642 VADDPD	(%RSI,%RAX,1),%ZMM15,%ZMM0

(233) 0x434649 VADDPD	(%RCX,%RAX,1),%ZMM5,%ZMM2

(233) 0x434650 VADDPD	%ZMM2,%ZMM0,%ZMM6

(233) 0x434656 VMULPD	%ZMM1,%ZMM6,%ZMM7

(233) 0x43465c VMOVUPD	%ZMM7,(%R8,%RAX,1)

(233) 0x434663 ADD	$0x40,%RAX

(233) 0x434667 CMP	%R13,%RAX

(233) 0x43466a JE	43474a

  (234) 0x434670 VMOVUPD	(%R10,%RAX,1),%ZMM8

  (234) 0x434677 VMOVUPD	(%R9,%RAX,1),%ZMM10

  (234) 0x43467e VADDPD	(%RSI,%RAX,1),%ZMM8,%ZMM9

  (234) 0x434685 VADDPD	(%RCX,%RAX,1),%ZMM10,%ZMM11

  (234) 0x43468c VADDPD	%ZMM11,%ZMM9,%ZMM12

  (234) 0x434692 VMULPD	%ZMM1,%ZMM12,%ZMM13

  (234) 0x434698 VMOVUPD	%ZMM13,(%R8,%RAX,1)

  (234) 0x43469f VMOVUPD	0x40(%R10,%RAX,1),%ZMM14

  (234) 0x4346a7 VMOVUPD	0x40(%R9,%RAX,1),%ZMM0

  (234) 0x4346af VADDPD	0x40(%RSI,%RAX,1),%ZMM14,%ZMM15

  (234) 0x4346b7 VADDPD	0x40(%RCX,%RAX,1),%ZMM0,%ZMM5

  (234) 0x4346bf VADDPD	%ZMM5,%ZMM15,%ZMM2

  (234) 0x4346c5 VMULPD	%ZMM1,%ZMM2,%ZMM6

  (234) 0x4346cb VMOVUPD	%ZMM6,0x40(%R8,%RAX,1)

  (234) 0x4346d3 VMOVUPD	0x80(%R10,%RAX,1),%ZMM7

  (234) 0x4346db VMOVUPD	0x80(%R9,%RAX,1),%ZMM9

  (234) 0x4346e3 VADDPD	0x80(%RSI,%RAX,1),%ZMM7,%ZMM8

  (234) 0x4346eb VADDPD	0x80(%RCX,%RAX,1),%ZMM9,%ZMM10

  (234) 0x4346f3 VADDPD	%ZMM10,%ZMM8,%ZMM11

  (234) 0x4346f9 VMULPD	%ZMM1,%ZMM11,%ZMM12

  (234) 0x4346ff VMOVUPD	%ZMM12,0x80(%R8,%RAX,1)

  (234) 0x434707 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM13

  (234) 0x43470f VMOVUPD	0xc0(%R9,%RAX,1),%ZMM15

  (234) 0x434717 VADDPD	0xc0(%RSI,%RAX,1),%ZMM13,%ZMM14

  (234) 0x43471f VADDPD	0xc0(%RCX,%RAX,1),%ZMM15,%ZMM0

  (234) 0x434727 VADDPD	%ZMM0,%ZMM14,%ZMM5

  (234) 0x43472d VMULPD	%ZMM1,%ZMM5,%ZMM2

  (234) 0x434733 VMOVUPD	%ZMM2,0xc0(%R8,%RAX,1)

  (234) 0x43473b ADD	$0x100,%RAX

  (234) 0x434741 CMP	%R13,%RAX

  (234) 0x434744 JNE	434670

(233) 0x43474a MOV	0x3c(%RSP),%ESI

(233) 0x43474e MOV	%EDX,%EAX

(233) 0x434750 AND	$-0x8,%EAX

(233) 0x434753 LEA	(%RAX,%RSI,1),%ECX

(233) 0x434756 ADD	%EAX,%R12D

(233) 0x434759 TEST	$0x7,%DL

(233) 0x43475c JE	43489f

(233) 0x434762 SUB	%EAX,%EDX

(233) 0x434764 LEA	-0x1(%RDX),%R10D

(233) 0x434768 CMP	$0x2,%R10D

(233) 0x43476c JBE	4347cc

(233) 0x43476e MOVSXD	0x3c(%RSP),%R9

(233) 0x434773 MOV	0x30(%RSP),%R11

(233) 0x434778 LEA	(%RBX,%R9,1),%R8

(233) 0x43477c ADD	%RAX,%R8

(233) 0x43477f VMOVUPD	-0x8(%RDI,%R8,8),%YMM6

(233) 0x434786 VMOVUPD	(%RDI,%R8,8),%YMM8

(233) 0x43478c LEA	(%R15,%R9,1),%R13

(233) 0x434790 ADD	%RAX,%R13

(233) 0x434793 VADDPD	-0x8(%RDI,%R13,8),%YMM6,%YMM7

(233) 0x43479a VADDPD	(%RDI,%R13,8),%YMM8,%YMM9

(233) 0x4347a0 ADD	%R11,%RAX

(233) 0x4347a3 MOV	0x28(%RSP),%RSI

(233) 0x4347a8 VADDPD	%YMM9,%YMM7,%YMM10

(233) 0x4347ad ADD	%R9,%RAX

(233) 0x4347b0 VMULPD	%YMM4,%YMM10,%YMM11

(233) 0x4347b4 VMOVUPD	%YMM11,(%RSI,%RAX,8)

(233) 0x4347b9 MOV	%EDX,%EAX

(233) 0x4347bb AND	$-0x4,%EAX

(233) 0x4347be ADD	%EAX,%ECX

(233) 0x4347c0 ADD	%EAX,%R12D

(233) 0x4347c3 AND	$0x3,%EDX

(233) 0x4347c6 JE	43489f

(233) 0x4347cc MOVSXD	%ECX,%RDX

(233) 0x4347cf LEA	-0x1(%RCX),%EAX

(233) 0x4347d2 CLTQ

(233) 0x4347d4 LEA	(%RBX,%RDX,1),%R9

(233) 0x4347d8 LEA	(%R15,%RAX,1),%R13

(233) 0x4347dc LEA	(%RDI,%R9,8),%R8

(233) 0x4347e0 VMOVSD	(%RDI,%R13,8),%XMM12

(233) 0x4347e6 LEA	(%RDX,%R15,1),%R10

(233) 0x4347ea VMOVSD	(%R8),%XMM14

(233) 0x4347ef LEA	(%RDI,%R10,8),%RSI

(233) 0x4347f3 ADD	%RBX,%RAX

(233) 0x4347f6 VADDSD	(%RDI,%RAX,8),%XMM12,%XMM13

(233) 0x4347fb VADDSD	(%RSI),%XMM14,%XMM15

(233) 0x4347ff MOV	0x30(%RSP),%R10

(233) 0x434804 MOV	0x28(%RSP),%R11

(233) 0x434809 VADDSD	%XMM15,%XMM13,%XMM0

(233) 0x43480e MOV	0x38(%RSP),%R13D

(233) 0x434813 ADD	%R10,%RDX

(233) 0x434816 VMULSD	%XMM3,%XMM0,%XMM5

(233) 0x43481a LEA	0x1(%R12),%EAX

(233) 0x43481f VMOVSD	%XMM5,(%R11,%RDX,8)

(233) 0x434825 CMP	%R13D,%EAX

(233) 0x434828 JAE	43489f

(233) 0x43482a LEA	0x1(%RCX),%EAX

(233) 0x43482d CLTQ

(233) 0x43482f LEA	(%R15,%RAX,1),%RDX

(233) 0x434833 LEA	(%RDI,%RDX,8),%R9

(233) 0x434837 LEA	(%RBX,%RAX,1),%RDX

(233) 0x43483b LEA	(%RDI,%RDX,8),%RDX

(233) 0x43483f VMOVSD	(%R8),%XMM2

(233) 0x434844 VMOVSD	(%RDX),%XMM7

(233) 0x434848 VADDSD	(%RSI),%XMM2,%XMM6

(233) 0x43484c VADDSD	(%R9),%XMM7,%XMM8

(233) 0x434851 ADD	%R10,%RAX

(233) 0x434854 ADD	$0x2,%R12D

(233) 0x434858 VADDSD	%XMM8,%XMM6,%XMM9

(233) 0x43485d VMULSD	%XMM3,%XMM9,%XMM10

(233) 0x434861 VMOVSD	%XMM10,(%R11,%RAX,8)

(233) 0x434867 CMP	%R13D,%R12D

(233) 0x43486a JAE	43489f

(233) 0x43486c ADD	$0x2,%ECX

(233) 0x43486f MOVSXD	%ECX,%R12

(233) 0x434872 ADD	%R12,%R10

(233) 0x434875 ADD	%R12,%R15

(233) 0x434878 ADD	%RBX,%R12

(233) 0x43487b VMOVSD	(%RDI,%R15,8),%XMM11

(233) 0x434881 VMOVSD	(%RDI,%R12,8),%XMM13

(233) 0x434887 VADDSD	(%R9),%XMM11,%XMM12

(233) 0x43488c VADDSD	(%RDX),%XMM13,%XMM14

(233) 0x434890 VADDSD	%XMM14,%XMM12,%XMM15

(233) 0x434895 VMULSD	%XMM3,%XMM15,%XMM0

(233) 0x434899 VMOVSD	%XMM0,(%R11,%R10,8)

(233) 0x43489f MOV	0x38(%RSP),%R12D

(233) 0x4348a4 INC	%R14

(233) 0x4348a7 CMP	%R14D,0x20(%RSP)

(233) 0x4348ac JLE	4348d0

(233) 0x4348ae MOV	0x18(%RSP),%EDI

(233) 0x4348b2 MOV	0x1c(%RSP),%EBX

(233) 0x4348b6 MOV	0x24(%RSP),%R15D

(233) 0x4348bb MOV	%EBX,0x3c(%RSP)

(233) 0x4348bf SUB	%R12D,%EDI

(233) 0x4348c2 JMP	434520

0x4348c7 NOPW	(%RAX,%RAX,1)

0x4348d0 VZEROUPPER

0x4348d3 LEA	-0x28(%RBP),%RSP

0x4348d7 POP	%RBX

0x4348d8 POP	%R12

0x4348da POP	%R13

0x4348dc POP	%R14

0x4348de POP	%R15

0x4348e0 POP	%RBP

0x4348e1 RET

0x4348e2 NOPW	(%RAX,%RAX,1)

(233) 0x4348e8 MOV	0x3c(%RSP),%ECX

(233) 0x4348ec XOR	%EAX,%EAX

(233) 0x4348ee JMP	434762

0x4348f3 INC	%EDI

0x4348f5 XOR	%EDX,%EDX

0x4348f7 JMP	4344c2

0x4348fc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.47	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.53	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.17 cycles (6.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.67 to 3.00 cycles (4.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	88
loop length	270
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67
cycles	6.30	11.73	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (3.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RBX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x14(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4348f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R12,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x24(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x1c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3b2ab(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4344c2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.17 cycles (6.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	88
loop length	270
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67
cycles	6.30	11.73	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (3.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 434440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RBX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x14(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4348f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R12,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 4348d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x493>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x24(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x1c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3b2ab(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4344c2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x82>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	0.99	0.28
▼Loop 233 - advec_mom.cpp:159-160 - exec–	0.00	0.01
○Loop 234 - advec_mom.cpp:160-160 - exec	0.99	0.28

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Code clean check

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Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code