OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 3.09% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x433b70 PUSH	%RBP

0x433b71 MOV	%RSP,%RBP

0x433b74 PUSH	%R15

0x433b76 PUSH	%R14

0x433b78 PUSH	%R13

0x433b7a PUSH	%R12

0x433b7c PUSH	%RBX

0x433b7d AND	$-0x40,%RSP

0x433b81 SUB	$0x100,%RSP

0x433b88 MOV	0x34(%RDI),%EAX

0x433b8b MOV	0x28(%RDI),%ECX

0x433b8e MOV	0x30(%RDI),%R12D

0x433b92 ADD	$0x4,%EAX

0x433b95 INC	%ECX

0x433b97 MOV	%EAX,0x70(%RSP)

0x433b9b MOV	%ECX,0x6c(%RSP)

0x433b9f MOV	0x2c(%RDI),%ESI

0x433ba2 CMP	%EAX,%R12D

0x433ba5 JGE	434413

0x433bab MOV	%EAX,%R14D

0x433bae LEA	0x3(%RSI),%R15D

0x433bb2 SUB	%R12D,%R14D

0x433bb5 CMP	%R15D,%ECX

0x433bb8 JGE	434413

0x433bbe MOV	%R15D,%EDX

0x433bc1 SUB	%ECX,%EDX

0x433bc3 MOV	%EDX,0x74(%RSP)

0x433bc7 MOV	%RDI,%RBX

0x433bca CALL	404630 <omp_get_num_threads@plt>

0x433bcf MOV	%EAX,%R13D

0x433bd2 CALL	404520 <omp_get_thread_num@plt>

0x433bd7 MOV	%EAX,%EDI

0x433bd9 MOV	0x74(%RSP),%EAX

0x433bdd XOR	%EDX,%EDX

0x433bdf IMUL	%R14D,%EAX

0x433be3 DIV	%R13D

0x433be6 MOV	%EAX,%ECX

0x433be8 CMP	%EDX,%EDI

0x433bea JB	434436

0x433bf0 IMUL	%ECX,%EDI

0x433bf3 LEA	(%RDI,%RDX,1),%EAX

0x433bf6 LEA	(%RCX,%RAX,1),%R8D

0x433bfa MOV	%EAX,0xfc(%RSP)

0x433c01 MOV	%R8D,0x68(%RSP)

0x433c06 CMP	%R8D,%EAX

0x433c09 JAE	434413

0x433c0f XOR	%EDX,%EDX

0x433c11 DIVL	0x74(%RSP)

0x433c15 MOV	0x6c(%RSP),%R9D

0x433c1a MOV	(%RBX),%R10

0x433c1d MOV	0x20(%RBX),%R11

0x433c21 MOV	0x10(%RBX),%RSI

0x433c25 MOV	0x18(%RBX),%R14

0x433c29 VMOVSD	0x3bb6f(%RIP),%XMM3

0x433c31 MOV	%R10,0x50(%RSP)

0x433c36 MOV	%R11,0x48(%RSP)

0x433c3b MOV	%R15D,%EDI

0x433c3e MOV	0x8(%RBX),%R15

0x433c42 MOV	%RSI,0x40(%RSP)

0x433c47 MOV	%R15,0x38(%RSP)

0x433c4c MOV	%R14,0x30(%RSP)

0x433c51 VBROADCASTSD	%XMM3,%YMM4

0x433c56 VBROADCASTSD	%XMM3,%ZMM2

0x433c5c ADD	%R12D,%EAX

0x433c5f ADD	%EDX,%R9D

0x433c62 MOVSXD	%EAX,%R12

0x433c65 MOV	%R9D,0x9c(%RSP)

0x433c6d MOV	%R12,0xe0(%RSP)

0x433c75 SUB	%R9D,%EDI

0x433c78 NOPL	(%RAX,%RAX,1)

(231) 0x433c80 CMP	%EDI,%ECX

(231) 0x433c82 CMOVBE	%ECX,%EDI

(231) 0x433c85 MOV	0xfc(%RSP),%ECX

(231) 0x433c8c MOV	%EDI,0xf8(%RSP)

(231) 0x433c93 LEA	(%RCX,%RDI,1),%EBX

(231) 0x433c96 MOV	%EBX,0x98(%RSP)

(231) 0x433c9d CMP	%EBX,%ECX

(231) 0x433c9f JAE	4343d4

(231) 0x433ca5 MOV	0x48(%RSP),%R8

(231) 0x433caa MOV	0x40(%RSP),%R10

(231) 0x433caf MOV	0xe0(%RSP),%RBX

(231) 0x433cb7 MOV	(%R8),%R9

(231) 0x433cba MOV	0x10(%R10),%RDX

(231) 0x433cbe MOV	0x10(%R8),%R15

(231) 0x433cc2 MOV	0x38(%RSP),%R8

(231) 0x433cc7 MOV	%EBX,%EAX

(231) 0x433cc9 MOV	%RDX,0xb0(%RSP)

(231) 0x433cd1 DEC	%EAX

(231) 0x433cd3 MOV	(%R8),%RDX

(231) 0x433cd6 CLTQ

(231) 0x433cd8 MOV	%EDI,%R12D

(231) 0x433cdb MOV	%RAX,%RSI

(231) 0x433cde MOV	0x50(%RSP),%RDI

(231) 0x433ce3 MOV	%RAX,%R14

(231) 0x433ce6 IMUL	%RDX,%RAX

(231) 0x433cea MOV	(%RDI),%RCX

(231) 0x433ced MOV	0x10(%RDI),%R13

(231) 0x433cf1 MOV	(%R10),%RDI

(231) 0x433cf4 MOV	%RAX,0xb8(%RSP)

(231) 0x433cfc MOV	0x30(%RSP),%RAX

(231) 0x433d01 IMUL	%RBX,%RDI

(231) 0x433d05 IMUL	%RCX,%RSI

(231) 0x433d09 IMUL	%R9,%R14

(231) 0x433d0d IMUL	%RBX,%RCX

(231) 0x433d11 IMUL	%RBX,%R9

(231) 0x433d15 IMUL	%RBX,%RDX

(231) 0x433d19 IMUL	(%RAX),%RBX

(231) 0x433d1d MOV	0x10(%R8),%R10

(231) 0x433d21 MOV	0x10(%RAX),%R11

(231) 0x433d25 MOV	%RDI,0xa0(%RSP)

(231) 0x433d2d LEA	-0x1(%R12),%EDI

(231) 0x433d32 MOV	%RSI,0x90(%RSP)

(231) 0x433d3a MOV	%R14,0xe8(%RSP)

(231) 0x433d42 MOV	%RCX,0xf0(%RSP)

(231) 0x433d4a MOV	%R9,0xa8(%RSP)

(231) 0x433d52 MOV	%R10,0xd8(%RSP)

(231) 0x433d5a MOV	%RDX,0xd0(%RSP)

(231) 0x433d62 MOV	%R11,0xc0(%RSP)

(231) 0x433d6a MOV	%RBX,0xc8(%RSP)

(231) 0x433d72 CMP	$0x6,%EDI

(231) 0x433d75 JBE	434428

(231) 0x433d7b MOVSXD	0x9c(%RSP),%RAX

(231) 0x433d83 MOV	0xa0(%RSP),%RDX

(231) 0x433d8b LEA	(%R9,%RAX,1),%R10

(231) 0x433d8f LEA	(%RSI,%RAX,1),%R8

(231) 0x433d93 SAL	$0x3,%R10

(231) 0x433d97 LEA	(%R14,%RAX,1),%RSI

(231) 0x433d9b SAL	$0x3,%RSI

(231) 0x433d9f ADD	%RAX,%RCX

(231) 0x433da2 LEA	(%R15,%R10,1),%R9

(231) 0x433da6 SAL	$0x3,%RCX

(231) 0x433daa LEA	(%R15,%RSI,1),%R14

(231) 0x433dae MOV	%R9,0x88(%RSP)

(231) 0x433db6 MOV	0xb0(%RSP),%RDI

(231) 0x433dbe LEA	-0x8(%R15,%RSI,1),%R9

(231) 0x433dc3 MOV	0xb8(%RSP),%RSI

(231) 0x433dcb MOV	%R14,0x80(%RSP)

(231) 0x433dd3 LEA	-0x8(%R13,%RCX,1),%R11

(231) 0x433dd8 LEA	(%R13,%RCX,1),%R14

(231) 0x433ddd LEA	(%RDX,%RAX,1),%RCX

(231) 0x433de1 LEA	(%RDI,%RCX,8),%RDI

(231) 0x433de5 LEA	(%RSI,%RAX,1),%RDX

(231) 0x433de9 MOV	0xd8(%RSP),%RCX

(231) 0x433df1 MOV	0xd0(%RSP),%RSI

(231) 0x433df9 LEA	(%RCX,%RDX,8),%RCX

(231) 0x433dfd LEA	(%RSI,%RAX,1),%RDX

(231) 0x433e01 MOV	0xd8(%RSP),%RSI

(231) 0x433e09 SAL	$0x3,%R8

(231) 0x433e0d LEA	(%RSI,%RDX,8),%RSI

(231) 0x433e11 MOV	0xc8(%RSP),%RDX

(231) 0x433e19 LEA	(%R13,%R8,1),%RBX

(231) 0x433e1e ADD	%RDX,%RAX

(231) 0x433e21 MOV	0xc0(%RSP),%RDX

(231) 0x433e29 LEA	-0x8(%R13,%R8,1),%R8

(231) 0x433e2e LEA	(%RDX,%RAX,8),%RDX

(231) 0x433e32 MOV	%R12D,%EAX

(231) 0x433e35 SHR	$0x3,%EAX

(231) 0x433e38 MOV	%RAX,%R12

(231) 0x433e3b SAL	$0x6,%RAX

(231) 0x433e3f MOV	%RAX,0x78(%RSP)

(231) 0x433e44 XOR	%EAX,%EAX

(231) 0x433e46 AND	$0x1,%R12D

(231) 0x433e4a LEA	-0x8(%R15,%R10,1),%R10

(231) 0x433e4f JE	433ecf

(231) 0x433e51 VMOVUPD	(%R14),%ZMM0

(231) 0x433e57 VMOVUPD	(%R11),%ZMM1

(231) 0x433e5d MOV	0x88(%RSP),%RAX

(231) 0x433e65 VMULPD	(%R10),%ZMM1,%ZMM6

(231) 0x433e6b VMULPD	(%RAX),%ZMM0,%ZMM5

(231) 0x433e71 MOV	0x80(%RSP),%R12

(231) 0x433e79 VMOVUPD	(%R9),%ZMM8

(231) 0x433e7f VMOVUPD	(%R12),%ZMM7

(231) 0x433e86 VFMADD231PD	(%R8),%ZMM8,%ZMM6

(231) 0x433e8c VFMADD231PD	(%RBX),%ZMM7,%ZMM5

(231) 0x433e92 MOV	0x78(%RSP),%R12

(231) 0x433e97 MOV	$0x40,%EAX

(231) 0x433e9c VADDPD	%ZMM6,%ZMM5,%ZMM9

(231) 0x433ea2 VMULPD	%ZMM2,%ZMM9,%ZMM10

(231) 0x433ea8 VMOVUPD	%ZMM10,(%RDI)

(231) 0x433eae VMOVUPD	(%RSI),%ZMM11

(231) 0x433eb4 VSUBPD	(%RCX),%ZMM11,%ZMM12

(231) 0x433eba VADDPD	%ZMM10,%ZMM12,%ZMM13

(231) 0x433ec0 VMOVUPD	%ZMM13,(%RDX)

(231) 0x433ec6 CMP	%R12,%RAX

(231) 0x433ec9 JE	433fde

(231) 0x433ecf MOV	%R15,0x60(%RSP)

(231) 0x433ed4 MOV	%R13,0x58(%RSP)

(231) 0x433ed9 MOV	0x80(%RSP),%R12

(231) 0x433ee1 MOV	0x88(%RSP),%R13

(231) 0x433ee9 MOV	0x78(%RSP),%R15

  (232) 0x433eee VMOVUPD	(%R14,%RAX,1),%ZMM14

  (232) 0x433ef5 VMOVUPD	(%R11,%RAX,1),%ZMM5

  (232) 0x433efc VMULPD	(%R13,%RAX,1),%ZMM14,%ZMM15

  (232) 0x433f04 VMULPD	(%R10,%RAX,1),%ZMM5,%ZMM7

  (232) 0x433f0b VMOVUPD	(%R12,%RAX,1),%ZMM0

  (232) 0x433f12 VMOVUPD	(%R9,%RAX,1),%ZMM1

  (232) 0x433f19 VFMADD231PD	(%RBX,%RAX,1),%ZMM0,%ZMM15

  (232) 0x433f20 VFMADD231PD	(%R8,%RAX,1),%ZMM1,%ZMM7

  (232) 0x433f27 VADDPD	%ZMM7,%ZMM15,%ZMM6

  (232) 0x433f2d VMULPD	%ZMM2,%ZMM6,%ZMM8

  (232) 0x433f33 VMOVUPD	%ZMM8,(%RDI,%RAX,1)

  (232) 0x433f3a VMOVUPD	(%RSI,%RAX,1),%ZMM9

  (232) 0x433f41 VSUBPD	(%RCX,%RAX,1),%ZMM9,%ZMM10

  (232) 0x433f48 VADDPD	%ZMM8,%ZMM10,%ZMM11

  (232) 0x433f4e VMOVUPD	%ZMM11,(%RDX,%RAX,1)

  (232) 0x433f55 VMOVUPD	0x40(%R14,%RAX,1),%ZMM12

  (232) 0x433f5d VMOVUPD	0x40(%R11,%RAX,1),%ZMM15

  (232) 0x433f65 VMULPD	0x40(%R13,%RAX,1),%ZMM12,%ZMM13

  (232) 0x433f6d VMULPD	0x40(%R10,%RAX,1),%ZMM15,%ZMM0

  (232) 0x433f75 VMOVUPD	0x40(%R12,%RAX,1),%ZMM14

  (232) 0x433f7d VMOVUPD	0x40(%R9,%RAX,1),%ZMM5

  (232) 0x433f85 VFMADD231PD	0x40(%RBX,%RAX,1),%ZMM14,%ZMM13

  (232) 0x433f8d VFMADD231PD	0x40(%R8,%RAX,1),%ZMM5,%ZMM0

  (232) 0x433f95 VADDPD	%ZMM0,%ZMM13,%ZMM7

  (232) 0x433f9b VMULPD	%ZMM2,%ZMM7,%ZMM6

  (232) 0x433fa1 VMOVUPD	%ZMM6,0x40(%RDI,%RAX,1)

  (232) 0x433fa9 VMOVUPD	0x40(%RSI,%RAX,1),%ZMM1

  (232) 0x433fb1 VSUBPD	0x40(%RCX,%RAX,1),%ZMM1,%ZMM8

  (232) 0x433fb9 VADDPD	%ZMM6,%ZMM8,%ZMM9

  (232) 0x433fbf VMOVUPD	%ZMM9,0x40(%RDX,%RAX,1)

  (232) 0x433fc7 SUB	$-0x80,%RAX

  (232) 0x433fcb CMP	%R15,%RAX

  (232) 0x433fce JNE	433eee

(231) 0x433fd4 MOV	0x60(%RSP),%R15

(231) 0x433fd9 MOV	0x58(%RSP),%R13

(231) 0x433fde MOV	0xf8(%RSP),%EBX

(231) 0x433fe5 MOV	0x9c(%RSP),%ECX

(231) 0x433fec MOV	%EBX,%EAX

(231) 0x433fee AND	$-0x8,%EAX

(231) 0x433ff1 ADD	%EAX,0xfc(%RSP)

(231) 0x433ff8 ADD	%EAX,%ECX

(231) 0x433ffa AND	$0x7,%EBX

(231) 0x433ffd JE	4343c4

(231) 0x434003 MOV	0xf8(%RSP),%R10D

(231) 0x43400b SUB	%EAX,%R10D

(231) 0x43400e LEA	-0x1(%R10),%R14D

(231) 0x434012 CMP	$0x2,%R14D

(231) 0x434016 JBE	434123

(231) 0x43401c MOVSXD	0x9c(%RSP),%RDX

(231) 0x434024 MOV	0x90(%RSP),%R8

(231) 0x43402c MOV	0xf0(%RSP),%R9

(231) 0x434034 MOV	0xa8(%RSP),%R11

(231) 0x43403c LEA	(%R8,%RDX,1),%RDI

(231) 0x434040 LEA	(%R9,%RDX,1),%R8

(231) 0x434044 LEA	(%R11,%RDX,1),%R9

(231) 0x434048 ADD	%RAX,%R9

(231) 0x43404b VMOVUPD	(%R15,%R9,8),%YMM10

(231) 0x434051 VMOVUPD	-0x8(%R15,%R9,8),%YMM13

(231) 0x434058 ADD	%RAX,%R8

(231) 0x43405b VMULPD	(%R13,%R8,8),%YMM10,%YMM11

(231) 0x434062 VMULPD	-0x8(%R13,%R8,8),%YMM13,%YMM14

(231) 0x434069 MOV	0xe8(%RSP),%RSI

(231) 0x434071 ADD	%RAX,%RDI

(231) 0x434074 VMOVUPD	(%R13,%RDI,8),%YMM12

(231) 0x43407b VMOVUPD	-0x8(%R13,%RDI,8),%YMM15

(231) 0x434082 ADD	%RDX,%RSI

(231) 0x434085 ADD	%RAX,%RSI

(231) 0x434088 VFMADD231PD	(%R15,%RSI,8),%YMM12,%YMM11

(231) 0x43408e VFMADD231PD	-0x8(%R15,%RSI,8),%YMM15,%YMM14

(231) 0x434095 MOV	0xb8(%RSP),%RBX

(231) 0x43409d MOV	0xa0(%RSP),%R12

(231) 0x4340a5 LEA	(%RBX,%RDX,1),%R11

(231) 0x4340a9 MOV	0xc8(%RSP),%R14

(231) 0x4340b1 VADDPD	%YMM14,%YMM11,%YMM0

(231) 0x4340b6 MOV	0xd0(%RSP),%RBX

(231) 0x4340be LEA	(%R12,%RDX,1),%R12

(231) 0x4340c2 VMULPD	%YMM4,%YMM0,%YMM5

(231) 0x4340c6 ADD	%RDX,%RBX

(231) 0x4340c9 ADD	%R14,%RDX

(231) 0x4340cc ADD	%RAX,%RDX

(231) 0x4340cf ADD	%RAX,%R12

(231) 0x4340d2 ADD	%RAX,%R11

(231) 0x4340d5 ADD	%RAX,%RBX

(231) 0x4340d8 MOV	0xb0(%RSP),%RAX

(231) 0x4340e0 MOV	0xd8(%RSP),%RDI

(231) 0x4340e8 VMOVUPD	%YMM5,(%RAX,%R12,8)

(231) 0x4340ee VMOVUPD	(%RDI,%RBX,8),%YMM7

(231) 0x4340f3 MOV	0xc0(%RSP),%RSI

(231) 0x4340fb VSUBPD	(%RDI,%R11,8),%YMM7,%YMM6

(231) 0x434101 VADDPD	%YMM5,%YMM6,%YMM1

(231) 0x434105 VMOVUPD	%YMM1,(%RSI,%RDX,8)

(231) 0x43410a MOV	%R10D,%EDX

(231) 0x43410d AND	$-0x4,%EDX

(231) 0x434110 ADD	%EDX,0xfc(%RSP)

(231) 0x434117 ADD	%EDX,%ECX

(231) 0x434119 AND	$0x3,%R10D

(231) 0x43411d JE	4343c4

(231) 0x434123 MOV	0xf0(%RSP),%R14

(231) 0x43412b MOV	0xe8(%RSP),%R11

(231) 0x434133 MOV	0xa8(%RSP),%RBX

(231) 0x43413b MOVSXD	%ECX,%RAX

(231) 0x43413e LEA	(%R11,%RAX,1),%R8

(231) 0x434142 LEA	(%R14,%RAX,1),%R9

(231) 0x434146 ADD	%RAX,%RBX

(231) 0x434149 LEA	(%R15,%R8,8),%RDI

(231) 0x43414d LEA	-0x1(%RCX),%EDX

(231) 0x434150 LEA	(%R13,%R9,8),%R8

(231) 0x434155 LEA	(%R15,%RBX,8),%R9

(231) 0x434159 MOV	0xa8(%RSP),%RBX

(231) 0x434161 MOVSXD	%EDX,%RDX

(231) 0x434164 MOV	0x90(%RSP),%R12

(231) 0x43416c ADD	%RDX,%RBX

(231) 0x43416f VMOVSD	(%R15,%RBX,8),%XMM11

(231) 0x434175 VMOVSD	(%R9),%XMM8

(231) 0x43417a LEA	(%R12,%RAX,1),%R10

(231) 0x43417e LEA	(%RDX,%R11,1),%R11

(231) 0x434182 LEA	(%R13,%R10,8),%RSI

(231) 0x434187 LEA	(%RDX,%R12,1),%R10

(231) 0x43418b ADD	%R14,%RDX

(231) 0x43418e VMULSD	(%R13,%RDX,8),%XMM11,%XMM12

(231) 0x434195 VMULSD	(%R8),%XMM8,%XMM9

(231) 0x43419a VMOVSD	(%R15,%R11,8),%XMM13

(231) 0x4341a0 VMOVSD	(%RDI),%XMM10

(231) 0x4341a4 MOV	0xa0(%RSP),%R14

(231) 0x4341ac VFMADD231SD	(%R13,%R10,8),%XMM13,%XMM12

(231) 0x4341b3 VFMADD231SD	(%RSI),%XMM10,%XMM9

(231) 0x4341b8 MOV	0xb0(%RSP),%R11

(231) 0x4341c0 LEA	(%R14,%RAX,1),%RDX

(231) 0x4341c4 MOV	0xc8(%RSP),%R10

(231) 0x4341cc MOV	0xb8(%RSP),%R14

(231) 0x4341d4 VADDSD	%XMM12,%XMM9,%XMM14

(231) 0x4341d9 LEA	(%R10,%RAX,1),%RBX

(231) 0x4341dd MOV	0x98(%RSP),%R10D

(231) 0x4341e5 VMULSD	%XMM3,%XMM14,%XMM15

(231) 0x4341e9 VMOVSD	%XMM15,(%R11,%RDX,8)

(231) 0x4341ef MOV	0xd0(%RSP),%RDX

(231) 0x4341f7 MOV	0xfc(%RSP),%R11D

(231) 0x4341ff ADD	%RAX,%RDX

(231) 0x434202 ADD	%R14,%RAX

(231) 0x434205 MOV	0xd8(%RSP),%R14

(231) 0x43420d INC	%R11D

(231) 0x434210 VMOVSD	(%R14,%RDX,8),%XMM0

(231) 0x434216 VSUBSD	(%R14,%RAX,8),%XMM0,%XMM5

(231) 0x43421c MOV	0xc0(%RSP),%RAX

(231) 0x434224 VADDSD	%XMM15,%XMM5,%XMM7

(231) 0x434229 VMOVSD	%XMM7,(%RAX,%RBX,8)

(231) 0x43422e CMP	%R10D,%R11D

(231) 0x434231 JAE	4343c4

(231) 0x434237 MOV	0xe8(%RSP),%RDX

(231) 0x43423f LEA	0x1(%RCX),%EAX

(231) 0x434242 CLTQ

(231) 0x434244 LEA	(%RDX,%RAX,1),%R11

(231) 0x434248 LEA	(%R15,%R11,8),%RDX

(231) 0x43424c MOV	0xa8(%RSP),%R11

(231) 0x434254 LEA	(%R12,%RAX,1),%RBX

(231) 0x434258 LEA	(%R13,%RBX,8),%R10

(231) 0x43425d ADD	%RAX,%R11

(231) 0x434260 MOV	0xf0(%RSP),%RBX

(231) 0x434268 LEA	(%R15,%R11,8),%R11

(231) 0x43426c VMOVSD	(%R9),%XMM9

(231) 0x434271 VMOVSD	(%R11),%XMM6

(231) 0x434276 ADD	%RAX,%RBX

(231) 0x434279 LEA	(%R13,%RBX,8),%RBX

(231) 0x43427e VMULSD	(%R8),%XMM9,%XMM10

(231) 0x434283 VMULSD	(%RBX),%XMM6,%XMM8

(231) 0x434287 VMOVSD	(%RDI),%XMM11

(231) 0x43428b VMOVSD	(%RDX),%XMM1

(231) 0x43428f MOV	0xa0(%RSP),%R9

(231) 0x434297 VFMADD231SD	(%RSI),%XMM11,%XMM10

(231) 0x43429c VFMADD132SD	(%R10),%XMM8,%XMM1

(231) 0x4342a1 MOV	0xb0(%RSP),%RDI

(231) 0x4342a9 MOV	0xd0(%RSP),%R8

(231) 0x4342b1 LEA	(%R9,%RAX,1),%RSI

(231) 0x4342b5 VADDSD	%XMM1,%XMM10,%XMM12

(231) 0x4342b9 VMULSD	%XMM3,%XMM12,%XMM13

(231) 0x4342bd VMOVSD	%XMM13,(%RDI,%RSI,8)

(231) 0x4342c2 LEA	(%R8,%RAX,1),%RDI

(231) 0x4342c6 MOV	0xc8(%RSP),%RSI

(231) 0x4342ce MOV	0xb8(%RSP),%R8

(231) 0x4342d6 VMOVSD	(%R14,%RDI,8),%XMM14

(231) 0x4342dc ADD	%RAX,%RSI

(231) 0x4342df ADD	%R8,%RAX

(231) 0x4342e2 VSUBSD	(%R14,%RAX,8),%XMM14,%XMM15

(231) 0x4342e8 MOV	0xc0(%RSP),%RAX

(231) 0x4342f0 MOV	0xfc(%RSP),%EDI

(231) 0x4342f7 VADDSD	%XMM13,%XMM15,%XMM0

(231) 0x4342fc ADD	$0x2,%EDI

(231) 0x4342ff VMOVSD	%XMM0,(%RAX,%RSI,8)

(231) 0x434304 MOV	0x98(%RSP),%ESI

(231) 0x43430b CMP	%ESI,%EDI

(231) 0x43430d JAE	4343c4

(231) 0x434313 MOV	0xa8(%RSP),%RDI

(231) 0x43431b ADD	$0x2,%ECX

(231) 0x43431e MOVSXD	%ECX,%RCX

(231) 0x434321 MOV	0xf0(%RSP),%R8

(231) 0x434329 ADD	%RCX,%RDI

(231) 0x43432c VMOVSD	(%R15,%RDI,8),%XMM5

(231) 0x434332 VMOVSD	(%RBX),%XMM8

(231) 0x434336 ADD	%RCX,%R8

(231) 0x434339 VMULSD	(%R13,%R8,8),%XMM5,%XMM7

(231) 0x434340 VMULSD	(%R11),%XMM8,%XMM1

(231) 0x434345 MOV	0xe8(%RSP),%RAX

(231) 0x43434d VMOVSD	(%R10),%XMM9

(231) 0x434352 ADD	%RCX,%RAX

(231) 0x434355 VMOVSD	(%R15,%RAX,8),%XMM6

(231) 0x43435b ADD	%RCX,%R12

(231) 0x43435e VFMADD231SD	(%R13,%R12,8),%XMM6,%XMM7

(231) 0x434365 VFMADD231SD	(%RDX),%XMM9,%XMM1

(231) 0x43436a MOV	0xb0(%RSP),%R13

(231) 0x434372 MOV	0xd0(%RSP),%R10

(231) 0x43437a ADD	%RCX,%R9

(231) 0x43437d MOV	0xb8(%RSP),%RDX

(231) 0x434385 VADDSD	%XMM1,%XMM7,%XMM10

(231) 0x434389 ADD	%RCX,%R10

(231) 0x43438c ADD	%RCX,%RDX

(231) 0x43438f VMULSD	%XMM3,%XMM10,%XMM11

(231) 0x434393 MOV	0xc8(%RSP),%R15

(231) 0x43439b ADD	%RCX,%R15

(231) 0x43439e VMOVSD	%XMM11,(%R13,%R9,8)

(231) 0x4343a5 VMOVSD	(%R14,%R10,8),%XMM12

(231) 0x4343ab VSUBSD	(%R14,%RDX,8),%XMM12,%XMM13

(231) 0x4343b1 MOV	0xc0(%RSP),%R14

(231) 0x4343b9 VADDSD	%XMM11,%XMM13,%XMM14

(231) 0x4343be VMOVSD	%XMM14,(%R14,%R15,8)

(231) 0x4343c4 MOV	0x98(%RSP),%R11D

(231) 0x4343cc MOV	%R11D,0xfc(%RSP)

(231) 0x4343d4 INCQ	0xe0(%RSP)

(231) 0x4343dc MOV	0xe0(%RSP),%RSI

(231) 0x4343e4 CMP	%ESI,0x70(%RSP)

(231) 0x4343e8 JLE	434410

(231) 0x4343ea MOV	0x68(%RSP),%ECX

(231) 0x4343ee MOV	0xfc(%RSP),%EAX

(231) 0x4343f5 MOV	0x6c(%RSP),%R12D

(231) 0x4343fa MOV	0x74(%RSP),%EDI

(231) 0x4343fe MOV	%R12D,0x9c(%RSP)

(231) 0x434406 SUB	%EAX,%ECX

(231) 0x434408 JMP	433c80

0x43440d NOPL	(%RAX)

0x434410 VZEROUPPER

0x434413 LEA	-0x28(%RBP),%RSP

0x434417 POP	%RBX

0x434418 POP	%R12

0x43441a POP	%R13

0x43441c POP	%R14

0x43441e POP	%R15

0x434420 POP	%RBP

0x434421 RET

0x434422 NOPW	(%RAX,%RAX,1)

(231) 0x434428 MOV	0x9c(%RSP),%ECX

(231) 0x43442f XOR	%EAX,%EAX

(231) 0x434431 JMP	434003

0x434436 INC	%ECX

0x434438 XOR	%EDX,%EDX

0x43443a JMP	433bf0

0x43443f NOP

Coverage (%)	Name	Source Location	Module
○97.65	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.35	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 2.33 cycles (6.79x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.83 to 3.00 cycles (5.28x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.83 to 14.67 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	85
nb uops	95
loop length	309
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67
cycles	6.30	11.73	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 433b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EAX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 434436 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xfc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x74(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x6c(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3bb6f(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R9D,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 433bf0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 2.33 cycles (6.79x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.83 to 14.67 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	85
nb uops	95
loop length	309
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67
cycles	6.30	11.73	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 433b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x4,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x6c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EAX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 434436 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDI,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%RAX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xfc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 434413 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x8a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x74(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x6c(%RSP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3bb6f(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R9D,0x9c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 433bf0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.09	0.89
▼Loop 231 - advec_mom.cpp:169-172 - exec–	0.00	0.01
○Loop 232 - advec_mom.cpp:170-172 - exec	3.08	0.89

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code