OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x433670 PUSH	%RBP

0x433671 MOV	%RSP,%RBP

0x433674 PUSH	%R15

0x433676 PUSH	%R14

0x433678 MOV	%RDI,%R14

0x43367b PUSH	%R13

0x43367d PUSH	%R12

0x43367f PUSH	%RBX

0x433680 AND	$-0x40,%RSP

0x433684 ADD	$-0x80,%RSP

0x433688 MOV	0x28(%RDI),%EAX

0x43368b MOV	0x2c(%RDI),%EDX

0x43368e MOV	0x20(%RDI),%EDI

0x433691 ADD	$0x3,%EDX

0x433694 INC	%EDI

0x433696 LEA	0x1(%RAX),%R12D

0x43369a MOV	%EDX,0x44(%RSP)

0x43369e MOV	%EDI,0x40(%RSP)

0x4336a2 MOV	0x24(%R14),%ECX

0x4336a6 CMP	%EDX,%R12D

0x4336a9 JGE	433b43

0x4336af MOV	%EDX,%EBX

0x4336b1 LEA	0x3(%RCX),%R15D

0x4336b5 SUB	%R12D,%EBX

0x4336b8 CMP	%R15D,%EDI

0x4336bb JGE	433b43

0x4336c1 MOV	%R15D,%ESI

0x4336c4 SUB	%EDI,%ESI

0x4336c6 MOV	%ESI,0x78(%RSP)

0x4336ca CALL	404630 <omp_get_num_threads@plt>

0x4336cf MOV	%EAX,%R13D

0x4336d2 CALL	404520 <omp_get_thread_num@plt>

0x4336d7 MOV	%EAX,%R8D

0x4336da MOV	0x78(%RSP),%EAX

0x4336de XOR	%EDX,%EDX

0x4336e0 IMUL	%EBX,%EAX

0x4336e3 DIV	%R13D

0x4336e6 MOV	%EAX,%ESI

0x4336e8 CMP	%EDX,%R8D

0x4336eb JB	433b62

0x4336f1 IMUL	%ESI,%R8D

0x4336f5 LEA	(%R8,%RDX,1),%R13D

0x4336f9 LEA	(%RSI,%R13,1),%R9D

0x4336fd MOV	%R9D,0x3c(%RSP)

0x433702 CMP	%R9D,%R13D

0x433705 JAE	433b43

0x43370b MOV	%R13D,%EAX

0x43370e XOR	%EDX,%EDX

0x433710 DIVL	0x78(%RSP)

0x433714 MOV	(%R14),%R10

0x433717 MOV	0x10(%R14),%R11

0x43371b MOV	0x40(%RSP),%EDI

0x43371f MOV	%R10,0x30(%RSP)

0x433724 MOV	%R11,0x28(%RSP)

0x433729 MOV	%R15D,%ECX

0x43372c MOV	0x18(%R14),%R15

0x433730 MOV	0x8(%R14),%R14

0x433734 MOV	%R15,0x20(%RSP)

0x433739 MOV	%R14,0x18(%RSP)

0x43373e ADD	%EDX,%EDI

0x433740 ADD	%R12D,%EAX

0x433743 SUB	%EDI,%ECX

0x433745 MOVSXD	%EAX,%R12

0x433748 NOPL	(%RAX,%RAX,1)

(229) 0x433750 CMP	%ECX,%ESI

(229) 0x433752 CMOVBE	%ESI,%ECX

(229) 0x433755 LEA	(%R13,%RCX,1),%EBX

(229) 0x43375a MOV	%EBX,0x7c(%RSP)

(229) 0x43375e CMP	%EBX,%R13D

(229) 0x433761 JAE	433b22

(229) 0x433767 MOV	0x30(%RSP),%RSI

(229) 0x43376c MOV	0x28(%RSP),%R8

(229) 0x433771 MOV	0x18(%RSP),%R11

(229) 0x433776 MOV	(%RSI),%RDX

(229) 0x433779 MOV	0x10(%R8),%R9

(229) 0x43377d MOV	(%R8),%RBX

(229) 0x433780 MOV	0x10(%R11),%R8

(229) 0x433784 MOV	(%R11),%R11

(229) 0x433787 MOV	0x20(%RSP),%RAX

(229) 0x43378c IMUL	%R12,%RDX

(229) 0x433790 IMUL	%R12,%RBX

(229) 0x433794 IMUL	%R12,%R11

(229) 0x433798 MOV	0x10(%RSI),%R10

(229) 0x43379c MOV	(%RAX),%R15

(229) 0x43379f LEA	-0x1(%RCX),%ESI

(229) 0x4337a2 MOV	%R10,0x50(%RSP)

(229) 0x4337a7 MOV	%RDX,0x48(%RSP)

(229) 0x4337ac MOV	%R9,0x68(%RSP)

(229) 0x4337b1 MOV	%RBX,0x58(%RSP)

(229) 0x4337b6 IMUL	%R12,%R15

(229) 0x4337ba MOV	%R8,0x70(%RSP)

(229) 0x4337bf MOV	%R11,0x60(%RSP)

(229) 0x4337c4 MOV	0x10(%RAX),%R14

(229) 0x4337c8 CMP	$0x6,%ESI

(229) 0x4337cb JBE	433b58

(229) 0x4337d1 MOVSXD	%EDI,%RAX

(229) 0x4337d4 LEA	(%RDX,%RAX,1),%RSI

(229) 0x4337d8 ADD	%RAX,%RBX

(229) 0x4337db LEA	(%R10,%RSI,8),%RDX

(229) 0x4337df LEA	(%R9,%RBX,8),%R10

(229) 0x4337e3 MOV	%ECX,%EBX

(229) 0x4337e5 SHR	$0x3,%EBX

(229) 0x4337e8 SAL	$0x6,%RBX

(229) 0x4337ec LEA	(%R15,%RAX,1),%RSI

(229) 0x4337f0 ADD	%R11,%RAX

(229) 0x4337f3 LEA	-0x40(%RBX),%R11

(229) 0x4337f7 SHR	$0x6,%R11

(229) 0x4337fb SAL	$0x3,%RSI

(229) 0x4337ff INC	%R11

(229) 0x433802 LEA	-0x8(%R14,%RSI,1),%R9

(229) 0x433807 LEA	(%R8,%RAX,8),%R8

(229) 0x43380b ADD	%R14,%RSI

(229) 0x43380e XOR	%EAX,%EAX

(229) 0x433810 AND	$0x3,%R11D

(229) 0x433814 JE	4338b4

(229) 0x43381a CMP	$0x1,%R11

(229) 0x43381e JE	43387d

(229) 0x433820 CMP	$0x2,%R11

(229) 0x433824 JE	43384f

(229) 0x433826 VMOVUPD	(%R10),%ZMM0

(229) 0x43382c VMOVUPD	(%RSI),%ZMM5

(229) 0x433832 MOV	$0x40,%EAX

(229) 0x433837 VFMSUB132PD	(%RDX),%ZMM5,%ZMM0

(229) 0x43383d VADDPD	(%R9),%ZMM0,%ZMM1

(229) 0x433843 VDIVPD	(%R8),%ZMM1,%ZMM2

(229) 0x433849 VMOVUPD	%ZMM2,(%RDX)

(229) 0x43384f VMOVUPD	(%R10,%RAX,1),%ZMM3

(229) 0x433856 VMOVUPD	(%RSI,%RAX,1),%ZMM6

(229) 0x43385d VFMSUB132PD	(%RDX,%RAX,1),%ZMM6,%ZMM3

(229) 0x433864 VADDPD	(%R9,%RAX,1),%ZMM3,%ZMM4

(229) 0x43386b VDIVPD	(%R8,%RAX,1),%ZMM4,%ZMM7

(229) 0x433872 VMOVUPD	%ZMM7,(%RDX,%RAX,1)

(229) 0x433879 ADD	$0x40,%RAX

(229) 0x43387d VMOVUPD	(%R10,%RAX,1),%ZMM8

(229) 0x433884 VMOVUPD	(%RSI,%RAX,1),%ZMM9

(229) 0x43388b VFMSUB132PD	(%RDX,%RAX,1),%ZMM9,%ZMM8

(229) 0x433892 VADDPD	(%R9,%RAX,1),%ZMM8,%ZMM10

(229) 0x433899 VDIVPD	(%R8,%RAX,1),%ZMM10,%ZMM11

(229) 0x4338a0 VMOVUPD	%ZMM11,(%RDX,%RAX,1)

(229) 0x4338a7 ADD	$0x40,%RAX

(229) 0x4338ab CMP	%RBX,%RAX

(229) 0x4338ae JE	43397d

  (230) 0x4338b4 VMOVUPD	(%R10,%RAX,1),%ZMM12

  (230) 0x4338bb VMOVUPD	(%RSI,%RAX,1),%ZMM13

  (230) 0x4338c2 VFMSUB132PD	(%RDX,%RAX,1),%ZMM13,%ZMM12

  (230) 0x4338c9 VADDPD	(%R9,%RAX,1),%ZMM12,%ZMM14

  (230) 0x4338d0 VDIVPD	(%R8,%RAX,1),%ZMM14,%ZMM15

  (230) 0x4338d7 VMOVUPD	%ZMM15,(%RDX,%RAX,1)

  (230) 0x4338de VMOVUPD	0x40(%R10,%RAX,1),%ZMM0

  (230) 0x4338e6 VMOVUPD	0x40(%RSI,%RAX,1),%ZMM5

  (230) 0x4338ee VFMSUB132PD	0x40(%RDX,%RAX,1),%ZMM5,%ZMM0

  (230) 0x4338f6 VADDPD	0x40(%R9,%RAX,1),%ZMM0,%ZMM1

  (230) 0x4338fe VDIVPD	0x40(%R8,%RAX,1),%ZMM1,%ZMM2

  (230) 0x433906 VMOVUPD	%ZMM2,0x40(%RDX,%RAX,1)

  (230) 0x43390e VMOVUPD	0x80(%R10,%RAX,1),%ZMM6

  (230) 0x433916 VMOVUPD	0x80(%RSI,%RAX,1),%ZMM3

  (230) 0x43391e VFMSUB132PD	0x80(%RDX,%RAX,1),%ZMM3,%ZMM6

  (230) 0x433926 VADDPD	0x80(%R9,%RAX,1),%ZMM6,%ZMM4

  (230) 0x43392e VDIVPD	0x80(%R8,%RAX,1),%ZMM4,%ZMM7

  (230) 0x433936 VMOVUPD	%ZMM7,0x80(%RDX,%RAX,1)

  (230) 0x43393e VMOVUPD	0xc0(%R10,%RAX,1),%ZMM8

  (230) 0x433946 VMOVUPD	0xc0(%RSI,%RAX,1),%ZMM9

  (230) 0x43394e VFMSUB132PD	0xc0(%RDX,%RAX,1),%ZMM9,%ZMM8

  (230) 0x433956 VADDPD	0xc0(%R9,%RAX,1),%ZMM8,%ZMM10

  (230) 0x43395e VDIVPD	0xc0(%R8,%RAX,1),%ZMM10,%ZMM11

  (230) 0x433966 VMOVUPD	%ZMM11,0xc0(%RDX,%RAX,1)

  (230) 0x43396e ADD	$0x100,%RAX

  (230) 0x433974 CMP	%RBX,%RAX

  (230) 0x433977 JNE	4338b4

(229) 0x43397d MOV	%ECX,%R10D

(229) 0x433980 AND	$-0x8,%R10D

(229) 0x433984 LEA	(%R10,%RDI,1),%EDX

(229) 0x433988 ADD	%R10D,%R13D

(229) 0x43398b TEST	$0x7,%CL

(229) 0x43398e JE	433b1d

(229) 0x433994 SUB	%R10D,%ECX

(229) 0x433997 LEA	-0x1(%RCX),%ESI

(229) 0x43399a CMP	$0x2,%ESI

(229) 0x43399d JBE	433a15

(229) 0x43399f MOV	0x48(%RSP),%R9

(229) 0x4339a4 MOVSXD	%EDI,%RDI

(229) 0x4339a7 LEA	(%R9,%RDI,1),%R8

(229) 0x4339ab MOV	0x50(%RSP),%RBX

(229) 0x4339b0 ADD	%R10,%R8

(229) 0x4339b3 LEA	(%RBX,%R8,8),%R11

(229) 0x4339b7 MOV	0x60(%RSP),%RAX

(229) 0x4339bc MOV	0x58(%RSP),%R8

(229) 0x4339c1 LEA	(%R15,%RDI,1),%RSI

(229) 0x4339c5 ADD	%R10,%RSI

(229) 0x4339c8 LEA	(%RAX,%RDI,1),%R9

(229) 0x4339cc ADD	%R8,%RDI

(229) 0x4339cf ADD	%R10,%RDI

(229) 0x4339d2 ADD	%R10,%R9

(229) 0x4339d5 VMOVUPD	(%R11),%YMM12

(229) 0x4339da VMOVUPD	-0x8(%R14,%RSI,8),%YMM13

(229) 0x4339e1 MOV	0x68(%RSP),%R10

(229) 0x4339e6 MOV	%ECX,%EBX

(229) 0x4339e8 VFMADD132PD	(%R10,%RDI,8),%YMM13,%YMM12

(229) 0x4339ee AND	$-0x4,%EBX

(229) 0x4339f1 MOV	0x70(%RSP),%RDI

(229) 0x4339f6 ADD	%EBX,%EDX

(229) 0x4339f8 ADD	%EBX,%R13D

(229) 0x4339fb VSUBPD	(%R14,%RSI,8),%YMM12,%YMM14

(229) 0x433a01 AND	$0x3,%ECX

(229) 0x433a04 VDIVPD	(%RDI,%R9,8),%YMM14,%YMM15

(229) 0x433a0a VMOVUPD	%YMM15,(%R11)

(229) 0x433a0f JE	433b1d

(229) 0x433a15 MOV	0x48(%RSP),%RBX

(229) 0x433a1a MOVSXD	%EDX,%RAX

(229) 0x433a1d MOV	0x50(%RSP),%R9

(229) 0x433a22 LEA	(%RBX,%RAX,1),%RCX

(229) 0x433a26 LEA	-0x1(%RDX),%R8D

(229) 0x433a2a MOV	0x58(%RSP),%R11

(229) 0x433a2f LEA	(%R9,%RCX,8),%RSI

(229) 0x433a33 MOVSXD	%R8D,%RDI

(229) 0x433a36 MOV	0x68(%RSP),%RCX

(229) 0x433a3b LEA	(%R11,%RAX,1),%R10

(229) 0x433a3f ADD	%R15,%RDI

(229) 0x433a42 VMOVSD	(%RCX,%R10,8),%XMM0

(229) 0x433a48 VMOVSD	(%R14,%RDI,8),%XMM5

(229) 0x433a4e LEA	(%R15,%RAX,1),%R10

(229) 0x433a52 VFMADD132SD	(%RSI),%XMM5,%XMM0

(229) 0x433a57 LEA	(%R14,%R10,8),%RCX

(229) 0x433a5b MOV	0x60(%RSP),%R10

(229) 0x433a60 MOV	0x70(%RSP),%R8

(229) 0x433a65 ADD	%R10,%RAX

(229) 0x433a68 VSUBSD	(%RCX),%XMM0,%XMM1

(229) 0x433a6c VDIVSD	(%R8,%RAX,8),%XMM1,%XMM2

(229) 0x433a72 VMOVSD	%XMM2,(%RSI)

(229) 0x433a76 MOV	0x7c(%RSP),%ESI

(229) 0x433a7a LEA	0x1(%R13),%EAX

(229) 0x433a7e CMP	%ESI,%EAX

(229) 0x433a80 JAE	433b1d

(229) 0x433a86 LEA	0x1(%RDX),%EAX

(229) 0x433a89 CLTQ

(229) 0x433a8b LEA	(%RBX,%RAX,1),%RDI

(229) 0x433a8f LEA	(%R15,%RAX,1),%R8

(229) 0x433a93 LEA	(%R9,%RDI,8),%RSI

(229) 0x433a97 LEA	(%R14,%R8,8),%RDI

(229) 0x433a9b MOV	%RDI,0x60(%RSP)

(229) 0x433aa0 MOV	0x68(%RSP),%RDI

(229) 0x433aa5 LEA	(%R11,%RAX,1),%R8

(229) 0x433aa9 VMOVSD	(%RDI,%R8,8),%XMM6

(229) 0x433aaf MOV	0x60(%RSP),%R8

(229) 0x433ab4 ADD	%R10,%RAX

(229) 0x433ab7 VMOVSD	(%R8),%XMM3

(229) 0x433abc MOV	0x70(%RSP),%R8

(229) 0x433ac1 VFMSUB132SD	(%RSI),%XMM3,%XMM6

(229) 0x433ac6 ADD	$0x2,%R13D

(229) 0x433aca VADDSD	(%RCX),%XMM6,%XMM4

(229) 0x433ace MOV	0x7c(%RSP),%ECX

(229) 0x433ad2 VDIVSD	(%R8,%RAX,8),%XMM4,%XMM7

(229) 0x433ad8 VMOVSD	%XMM7,(%RSI)

(229) 0x433adc CMP	%ECX,%R13D

(229) 0x433adf JAE	433b1d

(229) 0x433ae1 ADD	$0x2,%EDX

(229) 0x433ae4 MOVSXD	%EDX,%R13

(229) 0x433ae7 ADD	%R13,%R11

(229) 0x433aea ADD	%R13,%R15

(229) 0x433aed VMOVSD	(%R14,%R15,8),%XMM9

(229) 0x433af3 VMOVSD	(%RDI,%R11,8),%XMM8

(229) 0x433af9 ADD	%R13,%RBX

(229) 0x433afc LEA	(%R9,%RBX,8),%R9

(229) 0x433b00 VFMSUB132SD	(%R9),%XMM9,%XMM8

(229) 0x433b05 MOV	0x60(%RSP),%R14

(229) 0x433b0a ADD	%R13,%R10

(229) 0x433b0d VADDSD	(%R14),%XMM8,%XMM10

(229) 0x433b12 VDIVSD	(%R8,%R10,8),%XMM10,%XMM11

(229) 0x433b18 VMOVSD	%XMM11,(%R9)

(229) 0x433b1d MOV	0x7c(%RSP),%R13D

(229) 0x433b22 INC	%R12

(229) 0x433b25 CMP	%R12D,0x44(%RSP)

(229) 0x433b2a JLE	433b40

(229) 0x433b2c MOV	0x3c(%RSP),%ESI

(229) 0x433b30 MOV	0x78(%RSP),%ECX

(229) 0x433b34 MOV	0x40(%RSP),%EDI

(229) 0x433b38 SUB	%R13D,%ESI

(229) 0x433b3b JMP	433750

0x433b40 VZEROUPPER

0x433b43 LEA	-0x28(%RBP),%RSP

0x433b47 POP	%RBX

0x433b48 POP	%R12

0x433b4a POP	%R13

0x433b4c POP	%R14

0x433b4e POP	%R15

0x433b50 POP	%RBP

0x433b51 RET

0x433b52 NOPW	(%RAX,%RAX,1)

(229) 0x433b58 MOV	%EDI,%EDX

(229) 0x433b5a XOR	%R10D,%R10D

(229) 0x433b5d JMP	433994

0x433b62 INC	%ESI

0x433b64 XOR	%EDX,%EDX

0x433b66 JMP	4336f1

0x433b6b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.67 to 3.00 cycles (4.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	78
nb uops	88
loop length	262
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

2% of peak load performance is reached (4.09 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 433670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433b62 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4336f1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	78
nb uops	88
loop length	262
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.00	5.87	5.70	8.00	8.00	8.00	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

2% of peak load performance is reached (4.09 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 433670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%R14),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x3(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433b62 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ESI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433b43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x78(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4336f1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.33	1.25
▼Loop 229 - advec_mom.cpp:148-149 - exec–	0.00	0.01
○Loop 230 - advec_mom.cpp:149-149 - exec	4.33	1.25

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code