OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:85-88 [...]	Coverage (incl. loops): 1.00% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 85 - 88

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4331a0 PUSH	%RBP

0x4331a1 MOV	%RSP,%RBP

0x4331a4 PUSH	%R15

0x4331a6 PUSH	%R14

0x4331a8 PUSH	%R13

0x4331aa PUSH	%R12

0x4331ac PUSH	%RBX

0x4331ad AND	$-0x40,%RSP

0x4331b1 SUB	$0x40,%RSP

0x4331b5 MOV	0x18(%RDI),%EAX

0x4331b8 MOV	0x1c(%RDI),%EDX

0x4331bb MOV	0x10(%RDI),%ESI

0x4331be ADD	$0x3,%EDX

0x4331c1 DEC	%ESI

0x4331c3 LEA	0x1(%RAX),%R13D

0x4331c7 MOV	%EDX,0x20(%RSP)

0x4331cb MOV	%ESI,0x1c(%RSP)

0x4331cf MOV	0x14(%RDI),%ECX

0x4331d2 CMP	%EDX,%R13D

0x4331d5 JGE	433643

0x4331db MOV	%EDX,%EBX

0x4331dd LEA	0x4(%RCX),%R15D

0x4331e1 SUB	%R13D,%EBX

0x4331e4 CMP	%R15D,%ESI

0x4331e7 JGE	433643

0x4331ed MOV	%RDI,%R14

0x4331f0 MOV	%R15D,%EDI

0x4331f3 SUB	%ESI,%EDI

0x4331f5 MOV	%EDI,0x24(%RSP)

0x4331f9 CALL	404630 <omp_get_num_threads@plt>

0x4331fe MOV	%EAX,%R12D

0x433201 CALL	404520 <omp_get_thread_num@plt>

0x433206 MOV	%EAX,%R8D

0x433209 MOV	0x24(%RSP),%EAX

0x43320d XOR	%EDX,%EDX

0x43320f IMUL	%EBX,%EAX

0x433212 DIV	%R12D

0x433215 MOV	%EAX,%ECX

0x433217 CMP	%EDX,%R8D

0x43321a JB	433664

0x433220 IMUL	%ECX,%R8D

0x433224 LEA	(%R8,%RDX,1),%R12D

0x433228 LEA	(%RCX,%R12,1),%R9D

0x43322c MOV	%R9D,0x18(%RSP)

0x433231 CMP	%R9D,%R12D

0x433234 JAE	433643

0x43323a MOV	%R12D,%EAX

0x43323d XOR	%EDX,%EDX

0x43323f DIVL	0x24(%RSP)

0x433243 MOV	0x1c(%RSP),%R10D

0x433248 MOV	(%R14),%R11

0x43324b MOV	0x8(%R14),%RSI

0x43324f VMOVSD	0x3c549(%RIP),%XMM3

0x433257 MOV	%R11,0x10(%RSP)

0x43325c MOV	%RSI,0x8(%RSP)

0x433261 VBROADCASTSD	%XMM3,%YMM4

0x433266 VBROADCASTSD	%XMM3,%ZMM1

0x43326c ADD	%EDX,%R10D

0x43326f MOV	%R10D,0x3c(%RSP)

0x433274 ADD	%R13D,%EAX

0x433277 SUB	%R10D,%R15D

0x43327a MOVSXD	%EAX,%R13

0x43327d NOPL	(%RAX)

(227) 0x433280 CMP	%R15D,%ECX

(227) 0x433283 MOV	%R15D,%EDX

(227) 0x433286 CMOVBE	%ECX,%EDX

(227) 0x433289 LEA	(%R12,%RDX,1),%R15D

(227) 0x43328d MOV	%R15D,0x38(%RSP)

(227) 0x433292 CMP	%R15D,%R12D

(227) 0x433295 JAE	433617

(227) 0x43329b MOV	0x10(%RSP),%RBX

(227) 0x4332a0 MOV	0x8(%RSP),%R8

(227) 0x4332a5 MOV	(%RBX),%R14

(227) 0x4332a8 MOV	0x10(%RBX),%RCX

(227) 0x4332ac MOV	(%R8),%RBX

(227) 0x4332af MOV	0x10(%R8),%R15

(227) 0x4332b3 IMUL	%R13,%RBX

(227) 0x4332b7 LEA	-0x1(%R13),%EDI

(227) 0x4332bb MOVSXD	%EDI,%RSI

(227) 0x4332be LEA	-0x1(%RDX),%R9D

(227) 0x4332c2 IMUL	%R14,%RSI

(227) 0x4332c6 MOV	%R15,0x28(%RSP)

(227) 0x4332cb IMUL	%R13,%R14

(227) 0x4332cf MOV	%RBX,0x30(%RSP)

(227) 0x4332d4 CMP	$0x6,%R9D

(227) 0x4332d8 JBE	433658

(227) 0x4332de MOVSXD	0x3c(%RSP),%RAX

(227) 0x4332e3 LEA	(%RSI,%RAX,1),%R8

(227) 0x4332e7 LEA	(%R14,%RAX,1),%RDI

(227) 0x4332eb SAL	$0x3,%R8

(227) 0x4332ef SAL	$0x3,%RDI

(227) 0x4332f3 ADD	%RBX,%RAX

(227) 0x4332f6 LEA	(%RCX,%R8,1),%R11

(227) 0x4332fa LEA	(%RCX,%RDI,1),%R10

(227) 0x4332fe LEA	0x8(%RCX,%R8,1),%R9

(227) 0x433303 LEA	0x8(%RCX,%RDI,1),%R8

(227) 0x433308 LEA	(%R15,%RAX,8),%RDI

(227) 0x43330c MOV	%EDX,%R15D

(227) 0x43330f SHR	$0x3,%R15D

(227) 0x433313 SAL	$0x6,%R15

(227) 0x433317 LEA	-0x40(%R15),%RBX

(227) 0x43331b SHR	$0x6,%RBX

(227) 0x43331f INC	%RBX

(227) 0x433322 XOR	%EAX,%EAX

(227) 0x433324 AND	$0x3,%EBX

(227) 0x433327 JE	4333d7

(227) 0x43332d CMP	$0x1,%RBX

(227) 0x433331 JE	43339b

(227) 0x433333 CMP	$0x2,%RBX

(227) 0x433337 JE	433368

(227) 0x433339 VMOVUPD	(%R11),%ZMM0

(227) 0x43333f VMOVUPD	(%R9),%ZMM2

(227) 0x433345 VADDPD	(%R10),%ZMM0,%ZMM5

(227) 0x43334b VADDPD	(%R8),%ZMM2,%ZMM6

(227) 0x433351 MOV	$0x40,%EAX

(227) 0x433356 VADDPD	%ZMM6,%ZMM5,%ZMM7

(227) 0x43335c VMULPD	%ZMM1,%ZMM7,%ZMM8

(227) 0x433362 VMOVUPD	%ZMM8,(%RDI)

(227) 0x433368 VMOVUPD	(%R11,%RAX,1),%ZMM9

(227) 0x43336f VMOVUPD	(%R9,%RAX,1),%ZMM11

(227) 0x433376 VADDPD	(%R10,%RAX,1),%ZMM9,%ZMM10

(227) 0x43337d VADDPD	(%R8,%RAX,1),%ZMM11,%ZMM12

(227) 0x433384 VADDPD	%ZMM12,%ZMM10,%ZMM13

(227) 0x43338a VMULPD	%ZMM1,%ZMM13,%ZMM14

(227) 0x433390 VMOVUPD	%ZMM14,(%RDI,%RAX,1)

(227) 0x433397 ADD	$0x40,%RAX

(227) 0x43339b VMOVUPD	(%R11,%RAX,1),%ZMM15

(227) 0x4333a2 VMOVUPD	(%R9,%RAX,1),%ZMM5

(227) 0x4333a9 VADDPD	(%R10,%RAX,1),%ZMM15,%ZMM0

(227) 0x4333b0 VADDPD	(%R8,%RAX,1),%ZMM5,%ZMM2

(227) 0x4333b7 VADDPD	%ZMM2,%ZMM0,%ZMM6

(227) 0x4333bd VMULPD	%ZMM1,%ZMM6,%ZMM7

(227) 0x4333c3 VMOVUPD	%ZMM7,(%RDI,%RAX,1)

(227) 0x4333ca ADD	$0x40,%RAX

(227) 0x4333ce CMP	%RAX,%R15

(227) 0x4333d1 JE	4334b1

  (228) 0x4333d7 VMOVUPD	(%R11,%RAX,1),%ZMM8

  (228) 0x4333de VMOVUPD	(%R9,%RAX,1),%ZMM10

  (228) 0x4333e5 VADDPD	(%R10,%RAX,1),%ZMM8,%ZMM9

  (228) 0x4333ec VADDPD	(%R8,%RAX,1),%ZMM10,%ZMM11

  (228) 0x4333f3 VADDPD	%ZMM11,%ZMM9,%ZMM12

  (228) 0x4333f9 VMULPD	%ZMM1,%ZMM12,%ZMM13

  (228) 0x4333ff VMOVUPD	%ZMM13,(%RDI,%RAX,1)

  (228) 0x433406 VMOVUPD	0x40(%R11,%RAX,1),%ZMM14

  (228) 0x43340e VMOVUPD	0x40(%R9,%RAX,1),%ZMM0

  (228) 0x433416 VADDPD	0x40(%R10,%RAX,1),%ZMM14,%ZMM15

  (228) 0x43341e VADDPD	0x40(%R8,%RAX,1),%ZMM0,%ZMM5

  (228) 0x433426 VADDPD	%ZMM5,%ZMM15,%ZMM2

  (228) 0x43342c VMULPD	%ZMM1,%ZMM2,%ZMM6

  (228) 0x433432 VMOVUPD	%ZMM6,0x40(%RDI,%RAX,1)

  (228) 0x43343a VMOVUPD	0x80(%R11,%RAX,1),%ZMM7

  (228) 0x433442 VMOVUPD	0x80(%R9,%RAX,1),%ZMM9

  (228) 0x43344a VADDPD	0x80(%R10,%RAX,1),%ZMM7,%ZMM8

  (228) 0x433452 VADDPD	0x80(%R8,%RAX,1),%ZMM9,%ZMM10

  (228) 0x43345a VADDPD	%ZMM10,%ZMM8,%ZMM11

  (228) 0x433460 VMULPD	%ZMM1,%ZMM11,%ZMM12

  (228) 0x433466 VMOVUPD	%ZMM12,0x80(%RDI,%RAX,1)

  (228) 0x43346e VMOVUPD	0xc0(%R11,%RAX,1),%ZMM13

  (228) 0x433476 VMOVUPD	0xc0(%R9,%RAX,1),%ZMM15

  (228) 0x43347e VADDPD	0xc0(%R10,%RAX,1),%ZMM13,%ZMM14

  (228) 0x433486 VADDPD	0xc0(%R8,%RAX,1),%ZMM15,%ZMM0

  (228) 0x43348e VADDPD	%ZMM0,%ZMM14,%ZMM5

  (228) 0x433494 VMULPD	%ZMM1,%ZMM5,%ZMM2

  (228) 0x43349a VMOVUPD	%ZMM2,0xc0(%RDI,%RAX,1)

  (228) 0x4334a2 ADD	$0x100,%RAX

  (228) 0x4334a8 CMP	%RAX,%R15

  (228) 0x4334ab JNE	4333d7

(227) 0x4334b1 MOV	0x3c(%RSP),%EAX

(227) 0x4334b5 MOV	%EDX,%R11D

(227) 0x4334b8 AND	$-0x8,%R11D

(227) 0x4334bc ADD	%R11D,%EAX

(227) 0x4334bf ADD	%R11D,%R12D

(227) 0x4334c2 TEST	$0x7,%DL

(227) 0x4334c5 JE	433612

(227) 0x4334cb SUB	%R11D,%EDX

(227) 0x4334ce LEA	-0x1(%RDX),%R10D

(227) 0x4334d2 CMP	$0x2,%R10D

(227) 0x4334d6 JBE	433535

(227) 0x4334d8 MOVSXD	0x3c(%RSP),%R8

(227) 0x4334dd MOV	0x30(%RSP),%R15

(227) 0x4334e2 LEA	(%R14,%R8,1),%RDI

(227) 0x4334e6 ADD	%R11,%RDI

(227) 0x4334e9 VMOVUPD	0x8(%RCX,%RDI,8),%YMM6

(227) 0x4334ef VMOVUPD	(%RCX,%RDI,8),%YMM8

(227) 0x4334f4 LEA	(%RSI,%R8,1),%R9

(227) 0x4334f8 ADD	%R11,%R9

(227) 0x4334fb VADDPD	0x8(%RCX,%R9,8),%YMM6,%YMM7

(227) 0x433502 VADDPD	(%RCX,%R9,8),%YMM8,%YMM9

(227) 0x433508 ADD	%R15,%R8

(227) 0x43350b MOV	%EDX,%EBX

(227) 0x43350d VADDPD	%YMM9,%YMM7,%YMM10

(227) 0x433512 ADD	%R11,%R8

(227) 0x433515 AND	$-0x4,%EBX

(227) 0x433518 VMULPD	%YMM4,%YMM10,%YMM11

(227) 0x43351c MOV	0x28(%RSP),%R11

(227) 0x433521 ADD	%EBX,%EAX

(227) 0x433523 ADD	%EBX,%R12D

(227) 0x433526 AND	$0x3,%EDX

(227) 0x433529 VMOVUPD	%YMM11,(%R11,%R8,8)

(227) 0x43352f JE	433612

(227) 0x433535 LEA	0x1(%RAX),%R10D

(227) 0x433539 MOVSXD	%R10D,%RDI

(227) 0x43353c MOVSXD	%EAX,%RDX

(227) 0x43353f LEA	(%RDI,%RSI,1),%R8

(227) 0x433543 LEA	(%R14,%RDX,1),%R15

(227) 0x433547 MOV	0x30(%RSP),%RBX

(227) 0x43354c LEA	(%RCX,%R8,8),%R8

(227) 0x433550 VMOVSD	(%RCX,%R15,8),%XMM12

(227) 0x433556 VMOVSD	(%R8),%XMM14

(227) 0x43355b LEA	(%RDI,%R14,1),%R9

(227) 0x43355f LEA	(%RBX,%RDX,1),%R10

(227) 0x433563 LEA	(%RCX,%R9,8),%R9

(227) 0x433567 ADD	%RSI,%RDX

(227) 0x43356a VADDSD	(%RCX,%RDX,8),%XMM12,%XMM13

(227) 0x43356f VADDSD	(%R9),%XMM14,%XMM15

(227) 0x433574 MOV	0x28(%RSP),%R15

(227) 0x433579 MOV	0x38(%RSP),%R11D

(227) 0x43357e VADDSD	%XMM15,%XMM13,%XMM0

(227) 0x433583 LEA	0x1(%R12),%EDX

(227) 0x433588 VMULSD	%XMM3,%XMM0,%XMM5

(227) 0x43358c VMOVSD	%XMM5,(%R15,%R10,8)

(227) 0x433592 CMP	%R11D,%EDX

(227) 0x433595 JAE	433612

(227) 0x433597 LEA	0x2(%RAX),%R10D

(227) 0x43359b MOVSXD	%R10D,%RDX

(227) 0x43359e LEA	(%R14,%RDX,1),%R10

(227) 0x4335a2 LEA	(%RCX,%R10,8),%R10

(227) 0x4335a6 VMOVSD	(%R9),%XMM2

(227) 0x4335ab VMOVSD	(%R10),%XMM7

(227) 0x4335b0 LEA	(%RSI,%RDX,1),%R11

(227) 0x4335b4 LEA	(%RCX,%R11,8),%R11

(227) 0x4335b8 VADDSD	(%R8),%XMM2,%XMM6

(227) 0x4335bd VADDSD	(%R11),%XMM7,%XMM8

(227) 0x4335c2 ADD	%RBX,%RDI

(227) 0x4335c5 ADD	$0x2,%R12D

(227) 0x4335c9 VADDSD	%XMM8,%XMM6,%XMM9

(227) 0x4335ce VMULSD	%XMM3,%XMM9,%XMM10

(227) 0x4335d2 VMOVSD	%XMM10,(%R15,%RDI,8)

(227) 0x4335d8 MOV	0x38(%RSP),%EDI

(227) 0x4335dc CMP	%EDI,%R12D

(227) 0x4335df JAE	433612

(227) 0x4335e1 ADD	$0x3,%EAX

(227) 0x4335e4 CLTQ

(227) 0x4335e6 ADD	%RAX,%RSI

(227) 0x4335e9 VMOVSD	(%RCX,%RSI,8),%XMM11

(227) 0x4335ee VMOVSD	(%R11),%XMM13

(227) 0x4335f3 ADD	%R14,%RAX

(227) 0x4335f6 VADDSD	(%RCX,%RAX,8),%XMM11,%XMM12

(227) 0x4335fb VADDSD	(%R10),%XMM13,%XMM14

(227) 0x433600 ADD	%RDX,%RBX

(227) 0x433603 VADDSD	%XMM14,%XMM12,%XMM15

(227) 0x433608 VMULSD	%XMM3,%XMM15,%XMM0

(227) 0x43360c VMOVSD	%XMM0,(%R15,%RBX,8)

(227) 0x433612 MOV	0x38(%RSP),%R12D

(227) 0x433617 INC	%R13

(227) 0x43361a CMP	%R13D,0x20(%RSP)

(227) 0x43361f JLE	433640

(227) 0x433621 MOV	0x18(%RSP),%ECX

(227) 0x433625 MOV	0x1c(%RSP),%R14D

(227) 0x43362a MOV	0x24(%RSP),%R15D

(227) 0x43362f MOV	%R14D,0x3c(%RSP)

(227) 0x433634 SUB	%R12D,%ECX

(227) 0x433637 JMP	433280

0x43363c NOPL	(%RAX)

0x433640 VZEROUPPER

0x433643 LEA	-0x28(%RBP),%RSP

0x433647 POP	%RBX

0x433648 POP	%R12

0x43364a POP	%R13

0x43364c POP	%R14

0x43364e POP	%R15

0x433650 POP	%RBP

0x433651 RET

0x433652 NOPW	(%RAX,%RAX,1)

(227) 0x433658 MOV	0x3c(%RSP),%EAX

(227) 0x43365c XOR	%R11D,%R11D

(227) 0x43365f JMP	4334cb

0x433664 INC	%ECX

0x433666 XOR	%EDX,%EDX

0x433668 JMP	433220

0x43366d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.65	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.35	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.17 cycles (6.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.67 to 3.00 cycles (4.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	88
loop length	264
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67
cycles	6.30	11.73	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (3.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4331a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x14(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433664 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4c4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R12,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x24(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x1c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3c549(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 433220 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.17 cycles (6.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 13.50 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	88
loop length	264
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67
cycles	6.30	11.73	5.67	5.67	7.50	6.20	6.30	7.50	7.50	7.50	6.20	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.67
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.67

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (3.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4331a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
DEC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%RAX),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x14(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R13D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433664 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4c4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %ECX,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RCX,%R12,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433643 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x24(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x1c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3c549(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVSXD %EAX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 433220 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.00	0.29
▼Loop 227 - advec_mom.cpp:87-88 - exec–	0.00	0.01
○Loop 228 - advec_mom.cpp:88-88 - exec	1.00	0.29

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Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code