OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 3.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4328d0 PUSH	%RBP

0x4328d1 MOV	%RSP,%RBP

0x4328d4 PUSH	%R15

0x4328d6 PUSH	%R14

0x4328d8 PUSH	%R13

0x4328da PUSH	%R12

0x4328dc PUSH	%RBX

0x4328dd MOV	%RDI,%RBX

0x4328e0 AND	$-0x40,%RSP

0x4328e4 SUB	$0x100,%RSP

0x4328eb MOV	0x30(%RBX),%EAX

0x4328ee MOV	0x34(%RBX),%EDX

0x4328f1 MOV	0x28(%RDI),%EDI

0x4328f4 ADD	$0x3,%EDX

0x4328f7 LEA	0x1(%RAX),%R12D

0x4328fb MOV	%EDI,0x74(%RSP)

0x4328ff MOV	%EDX,0x78(%RSP)

0x432903 MOV	0x2c(%RBX),%ESI

0x432906 CMP	%EDX,%R12D

0x432909 JGE	433163

0x43290f MOV	%EDX,%R14D

0x432912 LEA	0x4(%RSI),%R15D

0x432916 SUB	%R12D,%R14D

0x432919 CMP	%R15D,%EDI

0x43291c JGE	433163

0x432922 MOV	%R15D,%ECX

0x432925 SUB	%EDI,%ECX

0x432927 MOV	%ECX,0x7c(%RSP)

0x43292b CALL	404630 <omp_get_num_threads@plt>

0x432930 MOV	%EAX,%R13D

0x432933 CALL	404520 <omp_get_thread_num@plt>

0x432938 MOV	%EAX,%R8D

0x43293b MOV	0x7c(%RSP),%EAX

0x43293f XOR	%EDX,%EDX

0x432941 IMUL	%R14D,%EAX

0x432945 DIV	%R13D

0x432948 MOV	%EAX,%R13D

0x43294b CMP	%EDX,%R8D

0x43294e JB	433187

0x432954 IMUL	%R13D,%R8D

0x432958 LEA	(%R8,%RDX,1),%EAX

0x43295c LEA	(%R13,%RAX,1),%R9D

0x432961 MOV	%EAX,0xfc(%RSP)

0x432968 MOV	%R9D,0x70(%RSP)

0x43296d CMP	%R9D,%EAX

0x432970 JAE	433163

0x432976 XOR	%EDX,%EDX

0x432978 DIVL	0x7c(%RSP)

0x43297c MOV	0x74(%RSP),%R10D

0x432981 MOV	(%RBX),%RDI

0x432984 MOV	0x20(%RBX),%RSI

0x432988 MOV	0x8(%RBX),%R14

0x43298c VMOVSD	0x3ce0c(%RIP),%XMM3

0x432994 MOV	%RDI,0x58(%RSP)

0x432999 MOV	%RSI,0x50(%RSP)

0x43299e MOV	%R14,0x40(%RSP)

0x4329a3 VBROADCASTSD	%XMM3,%YMM4

0x4329a8 VBROADCASTSD	%XMM3,%ZMM2

0x4329ae LEA	(%RDX,%R10,1),%R11D

0x4329b2 ADD	%R12D,%EAX

0x4329b5 MOV	%R15D,%R10D

0x4329b8 MOV	0x10(%RBX),%R15

0x4329bc MOV	0x18(%RBX),%RBX

0x4329c0 MOVSXD	%EAX,%R12

0x4329c3 MOV	%R11D,0xa4(%RSP)

0x4329cb MOV	%R15,0x48(%RSP)

0x4329d0 MOV	%RBX,0x38(%RSP)

0x4329d5 MOV	%R12,0xd0(%RSP)

0x4329dd SUB	%R11D,%R10D

(225) 0x4329e0 CMP	%R10D,%R13D

(225) 0x4329e3 CMOVBE	%R13D,%R10D

(225) 0x4329e7 MOV	0xfc(%RSP),%ECX

(225) 0x4329ee MOV	%R10D,0xf8(%RSP)

(225) 0x4329f6 LEA	(%RCX,%R10,1),%R13D

(225) 0x4329fa MOV	%R13D,0xa0(%RSP)

(225) 0x432a02 CMP	%R13D,%ECX

(225) 0x432a05 JAE	433121

(225) 0x432a0b MOV	0x48(%RSP),%RSI

(225) 0x432a10 MOV	%R10D,%R12D

(225) 0x432a13 MOV	0xd0(%RSP),%R10

(225) 0x432a1b MOV	0x58(%RSP),%R9

(225) 0x432a20 MOV	0x50(%RSP),%RDI

(225) 0x432a25 LEA	-0x1(%R10),%EAX

(225) 0x432a29 MOV	(%RSI),%RCX

(225) 0x432a2c MOV	(%R9),%RDX

(225) 0x432a2f MOVSXD	%EAX,%R8

(225) 0x432a32 MOV	0x10(%R9),%R13

(225) 0x432a36 MOV	(%RDI),%R9

(225) 0x432a39 IMUL	%R10,%RCX

(225) 0x432a3d MOV	%R8,%R11

(225) 0x432a40 MOV	%R10,%R14

(225) 0x432a43 MOV	0x10(%RSI),%RBX

(225) 0x432a47 IMUL	%RDX,%R11

(225) 0x432a4b IMUL	%R9,%R8

(225) 0x432a4f IMUL	%R10,%RDX

(225) 0x432a53 IMUL	%R10,%R9

(225) 0x432a57 MOV	0x38(%RSP),%RSI

(225) 0x432a5c MOV	0x40(%RSP),%R10

(225) 0x432a61 MOV	%RCX,0xb0(%RSP)

(225) 0x432a69 MOV	0x10(%RDI),%R15

(225) 0x432a6d MOV	(%RSI),%RCX

(225) 0x432a70 MOV	(%R10),%RDI

(225) 0x432a73 IMUL	%R14,%RCX

(225) 0x432a77 IMUL	%R14,%RDI

(225) 0x432a7b MOV	%RBX,0xb8(%RSP)

(225) 0x432a83 MOV	0x10(%R10),%RAX

(225) 0x432a87 MOV	0x10(%RSI),%RBX

(225) 0x432a8b MOV	%R12D,%R14D

(225) 0x432a8e DEC	%R14D

(225) 0x432a91 MOV	%R11,0x98(%RSP)

(225) 0x432a99 MOV	%R8,0xd8(%RSP)

(225) 0x432aa1 MOV	%RDX,0xa8(%RSP)

(225) 0x432aa9 MOV	%R9,0xe0(%RSP)

(225) 0x432ab1 MOV	%RAX,0xf0(%RSP)

(225) 0x432ab9 MOV	%RDI,0xe8(%RSP)

(225) 0x432ac1 MOV	%RBX,0xc0(%RSP)

(225) 0x432ac9 MOV	%RCX,0xc8(%RSP)

(225) 0x432ad1 CMP	$0x6,%R14D

(225) 0x432ad5 JBE	433178

(225) 0x432adb MOVSXD	0xa4(%RSP),%RAX

(225) 0x432ae3 MOV	0xb0(%RSP),%RSI

(225) 0x432aeb LEA	(%R8,%RAX,1),%R10

(225) 0x432aef LEA	(%RDX,%RAX,1),%RDI

(225) 0x432af3 LEA	(%R9,%RAX,1),%RDX

(225) 0x432af7 SAL	$0x3,%R10

(225) 0x432afb SAL	$0x3,%RDX

(225) 0x432aff LEA	(%R11,%RAX,1),%R11

(225) 0x432b03 SAL	$0x3,%R11

(225) 0x432b07 SAL	$0x3,%RDI

(225) 0x432b0b LEA	(%R15,%R10,1),%R8

(225) 0x432b0f LEA	(%R15,%RDX,1),%R9

(225) 0x432b13 MOV	%R8,0x88(%RSP)

(225) 0x432b1b MOV	%R9,0x90(%RSP)

(225) 0x432b23 LEA	(%R13,%R11,1),%RBX

(225) 0x432b28 LEA	(%R13,%RDI,1),%R14

(225) 0x432b2d LEA	-0x8(%R13,%R11,1),%R8

(225) 0x432b32 LEA	-0x8(%R15,%R10,1),%R9

(225) 0x432b37 LEA	-0x8(%R13,%RDI,1),%R11

(225) 0x432b3c LEA	-0x8(%R15,%RDX,1),%R10

(225) 0x432b41 MOV	0xb8(%RSP),%RDI

(225) 0x432b49 MOV	0xe8(%RSP),%RDX

(225) 0x432b51 LEA	(%RSI,%RAX,1),%RCX

(225) 0x432b55 LEA	(%RDX,%RAX,1),%RDX

(225) 0x432b59 LEA	(%RDI,%RCX,8),%RDI

(225) 0x432b5d MOV	0xf0(%RSP),%RCX

(225) 0x432b65 SAL	$0x3,%RDX

(225) 0x432b69 LEA	-0x8(%RCX,%RDX,1),%RSI

(225) 0x432b6e ADD	%RCX,%RDX

(225) 0x432b71 MOV	0xc8(%RSP),%RCX

(225) 0x432b79 ADD	%RCX,%RAX

(225) 0x432b7c MOV	0xc0(%RSP),%RCX

(225) 0x432b84 LEA	(%RCX,%RAX,8),%RCX

(225) 0x432b88 MOV	%R12D,%EAX

(225) 0x432b8b SHR	$0x3,%EAX

(225) 0x432b8e MOV	%RAX,%R12

(225) 0x432b91 SAL	$0x6,%RAX

(225) 0x432b95 MOV	%RAX,0x80(%RSP)

(225) 0x432b9d XOR	%EAX,%EAX

(225) 0x432b9f AND	$0x1,%R12D

(225) 0x432ba3 JE	432c2a

(225) 0x432ba9 VMOVUPD	(%R14),%ZMM0

(225) 0x432baf VMOVUPD	(%R11),%ZMM1

(225) 0x432bb5 MOV	0x90(%RSP),%RAX

(225) 0x432bbd VMULPD	(%R10),%ZMM1,%ZMM6

(225) 0x432bc3 VMULPD	(%RAX),%ZMM0,%ZMM5

(225) 0x432bc9 MOV	0x88(%RSP),%R12

(225) 0x432bd1 VMOVUPD	(%R9),%ZMM8

(225) 0x432bd7 VMOVUPD	(%R12),%ZMM7

(225) 0x432bde VFMADD231PD	(%R8),%ZMM8,%ZMM6

(225) 0x432be4 VFMADD231PD	(%RBX),%ZMM7,%ZMM5

(225) 0x432bea MOV	0x80(%RSP),%R12

(225) 0x432bf2 MOV	$0x40,%EAX

(225) 0x432bf7 VADDPD	%ZMM6,%ZMM5,%ZMM9

(225) 0x432bfd VMULPD	%ZMM2,%ZMM9,%ZMM10

(225) 0x432c03 VMOVUPD	%ZMM10,(%RDI)

(225) 0x432c09 VMOVUPD	(%RDX),%ZMM11

(225) 0x432c0f VSUBPD	(%RSI),%ZMM11,%ZMM12

(225) 0x432c15 VADDPD	%ZMM10,%ZMM12,%ZMM13

(225) 0x432c1b VMOVUPD	%ZMM13,(%RCX)

(225) 0x432c21 CMP	%R12,%RAX

(225) 0x432c24 JE	432d3c

(225) 0x432c2a MOV	%R15,0x68(%RSP)

(225) 0x432c2f MOV	%R13,0x60(%RSP)

(225) 0x432c34 MOV	0x88(%RSP),%R12

(225) 0x432c3c MOV	0x90(%RSP),%R13

(225) 0x432c44 MOV	0x80(%RSP),%R15

  (226) 0x432c4c VMOVUPD	(%R14,%RAX,1),%ZMM14

  (226) 0x432c53 VMOVUPD	(%R11,%RAX,1),%ZMM5

  (226) 0x432c5a VMULPD	(%R13,%RAX,1),%ZMM14,%ZMM15

  (226) 0x432c62 VMULPD	(%R10,%RAX,1),%ZMM5,%ZMM7

  (226) 0x432c69 VMOVUPD	(%R12,%RAX,1),%ZMM0

  (226) 0x432c70 VMOVUPD	(%R9,%RAX,1),%ZMM1

  (226) 0x432c77 VFMADD231PD	(%RBX,%RAX,1),%ZMM0,%ZMM15

  (226) 0x432c7e VFMADD231PD	(%R8,%RAX,1),%ZMM1,%ZMM7

  (226) 0x432c85 VADDPD	%ZMM7,%ZMM15,%ZMM6

  (226) 0x432c8b VMULPD	%ZMM2,%ZMM6,%ZMM8

  (226) 0x432c91 VMOVUPD	%ZMM8,(%RDI,%RAX,1)

  (226) 0x432c98 VMOVUPD	(%RDX,%RAX,1),%ZMM9

  (226) 0x432c9f VSUBPD	(%RSI,%RAX,1),%ZMM9,%ZMM10

  (226) 0x432ca6 VADDPD	%ZMM8,%ZMM10,%ZMM11

  (226) 0x432cac VMOVUPD	%ZMM11,(%RCX,%RAX,1)

  (226) 0x432cb3 VMOVUPD	0x40(%R14,%RAX,1),%ZMM12

  (226) 0x432cbb VMOVUPD	0x40(%R11,%RAX,1),%ZMM15

  (226) 0x432cc3 VMULPD	0x40(%R13,%RAX,1),%ZMM12,%ZMM13

  (226) 0x432ccb VMULPD	0x40(%R10,%RAX,1),%ZMM15,%ZMM0

  (226) 0x432cd3 VMOVUPD	0x40(%R12,%RAX,1),%ZMM14

  (226) 0x432cdb VMOVUPD	0x40(%R9,%RAX,1),%ZMM5

  (226) 0x432ce3 VFMADD231PD	0x40(%RBX,%RAX,1),%ZMM14,%ZMM13

  (226) 0x432ceb VFMADD231PD	0x40(%R8,%RAX,1),%ZMM5,%ZMM0

  (226) 0x432cf3 VADDPD	%ZMM0,%ZMM13,%ZMM7

  (226) 0x432cf9 VMULPD	%ZMM2,%ZMM7,%ZMM6

  (226) 0x432cff VMOVUPD	%ZMM6,0x40(%RDI,%RAX,1)

  (226) 0x432d07 VMOVUPD	0x40(%RDX,%RAX,1),%ZMM1

  (226) 0x432d0f VSUBPD	0x40(%RSI,%RAX,1),%ZMM1,%ZMM8

  (226) 0x432d17 VADDPD	%ZMM6,%ZMM8,%ZMM9

  (226) 0x432d1d VMOVUPD	%ZMM9,0x40(%RCX,%RAX,1)

  (226) 0x432d25 SUB	$-0x80,%RAX

  (226) 0x432d29 CMP	%R15,%RAX

  (226) 0x432d2c JNE	432c4c

(225) 0x432d32 MOV	0x68(%RSP),%R15

(225) 0x432d37 MOV	0x60(%RSP),%R13

(225) 0x432d3c MOV	0xf8(%RSP),%EBX

(225) 0x432d43 MOV	0xa4(%RSP),%EAX

(225) 0x432d4a MOV	%EBX,%R12D

(225) 0x432d4d AND	$-0x8,%R12D

(225) 0x432d51 ADD	%R12D,0xfc(%RSP)

(225) 0x432d59 ADD	%R12D,%EAX

(225) 0x432d5c AND	$0x7,%EBX

(225) 0x432d5f JE	433113

(225) 0x432d65 MOV	0xf8(%RSP),%R11D

(225) 0x432d6d SUB	%R12D,%R11D

(225) 0x432d70 LEA	-0x1(%R11),%R14D

(225) 0x432d74 CMP	$0x2,%R14D

(225) 0x432d78 JBE	432e75

(225) 0x432d7e MOVSXD	0xa4(%RSP),%RDX

(225) 0x432d86 MOV	0x98(%RSP),%R8

(225) 0x432d8e MOV	0xa8(%RSP),%R9

(225) 0x432d96 MOV	0xe0(%RSP),%R10

(225) 0x432d9e LEA	(%R8,%RDX,1),%RCX

(225) 0x432da2 LEA	(%R9,%RDX,1),%R8

(225) 0x432da6 LEA	(%R10,%RDX,1),%R9

(225) 0x432daa ADD	%R12,%R9

(225) 0x432dad VMOVUPD	(%R15,%R9,8),%YMM10

(225) 0x432db3 VMOVUPD	-0x8(%R15,%R9,8),%YMM13

(225) 0x432dba ADD	%R12,%R8

(225) 0x432dbd VMULPD	(%R13,%R8,8),%YMM10,%YMM11

(225) 0x432dc4 VMULPD	-0x8(%R13,%R8,8),%YMM13,%YMM14

(225) 0x432dcb MOV	0xd8(%RSP),%RDI

(225) 0x432dd3 ADD	%R12,%RCX

(225) 0x432dd6 VMOVUPD	(%R13,%RCX,8),%YMM12

(225) 0x432ddd VMOVUPD	-0x8(%R13,%RCX,8),%YMM15

(225) 0x432de4 ADD	%RDX,%RDI

(225) 0x432de7 ADD	%R12,%RDI

(225) 0x432dea VFMADD231PD	(%R15,%RDI,8),%YMM12,%YMM11

(225) 0x432df0 VFMADD231PD	-0x8(%R15,%RDI,8),%YMM15,%YMM14

(225) 0x432df7 MOV	0xb0(%RSP),%RBX

(225) 0x432dff MOV	0xe8(%RSP),%RSI

(225) 0x432e07 MOV	0xc8(%RSP),%R14

(225) 0x432e0f ADD	%RDX,%RBX

(225) 0x432e12 VADDPD	%YMM14,%YMM11,%YMM0

(225) 0x432e17 ADD	%RDX,%RSI

(225) 0x432e1a ADD	%R14,%RDX

(225) 0x432e1d VMULPD	%YMM4,%YMM0,%YMM5

(225) 0x432e21 ADD	%R12,%RSI

(225) 0x432e24 ADD	%R12,%RDX

(225) 0x432e27 ADD	%R12,%RBX

(225) 0x432e2a MOV	0xb8(%RSP),%R12

(225) 0x432e32 MOV	0xf0(%RSP),%RCX

(225) 0x432e3a VMOVUPD	%YMM5,(%R12,%RBX,8)

(225) 0x432e40 VMOVUPD	(%RCX,%RSI,8),%YMM7

(225) 0x432e45 MOV	0xc0(%RSP),%RDI

(225) 0x432e4d VSUBPD	-0x8(%RCX,%RSI,8),%YMM7,%YMM6

(225) 0x432e53 VADDPD	%YMM5,%YMM6,%YMM1

(225) 0x432e57 VMOVUPD	%YMM1,(%RDI,%RDX,8)

(225) 0x432e5c MOV	%R11D,%EDX

(225) 0x432e5f AND	$-0x4,%EDX

(225) 0x432e62 ADD	%EDX,0xfc(%RSP)

(225) 0x432e69 ADD	%EDX,%EAX

(225) 0x432e6b AND	$0x3,%R11D

(225) 0x432e6f JE	433113

(225) 0x432e75 MOV	0xd8(%RSP),%R10

(225) 0x432e7d MOV	0xe0(%RSP),%R12

(225) 0x432e85 MOV	0xa8(%RSP),%R9

(225) 0x432e8d MOVSXD	%EAX,%RDX

(225) 0x432e90 LEA	-0x1(%RAX),%ECX

(225) 0x432e93 MOVSXD	%ECX,%RCX

(225) 0x432e96 LEA	(%R10,%RDX,1),%R8

(225) 0x432e9a LEA	(%R12,%RDX,1),%RBX

(225) 0x432e9e ADD	%RDX,%R9

(225) 0x432ea1 ADD	%RCX,%R12

(225) 0x432ea4 LEA	(%R15,%R8,8),%RDI

(225) 0x432ea8 LEA	(%R13,%R9,8),%R8

(225) 0x432ead LEA	(%R15,%RBX,8),%R9

(225) 0x432eb1 MOV	0xa8(%RSP),%RBX

(225) 0x432eb9 VMOVSD	(%R15,%R12,8),%XMM11

(225) 0x432ebf VMOVSD	(%R9),%XMM8

(225) 0x432ec4 ADD	%RCX,%RBX

(225) 0x432ec7 MOV	0x98(%RSP),%R14

(225) 0x432ecf VMULSD	(%R13,%RBX,8),%XMM11,%XMM12

(225) 0x432ed6 VMULSD	(%R8),%XMM8,%XMM9

(225) 0x432edb LEA	(%R14,%RDX,1),%R11

(225) 0x432edf LEA	(%R13,%R11,8),%RSI

(225) 0x432ee4 LEA	(%RCX,%R10,1),%R11

(225) 0x432ee8 VMOVSD	(%R15,%R11,8),%XMM13

(225) 0x432eee VMOVSD	(%RDI),%XMM10

(225) 0x432ef2 LEA	(%RCX,%R14,1),%R10

(225) 0x432ef6 VFMADD231SD	(%R13,%R10,8),%XMM13,%XMM12

(225) 0x432efd VFMADD231SD	(%RSI),%XMM10,%XMM9

(225) 0x432f02 MOV	0xb0(%RSP),%R12

(225) 0x432f0a MOV	0xb8(%RSP),%R11

(225) 0x432f12 ADD	%RDX,%R12

(225) 0x432f15 MOV	0xc8(%RSP),%RBX

(225) 0x432f1d VADDSD	%XMM12,%XMM9,%XMM14

(225) 0x432f22 VMULSD	%XMM3,%XMM14,%XMM15

(225) 0x432f26 VMOVSD	%XMM15,(%R11,%R12,8)

(225) 0x432f2c MOV	0xe8(%RSP),%R11

(225) 0x432f34 MOV	0xf0(%RSP),%R12

(225) 0x432f3c LEA	(%R11,%RDX,1),%R10

(225) 0x432f40 LEA	(%R12,%R10,8),%R10

(225) 0x432f44 VMOVSD	(%R10),%XMM0

(225) 0x432f49 ADD	%R11,%RCX

(225) 0x432f4c VSUBSD	(%R12,%RCX,8),%XMM0,%XMM5

(225) 0x432f52 MOV	0xc0(%RSP),%RCX

(225) 0x432f5a ADD	%RBX,%RDX

(225) 0x432f5d VADDSD	%XMM15,%XMM5,%XMM7

(225) 0x432f62 MOV	0xa0(%RSP),%R11D

(225) 0x432f6a VMOVSD	%XMM7,(%RCX,%RDX,8)

(225) 0x432f6f MOV	0xfc(%RSP),%EDX

(225) 0x432f76 INC	%EDX

(225) 0x432f78 CMP	%R11D,%EDX

(225) 0x432f7b JAE	433113

(225) 0x432f81 MOV	0xd8(%RSP),%R11

(225) 0x432f89 LEA	0x1(%RAX),%R12D

(225) 0x432f8d MOVSXD	%R12D,%RDX

(225) 0x432f90 LEA	(%R11,%RDX,1),%R12

(225) 0x432f94 MOV	0xe0(%RSP),%R11

(225) 0x432f9c LEA	(%R14,%RDX,1),%RBX

(225) 0x432fa0 LEA	(%R13,%RBX,8),%RCX

(225) 0x432fa5 ADD	%RDX,%R11

(225) 0x432fa8 MOV	0xa8(%RSP),%RBX

(225) 0x432fb0 LEA	(%R15,%R11,8),%R11

(225) 0x432fb4 VMOVSD	(%R9),%XMM9

(225) 0x432fb9 VMOVSD	(%R11),%XMM6

(225) 0x432fbe ADD	%RDX,%RBX

(225) 0x432fc1 LEA	(%R13,%RBX,8),%RBX

(225) 0x432fc6 VMULSD	(%R8),%XMM9,%XMM10

(225) 0x432fcb VMULSD	(%RBX),%XMM6,%XMM8

(225) 0x432fcf LEA	(%R15,%R12,8),%R12

(225) 0x432fd3 VMOVSD	(%RDI),%XMM11

(225) 0x432fd7 VMOVSD	(%R12),%XMM1

(225) 0x432fdd VFMADD231SD	(%RSI),%XMM11,%XMM10

(225) 0x432fe2 VFMADD132SD	(%RCX),%XMM8,%XMM1

(225) 0x432fe7 MOV	0xb0(%RSP),%RSI

(225) 0x432fef MOV	0xb8(%RSP),%RDI

(225) 0x432ff7 ADD	%RDX,%RSI

(225) 0x432ffa MOV	0xe8(%RSP),%R8

(225) 0x433002 VADDSD	%XMM1,%XMM10,%XMM12

(225) 0x433006 LEA	(%R8,%RDX,1),%R9

(225) 0x43300a MOV	0xa0(%RSP),%R8D

(225) 0x433012 VMULSD	%XMM3,%XMM12,%XMM13

(225) 0x433016 VMOVSD	%XMM13,(%RDI,%RSI,8)

(225) 0x43301b MOV	0xf0(%RSP),%RSI

(225) 0x433023 MOV	0xc8(%RSP),%RDI

(225) 0x43302b LEA	(%RSI,%R9,8),%RSI

(225) 0x43302f VMOVSD	(%RSI),%XMM14

(225) 0x433033 ADD	%RDI,%RDX

(225) 0x433036 VSUBSD	(%R10),%XMM14,%XMM15

(225) 0x43303b MOV	0xc0(%RSP),%R10

(225) 0x433043 VADDSD	%XMM13,%XMM15,%XMM0

(225) 0x433048 VMOVSD	%XMM0,(%R10,%RDX,8)

(225) 0x43304e MOV	0xfc(%RSP),%EDX

(225) 0x433055 ADD	$0x2,%EDX

(225) 0x433058 CMP	%R8D,%EDX

(225) 0x43305b JAE	433113

(225) 0x433061 MOV	0xe0(%RSP),%RDI

(225) 0x433069 ADD	$0x2,%EAX

(225) 0x43306c CLTQ

(225) 0x43306e MOV	0xa8(%RSP),%R9

(225) 0x433076 ADD	%RAX,%RDI

(225) 0x433079 VMOVSD	(%R15,%RDI,8),%XMM5

(225) 0x43307f VMOVSD	(%RBX),%XMM8

(225) 0x433083 ADD	%RAX,%R9

(225) 0x433086 VMULSD	(%R13,%R9,8),%XMM5,%XMM7

(225) 0x43308d VMULSD	(%R11),%XMM8,%XMM1

(225) 0x433092 MOV	0xd8(%RSP),%R10

(225) 0x43309a VMOVSD	(%RCX),%XMM9

(225) 0x43309e ADD	%RAX,%R10

(225) 0x4330a1 VMOVSD	(%R15,%R10,8),%XMM6

(225) 0x4330a7 ADD	%RAX,%R14

(225) 0x4330aa VFMADD231SD	(%R13,%R14,8),%XMM6,%XMM7

(225) 0x4330b1 VFMADD231SD	(%R12),%XMM9,%XMM1

(225) 0x4330b7 MOV	0xb0(%RSP),%R13

(225) 0x4330bf MOV	0xb8(%RSP),%R15

(225) 0x4330c7 MOV	0xe8(%RSP),%R12

(225) 0x4330cf MOV	0xf0(%RSP),%RBX

(225) 0x4330d7 VADDSD	%XMM1,%XMM7,%XMM10

(225) 0x4330db ADD	%RAX,%R13

(225) 0x4330de ADD	%RAX,%R12

(225) 0x4330e1 VMULSD	%XMM3,%XMM10,%XMM11

(225) 0x4330e5 MOV	0xc8(%RSP),%RCX

(225) 0x4330ed MOV	0xc0(%RSP),%R11

(225) 0x4330f5 ADD	%RAX,%RCX

(225) 0x4330f8 VMOVSD	%XMM11,(%R15,%R13,8)

(225) 0x4330fe VMOVSD	(%RBX,%R12,8),%XMM12

(225) 0x433104 VSUBSD	(%RSI),%XMM12,%XMM13

(225) 0x433108 VADDSD	%XMM11,%XMM13,%XMM14

(225) 0x43310d VMOVSD	%XMM14,(%R11,%RCX,8)

(225) 0x433113 MOV	0xa0(%RSP),%ESI

(225) 0x43311a MOV	%ESI,0xfc(%RSP)

(225) 0x433121 INCQ	0xd0(%RSP)

(225) 0x433129 MOV	0xd0(%RSP),%RDX

(225) 0x433131 CMP	%EDX,0x78(%RSP)

(225) 0x433135 JLE	433160

(225) 0x433137 MOV	0x70(%RSP),%R13D

(225) 0x43313c MOV	0xfc(%RSP),%R8D

(225) 0x433144 MOV	0x74(%RSP),%R14D

(225) 0x433149 MOV	0x7c(%RSP),%R10D

(225) 0x43314e MOV	%R14D,0xa4(%RSP)

(225) 0x433156 SUB	%R8D,%R13D

(225) 0x433159 JMP	4329e0

0x43315e XCHG	%AX,%AX

0x433160 VZEROUPPER

0x433163 LEA	-0x28(%RBP),%RSP

0x433167 POP	%RBX

0x433168 POP	%R12

0x43316a POP	%R13

0x43316c POP	%R14

0x43316e POP	%R15

0x433170 POP	%RBP

0x433171 RET

0x433172 NOPW	(%RAX,%RAX,1)

(225) 0x433178 MOV	0xa4(%RSP),%EAX

(225) 0x43317f XOR	%R12D,%R12D

(225) 0x433182 JMP	432d65

0x433187 INC	%R13D

0x43318a XOR	%EDX,%EDX

0x43318c JMP	432954

0x433191 NOPW	%CS:(%RAX,%RAX,1)

0x43319c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 2.17 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.83 to 3.00 cycles (5.28x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.83 to 14.67 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	85
nb uops	95
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67
cycles	6.30	11.73	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4328d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ECX,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x7c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433187 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8b7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%RAX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xfc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x7c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x74(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3ce0c(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R10,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R11D,0xa4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R11D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 432954 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x84>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 2.17 cycles (7.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.83 to 14.67 cycles (1.08x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:97

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	85
nb uops	95
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.30	8.00	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67
cycles	6.30	11.73	6.67	6.67	10.00	6.20	6.30	10.00	10.00	10.00	6.20	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	15.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	15.83

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.83 cycles. At this rate:

2% of peak load performance is reached (4.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4328d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x100,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x2c(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %R15D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ECX,0x7c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x7c(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 433187 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8b7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%RAX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xfc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 433163 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x893>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x7c(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x74(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x3ce0c(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%YMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%R10,1),%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R11D,0xa4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R11D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 432954 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x84>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.07	0.89
▼Loop 225 - advec_mom.cpp:97-100 - exec–	0.01	0.01
○Loop 226 - advec_mom.cpp:98-100 - exec	3.06	0.88

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code