OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:71-75 [...]	Coverage (incl. loops): 2.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 71 - 75

--------------------------------------------------------------------------------

71: #pragma omp parallel for simd collapse(2)

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4322b0 PUSH	%RBP

0x4322b1 MOV	%RSP,%RBP

0x4322b4 PUSH	%R15

0x4322b6 PUSH	%R14

0x4322b8 PUSH	%R13

0x4322ba PUSH	%R12

0x4322bc PUSH	%RBX

0x4322bd AND	$-0x40,%RSP

0x4322c1 ADD	$-0x80,%RSP

0x4322c5 MOV	0x28(%RDI),%EAX

0x4322c8 MOV	0x2c(%RDI),%EDX

0x4322cb MOV	0x20(%RDI),%EBX

0x4322ce ADD	$0x4,%EDX

0x4322d1 LEA	-0x1(%RBX),%ESI

0x4322d4 LEA	-0x1(%RAX),%R12D

0x4322d8 MOV	%EDX,0x44(%RSP)

0x4322dc MOV	%ESI,0x40(%RSP)

0x4322e0 MOV	0x24(%RDI),%ECX

0x4322e3 CMP	%EDX,%R12D

0x4322e6 JGE	43289b

0x4322ec MOV	%EDX,%EBX

0x4322ee LEA	0x4(%RCX),%R15D

0x4322f2 SUB	%R12D,%EBX

0x4322f5 CMP	%R15D,%ESI

0x4322f8 JGE	43289b

0x4322fe MOV	%RDI,%R14

0x432301 MOV	%R15D,%EDI

0x432304 SUB	%ESI,%EDI

0x432306 MOV	%EDI,0x70(%RSP)

0x43230a CALL	404630 <omp_get_num_threads@plt>

0x43230f MOV	%EAX,%R13D

0x432312 CALL	404520 <omp_get_thread_num@plt>

0x432317 MOV	%EAX,%R8D

0x43231a MOV	0x70(%RSP),%EAX

0x43231e XOR	%EDX,%EDX

0x432320 IMUL	%EBX,%EAX

0x432323 DIV	%R13D

0x432326 MOV	%EAX,%EDI

0x432328 CMP	%EDX,%R8D

0x43232b JB	4328bc

0x432331 IMUL	%EDI,%R8D

0x432335 LEA	(%R8,%RDX,1),%R13D

0x432339 LEA	(%RDI,%R13,1),%R9D

0x43233d MOV	%R9D,0x3c(%RSP)

0x432342 CMP	%R9D,%R13D

0x432345 JAE	43289b

0x43234b MOV	%R13D,%EAX

0x43234e XOR	%EDX,%EDX

0x432350 DIVL	0x70(%RSP)

0x432354 MOV	0x40(%RSP),%R10D

0x432359 MOV	0x8(%R14),%R11

0x43235d MOV	0x18(%R14),%RSI

0x432361 MOV	0x10(%R14),%RBX

0x432365 MOV	%R11,0x30(%RSP)

0x43236a MOV	%RSI,0x28(%RSP)

0x43236f MOV	%RBX,0x18(%RSP)

0x432374 ADD	%EDX,%R10D

0x432377 MOV	%R15D,%EDX

0x43237a MOV	(%R14),%R15

0x43237d MOV	%R10D,0x74(%RSP)

0x432382 MOV	%R15,0x20(%RSP)

0x432387 ADD	%R12D,%EAX

0x43238a SUB	%R10D,%EDX

0x43238d MOVSXD	%EAX,%R12

(223) 0x432390 CMP	%EDX,%EDI

(223) 0x432392 CMOVBE	%EDI,%EDX

(223) 0x432395 LEA	(%R13,%RDX,1),%R15D

(223) 0x43239a CMP	%R15D,%R13D

(223) 0x43239d JAE	432870

(223) 0x4323a3 MOV	0x30(%RSP),%RCX

(223) 0x4323a8 MOV	0x28(%RSP),%R14

(223) 0x4323ad MOV	0x18(%RSP),%R11

(223) 0x4323b2 MOV	(%RCX),%R10

(223) 0x4323b5 MOV	(%R14),%RDI

(223) 0x4323b8 MOV	0x10(%R11),%RSI

(223) 0x4323bc MOV	(%R11),%R11

(223) 0x4323bf MOV	0x20(%RSP),%RAX

(223) 0x4323c4 IMUL	%R12,%R10

(223) 0x4323c8 IMUL	%R12,%RDI

(223) 0x4323cc IMUL	%R12,%R11

(223) 0x4323d0 MOV	0x10(%RCX),%R9

(223) 0x4323d4 MOV	0x10(%R14),%R8

(223) 0x4323d8 MOV	(%RAX),%R14

(223) 0x4323db LEA	-0x1(%RDX),%ECX

(223) 0x4323de MOV	%R9,0x50(%RSP)

(223) 0x4323e3 MOV	%R10,0x48(%RSP)

(223) 0x4323e8 MOV	%R8,0x68(%RSP)

(223) 0x4323ed MOV	%RDI,0x58(%RSP)

(223) 0x4323f2 IMUL	%R12,%R14

(223) 0x4323f6 MOV	%RSI,0x78(%RSP)

(223) 0x4323fb MOV	%R11,0x60(%RSP)

(223) 0x432400 MOV	0x10(%RAX),%RBX

(223) 0x432404 CMP	$0x6,%ECX

(223) 0x432407 JBE	4328b0

(223) 0x43240d MOVSXD	0x74(%RSP),%RAX

(223) 0x432412 LEA	(%R10,%RAX,1),%RCX

(223) 0x432416 LEA	(%RDI,%RAX,1),%RDI

(223) 0x43241a LEA	0x1(%R14,%RAX,1),%RSI

(223) 0x43241f ADD	%R11,%RAX

(223) 0x432422 MOV	0x78(%RSP),%R11

(223) 0x432427 LEA	(%R9,%RCX,8),%R9

(223) 0x43242b LEA	(%R11,%RAX,8),%RCX

(223) 0x43242f MOV	%EDX,%R11D

(223) 0x432432 SHR	$0x3,%R11D

(223) 0x432436 SAL	$0x6,%R11

(223) 0x43243a LEA	-0x40(%R11),%R10

(223) 0x43243e SHR	$0x6,%R10

(223) 0x432442 SAL	$0x3,%RSI

(223) 0x432446 INC	%R10

(223) 0x432449 LEA	(%R8,%RDI,8),%R8

(223) 0x43244d XOR	%EAX,%EAX

(223) 0x43244f LEA	(%RBX,%RSI,1),%RDI

(223) 0x432453 LEA	-0x8(%RBX,%RSI,1),%RSI

(223) 0x432458 AND	$0x7,%R10D

(223) 0x43245c JE	4325a8

(223) 0x432462 CMP	$0x1,%R10

(223) 0x432466 JE	432578

(223) 0x43246c CMP	$0x2,%R10

(223) 0x432470 JE	432551

(223) 0x432476 CMP	$0x3,%R10

(223) 0x43247a JE	43252a

(223) 0x432480 CMP	$0x4,%R10

(223) 0x432484 JE	432503

(223) 0x432486 CMP	$0x5,%R10

(223) 0x43248a JE	4324dc

(223) 0x43248c CMP	$0x6,%R10

(223) 0x432490 JE	4324b5

(223) 0x432492 VMOVUPD	(%R9),%ZMM0

(223) 0x432498 MOV	$0x40,%EAX

(223) 0x43249d VMOVUPD	%ZMM0,(%R8)

(223) 0x4324a3 VADDPD	(%RDI),%ZMM0,%ZMM1

(223) 0x4324a9 VSUBPD	(%RSI),%ZMM1,%ZMM2

(223) 0x4324af VMOVUPD	%ZMM2,(%RCX)

(223) 0x4324b5 VMOVUPD	(%R9,%RAX,1),%ZMM3

(223) 0x4324bc VMOVUPD	%ZMM3,(%R8,%RAX,1)

(223) 0x4324c3 VADDPD	(%RDI,%RAX,1),%ZMM3,%ZMM4

(223) 0x4324ca VSUBPD	(%RSI,%RAX,1),%ZMM4,%ZMM5

(223) 0x4324d1 VMOVUPD	%ZMM5,(%RCX,%RAX,1)

(223) 0x4324d8 ADD	$0x40,%RAX

(223) 0x4324dc VMOVUPD	(%R9,%RAX,1),%ZMM6

(223) 0x4324e3 VMOVUPD	%ZMM6,(%R8,%RAX,1)

(223) 0x4324ea VADDPD	(%RDI,%RAX,1),%ZMM6,%ZMM7

(223) 0x4324f1 VSUBPD	(%RSI,%RAX,1),%ZMM7,%ZMM8

(223) 0x4324f8 VMOVUPD	%ZMM8,(%RCX,%RAX,1)

(223) 0x4324ff ADD	$0x40,%RAX

(223) 0x432503 VMOVUPD	(%R9,%RAX,1),%ZMM9

(223) 0x43250a VMOVUPD	%ZMM9,(%R8,%RAX,1)

(223) 0x432511 VADDPD	(%RDI,%RAX,1),%ZMM9,%ZMM10

(223) 0x432518 VSUBPD	(%RSI,%RAX,1),%ZMM10,%ZMM11

(223) 0x43251f VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(223) 0x432526 ADD	$0x40,%RAX

(223) 0x43252a VMOVUPD	(%R9,%RAX,1),%ZMM12

(223) 0x432531 VMOVUPD	%ZMM12,(%R8,%RAX,1)

(223) 0x432538 VADDPD	(%RDI,%RAX,1),%ZMM12,%ZMM13

(223) 0x43253f VSUBPD	(%RSI,%RAX,1),%ZMM13,%ZMM14

(223) 0x432546 VMOVUPD	%ZMM14,(%RCX,%RAX,1)

(223) 0x43254d ADD	$0x40,%RAX

(223) 0x432551 VMOVUPD	(%R9,%RAX,1),%ZMM15

(223) 0x432558 VMOVUPD	%ZMM15,(%R8,%RAX,1)

(223) 0x43255f VADDPD	(%RDI,%RAX,1),%ZMM15,%ZMM0

(223) 0x432566 VSUBPD	(%RSI,%RAX,1),%ZMM0,%ZMM1

(223) 0x43256d VMOVUPD	%ZMM1,(%RCX,%RAX,1)

(223) 0x432574 ADD	$0x40,%RAX

(223) 0x432578 VMOVUPD	(%R9,%RAX,1),%ZMM2

(223) 0x43257f VMOVUPD	%ZMM2,(%R8,%RAX,1)

(223) 0x432586 VADDPD	(%RDI,%RAX,1),%ZMM2,%ZMM3

(223) 0x43258d VSUBPD	(%RSI,%RAX,1),%ZMM3,%ZMM4

(223) 0x432594 VMOVUPD	%ZMM4,(%RCX,%RAX,1)

(223) 0x43259b ADD	$0x40,%RAX

(223) 0x43259f CMP	%RAX,%R11

(223) 0x4325a2 JE	4326f2

  (224) 0x4325a8 VMOVUPD	(%R9,%RAX,1),%ZMM5

  (224) 0x4325af VMOVUPD	%ZMM5,(%R8,%RAX,1)

  (224) 0x4325b6 VADDPD	(%RDI,%RAX,1),%ZMM5,%ZMM6

  (224) 0x4325bd VSUBPD	(%RSI,%RAX,1),%ZMM6,%ZMM7

  (224) 0x4325c4 VMOVUPD	%ZMM7,(%RCX,%RAX,1)

  (224) 0x4325cb VMOVUPD	0x40(%R9,%RAX,1),%ZMM8

  (224) 0x4325d3 VMOVUPD	%ZMM8,0x40(%R8,%RAX,1)

  (224) 0x4325db VADDPD	0x40(%RDI,%RAX,1),%ZMM8,%ZMM9

  (224) 0x4325e3 VSUBPD	0x40(%RSI,%RAX,1),%ZMM9,%ZMM10

  (224) 0x4325eb VMOVUPD	%ZMM10,0x40(%RCX,%RAX,1)

  (224) 0x4325f3 VMOVUPD	0x80(%R9,%RAX,1),%ZMM11

  (224) 0x4325fb VMOVUPD	%ZMM11,0x80(%R8,%RAX,1)

  (224) 0x432603 VADDPD	0x80(%RDI,%RAX,1),%ZMM11,%ZMM12

  (224) 0x43260b VSUBPD	0x80(%RSI,%RAX,1),%ZMM12,%ZMM13

  (224) 0x432613 VMOVUPD	%ZMM13,0x80(%RCX,%RAX,1)

  (224) 0x43261b VMOVUPD	0xc0(%R9,%RAX,1),%ZMM14

  (224) 0x432623 VMOVUPD	%ZMM14,0xc0(%R8,%RAX,1)

  (224) 0x43262b VADDPD	0xc0(%RDI,%RAX,1),%ZMM14,%ZMM15

  (224) 0x432633 VSUBPD	0xc0(%RSI,%RAX,1),%ZMM15,%ZMM0

  (224) 0x43263b VMOVUPD	%ZMM0,0xc0(%RCX,%RAX,1)

  (224) 0x432643 VMOVUPD	0x100(%R9,%RAX,1),%ZMM1

  (224) 0x43264b VMOVUPD	%ZMM1,0x100(%R8,%RAX,1)

  (224) 0x432653 VADDPD	0x100(%RDI,%RAX,1),%ZMM1,%ZMM2

  (224) 0x43265b VSUBPD	0x100(%RSI,%RAX,1),%ZMM2,%ZMM3

  (224) 0x432663 VMOVUPD	%ZMM3,0x100(%RCX,%RAX,1)

  (224) 0x43266b VMOVUPD	0x140(%R9,%RAX,1),%ZMM4

  (224) 0x432673 VMOVUPD	%ZMM4,0x140(%R8,%RAX,1)

  (224) 0x43267b VADDPD	0x140(%RDI,%RAX,1),%ZMM4,%ZMM5

  (224) 0x432683 VSUBPD	0x140(%RSI,%RAX,1),%ZMM5,%ZMM6

  (224) 0x43268b VMOVUPD	%ZMM6,0x140(%RCX,%RAX,1)

  (224) 0x432693 VMOVUPD	0x180(%R9,%RAX,1),%ZMM7

  (224) 0x43269b VMOVUPD	%ZMM7,0x180(%R8,%RAX,1)

  (224) 0x4326a3 VADDPD	0x180(%RDI,%RAX,1),%ZMM7,%ZMM8

  (224) 0x4326ab VSUBPD	0x180(%RSI,%RAX,1),%ZMM8,%ZMM9

  (224) 0x4326b3 VMOVUPD	%ZMM9,0x180(%RCX,%RAX,1)

  (224) 0x4326bb VMOVUPD	0x1c0(%R9,%RAX,1),%ZMM10

  (224) 0x4326c3 VMOVUPD	%ZMM10,0x1c0(%R8,%RAX,1)

  (224) 0x4326cb VADDPD	0x1c0(%RDI,%RAX,1),%ZMM10,%ZMM11

  (224) 0x4326d3 VSUBPD	0x1c0(%RSI,%RAX,1),%ZMM11,%ZMM12

  (224) 0x4326db VMOVUPD	%ZMM12,0x1c0(%RCX,%RAX,1)

  (224) 0x4326e3 ADD	$0x200,%RAX

  (224) 0x4326e9 CMP	%RAX,%R11

  (224) 0x4326ec JNE	4325a8

(223) 0x4326f2 MOV	0x74(%RSP),%ESI

(223) 0x4326f6 MOV	%EDX,%R10D

(223) 0x4326f9 AND	$-0x8,%R10D

(223) 0x4326fd ADD	%R10D,%ESI

(223) 0x432700 ADD	%R10D,%R13D

(223) 0x432703 TEST	$0x7,%DL

(223) 0x432706 JE	43286d

(223) 0x43270c SUB	%R10D,%EDX

(223) 0x43270f LEA	-0x1(%RDX),%R9D

(223) 0x432713 CMP	$0x2,%R9D

(223) 0x432717 JBE	43278d

(223) 0x432719 MOVSXD	0x74(%RSP),%RCX

(223) 0x43271e MOV	0x48(%RSP),%RDI

(223) 0x432723 LEA	(%R14,%RCX,1),%R8

(223) 0x432727 LEA	0x1(%R10,%R8,1),%R11

(223) 0x43272c ADD	%RCX,%RDI

(223) 0x43272f MOV	0x50(%RSP),%RAX

(223) 0x432734 MOV	0x58(%RSP),%R8

(223) 0x432739 ADD	%R10,%RDI

(223) 0x43273c VMOVUPD	(%RAX,%RDI,8),%YMM13

(223) 0x432741 ADD	%RCX,%R8

(223) 0x432744 MOV	0x68(%RSP),%R9

(223) 0x432749 ADD	%R10,%R8

(223) 0x43274c VMOVUPD	%YMM13,(%R9,%R8,8)

(223) 0x432752 VMOVUPD	(%RBX,%R11,8),%YMM14

(223) 0x432758 VSUBPD	-0x8(%RBX,%R11,8),%YMM14,%YMM15

(223) 0x43275f MOV	0x60(%RSP),%R11

(223) 0x432764 VADDPD	%YMM13,%YMM15,%YMM0

(223) 0x432769 ADD	%R11,%RCX

(223) 0x43276c ADD	%R10,%RCX

(223) 0x43276f MOV	0x78(%RSP),%R10

(223) 0x432774 VMOVUPD	%YMM0,(%R10,%RCX,8)

(223) 0x43277a MOV	%EDX,%ECX

(223) 0x43277c AND	$-0x4,%ECX

(223) 0x43277f ADD	%ECX,%ESI

(223) 0x432781 ADD	%ECX,%R13D

(223) 0x432784 AND	$0x3,%EDX

(223) 0x432787 JE	43286d

(223) 0x43278d MOV	0x48(%RSP),%R9

(223) 0x432792 MOVSXD	%ESI,%RDX

(223) 0x432795 MOV	0x50(%RSP),%R8

(223) 0x43279a LEA	(%R9,%RDX,1),%RDI

(223) 0x43279e MOV	0x58(%RSP),%R10

(223) 0x4327a3 VMOVSD	(%R8,%RDI,8),%XMM1

(223) 0x4327a9 MOV	0x68(%RSP),%R11

(223) 0x4327ae LEA	(%R10,%RDX,1),%RAX

(223) 0x4327b2 VMOVSD	%XMM1,(%R11,%RAX,8)

(223) 0x4327b8 LEA	0x1(%RSI),%EAX

(223) 0x4327bb CLTQ

(223) 0x4327bd LEA	(%R14,%RAX,1),%RCX

(223) 0x4327c1 MOV	0x60(%RSP),%R11

(223) 0x4327c6 LEA	(%RBX,%RCX,8),%RCX

(223) 0x4327ca VMOVSD	(%RCX),%XMM2

(223) 0x4327ce LEA	(%R11,%RDX,1),%RDI

(223) 0x4327d2 ADD	%R14,%RDX

(223) 0x4327d5 VSUBSD	(%RBX,%RDX,8),%XMM2,%XMM3

(223) 0x4327da MOV	0x78(%RSP),%RDX

(223) 0x4327df VADDSD	%XMM1,%XMM3,%XMM4

(223) 0x4327e3 VMOVSD	%XMM4,(%RDX,%RDI,8)

(223) 0x4327e8 LEA	0x1(%R13),%EDI

(223) 0x4327ec CMP	%R15D,%EDI

(223) 0x4327ef JAE	43286d

(223) 0x4327f1 LEA	(%RAX,%R9,1),%RDX

(223) 0x4327f5 VMOVSD	(%R8,%RDX,8),%XMM5

(223) 0x4327fb MOV	0x68(%RSP),%RDI

(223) 0x432800 LEA	(%RAX,%R10,1),%RDX

(223) 0x432804 VMOVSD	%XMM5,(%RDI,%RDX,8)

(223) 0x432809 LEA	0x2(%RSI),%EDX

(223) 0x43280c MOVSXD	%EDX,%RDX

(223) 0x43280f LEA	(%R14,%RDX,1),%RDI

(223) 0x432813 LEA	(%RBX,%RDI,8),%RDI

(223) 0x432817 VADDSD	(%RDI),%XMM5,%XMM6

(223) 0x43281b ADD	%R11,%RAX

(223) 0x43281e ADD	$0x2,%R13D

(223) 0x432822 VSUBSD	(%RCX),%XMM6,%XMM7

(223) 0x432826 MOV	0x78(%RSP),%RCX

(223) 0x43282b VMOVSD	%XMM7,(%RCX,%RAX,8)

(223) 0x432830 CMP	%R15D,%R13D

(223) 0x432833 JAE	43286d

(223) 0x432835 ADD	%RDX,%R9

(223) 0x432838 VMOVSD	(%R8,%R9,8),%XMM8

(223) 0x43283e MOV	0x68(%RSP),%R13

(223) 0x432843 ADD	$0x3,%ESI

(223) 0x432846 ADD	%RDX,%R10

(223) 0x432849 MOVSXD	%ESI,%RSI

(223) 0x43284c VMOVSD	%XMM8,(%R13,%R10,8)

(223) 0x432853 ADD	%R14,%RSI

(223) 0x432856 VADDSD	(%RBX,%RSI,8),%XMM8,%XMM9

(223) 0x43285b MOV	0x78(%RSP),%RBX

(223) 0x432860 ADD	%RDX,%R11

(223) 0x432863 VSUBSD	(%RDI),%XMM9,%XMM10

(223) 0x432867 VMOVSD	%XMM10,(%RBX,%R11,8)

(223) 0x43286d MOV	%R15D,%R13D

(223) 0x432870 INC	%R12

(223) 0x432873 CMP	%R12D,0x44(%RSP)

(223) 0x432878 JLE	432898

(223) 0x43287a MOV	0x3c(%RSP),%EDI

(223) 0x43287e MOV	0x40(%RSP),%R15D

(223) 0x432883 MOV	0x70(%RSP),%EDX

(223) 0x432887 MOV	%R15D,0x74(%RSP)

(223) 0x43288c SUB	%R13D,%EDI

(223) 0x43288f JMP	432390

0x432894 NOPL	(%RAX)

0x432898 VZEROUPPER

0x43289b LEA	-0x28(%RBP),%RSP

0x43289f POP	%RBX

0x4328a0 POP	%R12

0x4328a2 POP	%R13

0x4328a4 POP	%R14

0x4328a6 POP	%R15

0x4328a8 POP	%RBP

0x4328a9 RET

0x4328aa NOPW	(%RAX,%RAX,1)

(223) 0x4328b0 MOV	0x74(%RSP),%ESI

(223) 0x4328b4 XOR	%R10D,%R10D

(223) 0x4328b7 JMP	43270c

0x4328bc INC	%EDI

0x4328be XOR	%EDX,%EDX

0x4328c0 JMP	432331

0x4328c5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.83 to 3.00 cycles (4.94x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.83 to 13.67 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	79
nb uops	89
loop length	272
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.83

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.51 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4322b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4328bc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x60c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x70(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x40(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10D,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 432331 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.83 to 13.67 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	79
nb uops	89
loop length	272
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.70	8.00	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00
cycles	5.70	11.73	6.00	6.00	8.50	5.87	5.70	8.50	8.50	8.50	5.73	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	14.83
Dispatch	11.73
DIV/SQRT	12.00
Overall L1	14.83

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

2% of peak load performance is reached (4.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.51 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4322b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RBX),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RAX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,0x44(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ESI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %EDX,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB %R12D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ESI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x70(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 4328bc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x60c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,1),%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RDI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R9D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 43289b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x5eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVL 0x70(%RSP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	6	scal (6.3%)
MOV 0x40(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10D,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 432331 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.59	0.75
▼Loop 223 - advec_mom.cpp:73-75 - exec–	0.01	0.01
○Loop 224 - advec_mom.cpp:74-75 - exec	2.59	0.74

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code