OV - exec - Loop 643

	Loop Id: 643	Module: exec	Source: par_multi_interp.c:1774-1876	Coverage: 0.19%

0x473f40 MOV	0xf8(%RSP),%R15

0x473f48 MOV	0xd8(%RSP),%RAX

0x473f50 MOV	0xb0(%RSP),%RCX

0x473f58 MOV	(%R15),%R12

0x473f5b LEA	(,%R12,8),%RBX

0x473f63 LEA	0x8(%RAX,%RBX,1),%RDI

0x473f68 MOV	(%RCX,%RBX,1),%RDX

0x473f6c ADD	%RBX,%RAX

0x473f6f VMOVQ	%RBX,%XMM13

0x473f74 MOV	(%RDI),%RSI

0x473f77 VMOVQ	%RAX,%XMM15

0x473f7c MOV	(%RAX),%RAX

0x473f7f LEA	0x8(%RBX),%R15

0x473f83 ADD	%RDX,%RSI

0x473f86 SUB	%RAX,%RSI

0x473f89 CMP	%RSI,%RDX

0x473f8c JGE	47416d

0x473f92 MOV	%RAX,%RBX

0x473f95 VMOVQ	%XMM7,%RCX

0x473f9a SUB	%RDX,%RBX

0x473f9d SUB	%RAX,%RDX

0x473fa0 ADD	%RBX,%RSI

0x473fa3 MOV	0x78(%RSP),%RBX

0x473fa8 MOV	(%RBX,%RCX,1),%RBX

0x473fac LEA	(%RBX,%RDX,8),%RBX

0x473fb0 MOV	%RSI,%RDX

0x473fb3 SUB	%RAX,%RDX

0x473fb6 AND	$0x7,%EDX

0x473fb9 JE	47409c

0x473fbf CMP	$0x1,%RDX

0x473fc3 JE	47407b

0x473fc9 CMP	$0x2,%RDX

0x473fcd JE	474063

0x473fd3 CMP	$0x3,%RDX

0x473fd7 JE	47404b

0x473fd9 CMP	$0x4,%RDX

0x473fdd JE	474033

0x473fdf CMP	$0x5,%RDX

0x473fe3 JE	47401b

0x473fe5 CMP	$0x6,%RDX

0x473fe9 JE	474003

0x473feb MOV	(%RBX,%RAX,8),%RCX

0x473fef MOV	%RAX,(%R14,%RCX,8)

0x473ff3 MOVQ	$0,(%R8,%RAX,8)

0x473ffb INC	%RAX

0x473ffe MOV	%RCX,-0x8(%R9,%RAX,8)

0x474003 MOV	(%RBX,%RAX,8),%RDX

0x474007 MOV	%RAX,(%R14,%RDX,8)

0x47400b MOVQ	$0,(%R8,%RAX,8)

0x474013 INC	%RAX

0x474016 MOV	%RDX,-0x8(%R9,%RAX,8)

0x47401b MOV	(%RBX,%RAX,8),%RCX

0x47401f MOV	%RAX,(%R14,%RCX,8)

0x474023 MOVQ	$0,(%R8,%RAX,8)

0x47402b INC	%RAX

0x47402e MOV	%RCX,-0x8(%R9,%RAX,8)

0x474033 MOV	(%RBX,%RAX,8),%RDX

0x474037 MOV	%RAX,(%R14,%RDX,8)

0x47403b MOVQ	$0,(%R8,%RAX,8)

0x474043 INC	%RAX

0x474046 MOV	%RDX,-0x8(%R9,%RAX,8)

0x47404b MOV	(%RBX,%RAX,8),%RCX

0x47404f MOV	%RAX,(%R14,%RCX,8)

0x474053 MOVQ	$0,(%R8,%RAX,8)

0x47405b INC	%RAX

0x47405e MOV	%RCX,-0x8(%R9,%RAX,8)

0x474063 MOV	(%RBX,%RAX,8),%RDX

0x474067 MOV	%RAX,(%R14,%RDX,8)

0x47406b MOVQ	$0,(%R8,%RAX,8)

0x474073 INC	%RAX

0x474076 MOV	%RDX,-0x8(%R9,%RAX,8)

0x47407b MOV	(%RBX,%RAX,8),%RCX

0x47407f MOV	%RAX,(%R14,%RCX,8)

0x474083 MOVQ	$0,(%R8,%RAX,8)

0x47408b INC	%RAX

0x47408e MOV	%RCX,-0x8(%R9,%RAX,8)

0x474093 CMP	%RSI,%RAX

0x474096 JE	47416d

  (654) 0x47409c MOV	(%RBX,%RAX,8),%RCX

  (654) 0x4740a0 LEA	0x1(%RAX),%RDX

  (654) 0x4740a4 MOV	%RAX,(%R14,%RCX,8)

  (654) 0x4740a8 MOVQ	$0,(%R8,%RAX,8)

  (654) 0x4740b0 MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x4740b5 MOV	(%RBX,%RDX,8),%RCX

  (654) 0x4740b9 MOV	%RDX,(%R14,%RCX,8)

  (654) 0x4740bd MOVQ	$0,(%R8,%RDX,8)

  (654) 0x4740c5 LEA	0x2(%RAX),%RDX

  (654) 0x4740c9 MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x4740ce MOV	(%RBX,%RDX,8),%RCX

  (654) 0x4740d2 MOV	%RDX,(%R14,%RCX,8)

  (654) 0x4740d6 MOVQ	$0,(%R8,%RDX,8)

  (654) 0x4740de LEA	0x3(%RAX),%RDX

  (654) 0x4740e2 MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x4740e7 MOV	(%RBX,%RDX,8),%RCX

  (654) 0x4740eb MOV	%RDX,(%R14,%RCX,8)

  (654) 0x4740ef MOVQ	$0,(%R8,%RDX,8)

  (654) 0x4740f7 LEA	0x4(%RAX),%RDX

  (654) 0x4740fb MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x474100 MOV	(%RBX,%RDX,8),%RCX

  (654) 0x474104 MOV	%RDX,(%R14,%RCX,8)

  (654) 0x474108 MOVQ	$0,(%R8,%RDX,8)

  (654) 0x474110 LEA	0x5(%RAX),%RDX

  (654) 0x474114 MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x474119 MOV	(%RBX,%RDX,8),%RCX

  (654) 0x47411d MOV	%RDX,(%R14,%RCX,8)

  (654) 0x474121 MOVQ	$0,(%R8,%RDX,8)

  (654) 0x474129 LEA	0x6(%RAX),%RDX

  (654) 0x47412d MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x474132 MOV	(%RBX,%RDX,8),%RCX

  (654) 0x474136 MOV	%RDX,(%R14,%RCX,8)

  (654) 0x47413a MOVQ	$0,(%R8,%RDX,8)

  (654) 0x474142 LEA	0x7(%RAX),%RDX

  (654) 0x474146 ADD	$0x8,%RAX

  (654) 0x47414a MOV	%RCX,-0x8(%R9,%RDX,8)

  (654) 0x47414f MOV	(%RBX,%RDX,8),%RCX

  (654) 0x474153 MOV	%RDX,(%R14,%RCX,8)

  (654) 0x474157 MOVQ	$0,(%R8,%RDX,8)

  (654) 0x47415f MOV	%RCX,-0x8(%R9,%RAX,8)

  (654) 0x474164 CMP	%RSI,%RAX

  (654) 0x474167 JNE	47409c

0x47416d MOV	0xe0(%RSP),%RCX

0x474175 MOV	0xb8(%RSP),%RAX

0x47417d VMOVQ	%XMM13,%RSI

0x474182 LEA	(%RCX,%R15,1),%RBX

0x474186 MOV	(%RAX,%RSI,1),%RDX

0x47418a ADD	%RSI,%RCX

0x47418d MOV	(%RBX),%RSI

0x474190 MOV	(%RCX),%RAX

0x474193 VMOVQ	%RBX,%XMM16

0x474199 VMOVQ	%RCX,%XMM17

0x47419f ADD	%RDX,%RSI

0x4741a2 SUB	%RAX,%RSI

0x4741a5 CMP	%RSI,%RDX

0x4741a8 JGE	47439b

0x4741ae MOV	0x80(%RSP),%RBX

0x4741b6 MOV	%RAX,%RCX

0x4741b9 SUB	%RDX,%RCX

0x4741bc SUB	%RAX,%RDX

0x4741bf ADD	%RCX,%RSI

0x4741c2 VMOVQ	%XMM7,%RCX

0x4741c7 MOV	(%RBX,%RCX,1),%RBX

0x4741cb LEA	(%RBX,%RDX,8),%RBX

0x4741cf MOV	%RSI,%RDX

0x4741d2 SUB	%RAX,%RDX

0x4741d5 AND	$0x7,%EDX

0x4741d8 JE	4742c2

0x4741de CMP	$0x1,%RDX

0x4741e2 JE	4742a0

0x4741e8 CMP	$0x2,%RDX

0x4741ec JE	474287

0x4741f2 CMP	$0x3,%RDX

0x4741f6 JE	47426e

0x4741f8 CMP	$0x4,%RDX

0x4741fc JE	474255

0x4741fe CMP	$0x5,%RDX

0x474202 JE	47423c

0x474204 CMP	$0x6,%RDX

0x474208 JE	474223

0x47420a MOV	(%RBX,%RAX,8),%RCX

0x47420e MOV	%RAX,(%R13,%RCX,8)

0x474213 MOVQ	$0,(%R10,%RAX,8)

0x47421b INC	%RAX

0x47421e MOV	%RCX,-0x8(%R11,%RAX,8)

0x474223 MOV	(%RBX,%RAX,8),%RDX

0x474227 MOV	%RAX,(%R13,%RDX,8)

0x47422c MOVQ	$0,(%R10,%RAX,8)

0x474234 INC	%RAX

0x474237 MOV	%RDX,-0x8(%R11,%RAX,8)

0x47423c MOV	(%RBX,%RAX,8),%RCX

0x474240 MOV	%RAX,(%R13,%RCX,8)

0x474245 MOVQ	$0,(%R10,%RAX,8)

0x47424d INC	%RAX

0x474250 MOV	%RCX,-0x8(%R11,%RAX,8)

0x474255 MOV	(%RBX,%RAX,8),%RDX

0x474259 MOV	%RAX,(%R13,%RDX,8)

0x47425e MOVQ	$0,(%R10,%RAX,8)

0x474266 INC	%RAX

0x474269 MOV	%RDX,-0x8(%R11,%RAX,8)

0x47426e MOV	(%RBX,%RAX,8),%RCX

0x474272 MOV	%RAX,(%R13,%RCX,8)

0x474277 MOVQ	$0,(%R10,%RAX,8)

0x47427f INC	%RAX

0x474282 MOV	%RCX,-0x8(%R11,%RAX,8)

0x474287 MOV	(%RBX,%RAX,8),%RDX

0x47428b MOV	%RAX,(%R13,%RDX,8)

0x474290 MOVQ	$0,(%R10,%RAX,8)

0x474298 INC	%RAX

0x47429b MOV	%RDX,-0x8(%R11,%RAX,8)

0x4742a0 MOV	(%RBX,%RAX,8),%RCX

0x4742a4 MOV	%RAX,(%R13,%RCX,8)

0x4742a9 MOVQ	$0,(%R10,%RAX,8)

0x4742b1 INC	%RAX

0x4742b4 MOV	%RCX,-0x8(%R11,%RAX,8)

0x4742b9 CMP	%RAX,%RSI

0x4742bc JE	47439b

  (653) 0x4742c2 MOV	(%RBX,%RAX,8),%RCX

  (653) 0x4742c6 LEA	0x1(%RAX),%RDX

  (653) 0x4742ca MOV	%RAX,(%R13,%RCX,8)

  (653) 0x4742cf MOVQ	$0,(%R10,%RAX,8)

  (653) 0x4742d7 MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x4742dc MOV	(%RBX,%RDX,8),%RCX

  (653) 0x4742e0 MOV	%RDX,(%R13,%RCX,8)

  (653) 0x4742e5 MOVQ	$0,(%R10,%RDX,8)

  (653) 0x4742ed LEA	0x2(%RAX),%RDX

  (653) 0x4742f1 MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x4742f6 MOV	(%RBX,%RDX,8),%RCX

  (653) 0x4742fa MOV	%RDX,(%R13,%RCX,8)

  (653) 0x4742ff MOVQ	$0,(%R10,%RDX,8)

  (653) 0x474307 LEA	0x3(%RAX),%RDX

  (653) 0x47430b MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x474310 MOV	(%RBX,%RDX,8),%RCX

  (653) 0x474314 MOV	%RDX,(%R13,%RCX,8)

  (653) 0x474319 MOVQ	$0,(%R10,%RDX,8)

  (653) 0x474321 LEA	0x4(%RAX),%RDX

  (653) 0x474325 MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x47432a MOV	(%RBX,%RDX,8),%RCX

  (653) 0x47432e MOV	%RDX,(%R13,%RCX,8)

  (653) 0x474333 MOVQ	$0,(%R10,%RDX,8)

  (653) 0x47433b LEA	0x5(%RAX),%RDX

  (653) 0x47433f MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x474344 MOV	(%RBX,%RDX,8),%RCX

  (653) 0x474348 MOV	%RDX,(%R13,%RCX,8)

  (653) 0x47434d MOVQ	$0,(%R10,%RDX,8)

  (653) 0x474355 LEA	0x6(%RAX),%RDX

  (653) 0x474359 MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x47435e MOV	(%RBX,%RDX,8),%RCX

  (653) 0x474362 MOV	%RDX,(%R13,%RCX,8)

  (653) 0x474367 MOVQ	$0,(%R10,%RDX,8)

  (653) 0x47436f LEA	0x7(%RAX),%RDX

  (653) 0x474373 ADD	$0x8,%RAX

  (653) 0x474377 MOV	%RCX,-0x8(%R11,%RDX,8)

  (653) 0x47437c MOV	(%RBX,%RDX,8),%RCX

  (653) 0x474380 MOV	%RDX,(%R13,%RCX,8)

  (653) 0x474385 MOVQ	$0,(%R10,%RDX,8)

  (653) 0x47438d MOV	%RCX,-0x8(%R11,%RAX,8)

  (653) 0x474392 CMP	%RAX,%RSI

  (653) 0x474395 JNE	4742c2

0x47439b MOV	0xa0(%RSP),%RSI

0x4743a3 VMOVQ	%XMM13,%RAX

0x4743a8 VMOVQ	%R8,%XMM4

0x4743ad VMOVQ	%RDI,%XMM5

0x4743b2 LEA	(%RSI,%R15,1),%RBX

0x4743b6 MOV	(%RSI,%RAX,1),%RAX

0x4743ba MOV	(%RBX),%RSI

0x4743bd VMOVQ	%RBX,%XMM1

0x4743c2 VMOVQ	%XMM3,%RBX

0x4743c7 CMP	%RSI,%RAX

0x4743ca JGE	47443d

0x4743cc NOPW	%CS:(%RAX,%RAX,1)

0x4743d7 NOPW	%CS:(%RAX,%RAX,1)

0x4743e2 NOPW	%CS:(%RAX,%RAX,1)

0x4743ed NOPW	%CS:(%RAX,%RAX,1)

0x4743f8 NOPL	(%RAX,%RAX,1)

  (652) 0x474400 MOV	(%RBX,%RAX,8),%RDX

  (652) 0x474404 MOV	0x120(%RSP),%RDI

  (652) 0x47440c MOV	0x138(%RSP),%R8

  (652) 0x474414 LEA	(,%RDX,8),%RCX

  (652) 0x47441c CMP	(%RDI,%RDX,8),%R8

  (652) 0x474420 JE	474ae0

  (652) 0x474426 INC	%RAX

  (652) 0x474429 CMP	%RSI,%RAX

  (652) 0x47442c JL	474400

0x47442e VMOVQ	%XMM4,%R8

0x474433 VMOVQ	%RBX,%XMM3

0x474438 VMOVQ	%XMM5,%RDI

0x47443d MOV	0xa8(%RSP),%RBX

0x474445 VMOVQ	%XMM13,%RAX

0x47444a LEA	(%RBX,%R15,1),%RCX

0x47444e MOV	(%RBX,%RAX,1),%RAX

0x474452 MOV	(%RCX),%RSI

0x474455 VMOVQ	%RCX,%XMM2

0x47445a CMP	%RSI,%RAX

0x47445d JGE	4744b8

0x47445f MOV	0x68(%RSP),%RBX

0x474464 VMOVQ	%R8,%XMM6

0x474469 VMOVQ	%RDI,%XMM10

0x47446e NOPW	%CS:(%RAX,%RAX,1)

0x474479 NOPL	(%RAX)

  (651) 0x474480 MOV	(%RBX,%RAX,8),%RDX

  (651) 0x474484 MOV	0x128(%RSP),%RDI

  (651) 0x47448c MOV	0x138(%RSP),%R8

  (651) 0x474494 LEA	(,%RDX,8),%RCX

  (651) 0x47449c CMP	(%RDI,%RDX,8),%R8

  (651) 0x4744a0 JE	474ab0

  (651) 0x4744a6 INC	%RAX

  (651) 0x4744a9 CMP	%RSI,%RAX

  (651) 0x4744ac JL	474480

0x4744ae VMOVQ	%XMM6,%R8

0x4744b3 VMOVQ	%XMM10,%RDI

0x4744b8 MOV	0x90(%RSP),%RBX

0x4744c0 VMOVQ	%XMM13,%RAX

0x4744c5 VMOVQ	(%RBX,%RAX,1),%XMM18

0x4744cc MOV	(%RBX,%R15,1),%RDX

0x4744d0 VMOVQ	%XMM18,%RAX

0x4744d6 INC	%RAX

0x4744d9 CMP	%RDX,%RAX

0x4744dc JGE	4751a6

0x4744e2 MOV	0x50(%RSP),%RBX

0x4744e7 MOV	0xd0(%RSP),%RCX

0x4744ef VMOVQ	%R15,%XMM4

0x4744f4 VXORPD	%XMM0,%XMM0,%XMM0

0x4744f8 MOV	%R12,%R15

0x4744fb VMOVAPD	%XMM0,%XMM1

0x4744ff VMOVQ	%R11,%XMM5

0x474504 MOV	%R9,%R12

0x474507 SAL	$0x3,%RAX

0x47450b VMOVQ	%RDI,%XMM14

0x474510 LEA	(%RBX,%RAX,1),%RSI

0x474514 ADD	%RCX,%RAX

0x474517 LEA	(%RBX,%RDX,8),%RBX

0x47451b MOV	0xf0(%RSP),%RCX

0x474523 JMP	474554

  (648) 0x474530 MOV	0x108(%RSP),%R11

  (648) 0x474538 VMOVQ	%XMM13,%RDX

  (648) 0x47453d MOV	(%R11,%R9,1),%R9

  (648) 0x474541 CMP	%R9,(%R11,%RDX,1)

  (648) 0x474545 JE	474583

  (648) 0x474547 ADD	$0x8,%RSI

  (648) 0x47454b ADD	$0x8,%RAX

  (648) 0x47454f CMP	%RSI,%RBX

  (648) 0x474552 JE	474594

  (648) 0x474554 MOV	(%RSI),%R11

  (648) 0x474557 LEA	(,%R11,8),%R9

  (648) 0x47455f CMP	(%RCX,%R11,8),%R15

  (648) 0x474563 JE	474b10

  (648) 0x474569 MOV	0x110(%RSP),%RDI

  (648) 0x474571 CMPQ	$-0x3,(%RDI,%R9,1)

  (648) 0x474576 JE	474547

  (648) 0x474578 CMPQ	$0x1,0x130(%RSP)

  (648) 0x474581 JNE	474530

  (648) 0x474583 ADD	$0x8,%RSI

  (648) 0x474587 VADDSD	(%RAX),%XMM0,%XMM0

  (648) 0x47458b ADD	$0x8,%RAX

  (648) 0x47458f CMP	%RSI,%RBX

  (648) 0x474592 JNE	474554

0x474594 MOV	%R12,%R9

0x474597 VMOVQ	%XMM5,%R11

0x47459c MOV	%R15,%R12

0x47459f VMOVQ	%XMM14,%RDI

0x4745a4 VMOVQ	%XMM4,%R15

0x4745a9 MOV	0x98(%RSP),%RCX

0x4745b1 VMOVQ	%XMM13,%RSI

0x4745b6 MOV	(%RCX,%RSI,1),%RDX

0x4745ba MOV	(%RCX,%R15,1),%R15

0x4745be CMP	%R15,%RDX

0x4745c1 JGE	4746a8

0x4745c7 MOV	0x60(%RSP),%RBX

0x4745cc MOV	0x58(%RSP),%RCX

0x4745d1 VMOVQ	%R9,%XMM6

0x4745d6 MOV	%R12,%R9

0x4745d9 VMOVQ	%R8,%XMM5

0x4745de MOV	%R14,%R12

0x4745e1 VMOVQ	%RDI,%XMM14

0x4745e6 MOV	0x48(%RSP),%RSI

0x4745eb MOV	%R13,%RDI

0x4745ee MOV	%R9,%R14

0x4745f1 SAL	$0x3,%RDX

0x4745f5 LEA	(%RBX,%R15,8),%R15

0x4745f9 LEA	(%RBX,%RDX,1),%RAX

0x4745fd MOV	0x70(%RSP),%RBX

0x474602 ADD	%RCX,%RDX

0x474605 MOV	%R15,%R8

0x474608 JMP	47463c

  (646) 0x474610 MOV	0x108(%RSP),%R9

  (646) 0x474618 MOV	0xe8(%RSP),%RCX

  (646) 0x474620 VMOVQ	%XMM13,%R13

  (646) 0x474625 MOV	(%R9,%R13,1),%R9

  (646) 0x474629 CMP	%R9,(%RCX,%R15,1)

  (646) 0x47462d JE	474682

  (646) 0x47462f ADD	$0x8,%RAX

  (646) 0x474633 ADD	$0x8,%RDX

  (646) 0x474637 CMP	%R8,%RAX

  (646) 0x47463a JE	474693

  (646) 0x47463c MOV	(%RAX),%RCX

  (646) 0x47463f TEST	%RSI,%RSI

  (646) 0x474642 JE	474651

  (646) 0x474644 MOV	0x100(%RSP),%R13

  (646) 0x47464c MOV	(%R13,%RCX,8),%RCX

  (646) 0x474651 LEA	(,%RCX,8),%R15

  (646) 0x474659 TEST	%RCX,%RCX

  (646) 0x47465c JS	474670

  (646) 0x47465e MOV	0x118(%RSP),%R9

  (646) 0x474666 CMP	(%R9,%R15,1),%R14

  (646) 0x47466a JE	474e70

  (646) 0x474670 CMPQ	$-0x3,(%RBX,%R15,1)

  (646) 0x474675 JE	47462f

  (646) 0x474677 CMPQ	$0x1,0x130(%RSP)

  (646) 0x474680 JNE	474610

  (646) 0x474682 ADD	$0x8,%RAX

  (646) 0x474686 VADDSD	(%RDX),%XMM0,%XMM0

  (646) 0x47468a ADD	$0x8,%RDX

  (646) 0x47468e CMP	%R8,%RAX

  (646) 0x474691 JNE	47463c

0x474693 MOV	%RDI,%R13

0x474696 MOV	%R12,%R14

0x474699 VMOVQ	%XMM6,%R9

0x47469e VMOVQ	%XMM5,%R8

0x4746a3 VMOVQ	%XMM14,%RDI

0x4746a8 MOV	0xd0(%RSP),%RCX

0x4746b0 VMOVQ	%XMM18,%R15

0x4746b6 VMULSD	(%RCX,%R15,8),%XMM1,%XMM13

0x4746bc VCOMISD	%XMM8,%XMM13

0x4746c1 JE	4746cd

0x4746c3 VXORPD	%XMM9,%XMM0,%XMM2

0x4746c8 VDIVSD	%XMM13,%XMM2,%XMM11

0x4746cd VMOVQ	%XMM15,%RAX

0x4746d2 MOV	(%RDI),%RDI

0x4746d5 MOV	(%RAX),%RSI

0x4746d8 CMP	%RDI,%RSI

0x4746db JGE	4748a9

0x4746e1 MOV	%RDI,%RBX

0x4746e4 SUB	%RSI,%RBX

0x4746e7 LEA	-0x1(%RBX),%RDX

0x4746eb CMP	$0x2,%RDX

0x4746ef JBE	474869

0x4746f5 MOV	%RBX,%RCX

0x4746f8 LEA	(%R8,%RSI,8),%R12

0x4746fc VBROADCASTSD	%XMM11,%YMM15

0x474701 SHR	$0x2,%RCX

0x474705 SAL	$0x5,%RCX

0x474709 LEA	(%RCX,%R12,1),%R15

0x47470d SUB	$0x20,%RCX

0x474711 SHR	$0x5,%RCX

0x474715 INC	%RCX

0x474718 AND	$0x7,%ECX

0x47471b JE	4747c9

0x474721 CMP	$0x1,%RCX

0x474725 JE	4747af

0x47472b CMP	$0x2,%RCX

0x47472f JE	47479e

0x474731 CMP	$0x3,%RCX

0x474735 JE	47478d

0x474737 CMP	$0x4,%RCX

0x47473b JE	47477c

0x47473d CMP	$0x5,%RCX

0x474741 JE	47476b

0x474743 CMP	$0x6,%RCX

0x474747 JE	47475a

0x474749 VMULPD	(%R12),%YMM15,%YMM12

0x47474f ADD	$0x20,%R12

0x474753 VMOVUPD	%YMM12,-0x20(%R12)

0x47475a VMULPD	(%R12),%YMM15,%YMM4

0x474760 ADD	$0x20,%R12

0x474764 VMOVUPD	%YMM4,-0x20(%R12)

0x47476b VMULPD	(%R12),%YMM15,%YMM0

0x474771 ADD	$0x20,%R12

0x474775 VMOVUPD	%YMM0,-0x20(%R12)

0x47477c VMULPD	(%R12),%YMM15,%YMM1

0x474782 ADD	$0x20,%R12

0x474786 VMOVUPD	%YMM1,-0x20(%R12)

0x47478d VMULPD	(%R12),%YMM15,%YMM10

0x474793 ADD	$0x20,%R12

0x474797 VMOVUPD	%YMM10,-0x20(%R12)

0x47479e VMULPD	(%R12),%YMM15,%YMM5

0x4747a4 ADD	$0x20,%R12

0x4747a8 VMOVUPD	%YMM5,-0x20(%R12)

0x4747af VMULPD	(%R12),%YMM15,%YMM6

0x4747b5 ADD	$0x20,%R12

0x4747b9 VMOVUPD	%YMM6,-0x20(%R12)

0x4747c0 CMP	%R12,%R15

0x4747c3 JE	47485a

  (645) 0x4747c9 VMULPD	(%R12),%YMM15,%YMM14

  (645) 0x4747cf VMULPD	0x20(%R12),%YMM15,%YMM13

  (645) 0x4747d6 ADD	$0x100,%R12

  (645) 0x4747dd VMULPD	-0xc0(%R12),%YMM15,%YMM2

  (645) 0x4747e7 VMULPD	-0xa0(%R12),%YMM15,%YMM12

  (645) 0x4747f1 VMULPD	-0x80(%R12),%YMM15,%YMM4

  (645) 0x4747f8 VMULPD	-0x60(%R12),%YMM15,%YMM0

  (645) 0x4747ff VMULPD	-0x40(%R12),%YMM15,%YMM1

  (645) 0x474806 VMULPD	-0x20(%R12),%YMM15,%YMM10

  (645) 0x47480d VMOVUPD	%YMM14,-0x100(%R12)

  (645) 0x474817 VMOVUPD	%YMM13,-0xe0(%R12)

  (645) 0x474821 VMOVUPD	%YMM2,-0xc0(%R12)

  (645) 0x47482b VMOVUPD	%YMM12,-0xa0(%R12)

  (645) 0x474835 VMOVUPD	%YMM4,-0x80(%R12)

  (645) 0x47483c VMOVUPD	%YMM0,-0x60(%R12)

  (645) 0x474843 VMOVUPD	%YMM1,-0x40(%R12)

  (645) 0x47484a VMOVUPD	%YMM10,-0x20(%R12)

  (645) 0x474851 CMP	%R12,%R15

  (645) 0x474854 JNE	4747c9

0x47485a MOV	%RBX,%RAX

0x47485d AND	$-0x4,%RAX

0x474861 ADD	%RAX,%RSI

0x474864 AND	$0x3,%EBX

0x474867 JE	4748a9

0x474869 LEA	(,%RSI,8),%RBX

0x474871 LEA	0x1(%RSI),%R12

0x474875 LEA	(%R8,%RBX,1),%RDX

0x474879 VMULSD	(%RDX),%XMM11,%XMM15

0x47487d VMOVSD	%XMM15,(%RDX)

0x474881 CMP	%R12,%RDI

0x474884 JLE	4748a9

0x474886 LEA	0x8(%R8,%RBX,1),%RCX

0x47488b ADD	$0x2,%RSI

0x47488f VMULSD	(%RCX),%XMM11,%XMM5

0x474893 VMOVSD	%XMM5,(%RCX)

0x474897 CMP	%RDI,%RSI

0x47489a JGE	4748a9

0x47489c LEA	0x10(%R8,%RBX,1),%RSI

0x4748a1 VMULSD	(%RSI),%XMM11,%XMM6

0x4748a5 VMOVSD	%XMM6,(%RSI)

0x4748a9 VMOVQ	%XMM17,%RDI

0x4748af VMOVQ	%XMM16,%R15

0x4748b5 MOV	(%RDI),%R12

0x4748b8 MOV	(%R15),%RCX

0x4748bb CMP	%RCX,%R12

0x4748be JGE	474a49

0x4748c4 MOV	%RCX,%RBX

0x4748c7 SUB	%R12,%RBX

0x4748ca LEA	-0x1(%RBX),%RAX

0x4748ce CMP	$0x2,%RAX

0x4748d2 JBE	474a04

0x4748d8 MOV	%RBX,%RDX

0x4748db LEA	(%R10,%R12,8),%RSI

0x4748df VBROADCASTSD	%XMM11,%YMM14

0x4748e4 SHR	$0x2,%RDX

0x4748e8 SAL	$0x5,%RDX

0x4748ec LEA	(%RDX,%RSI,1),%RDI

0x4748f0 SUB	$0x20,%RDX

0x4748f4 SHR	$0x5,%RDX

0x4748f8 INC	%RDX

0x4748fb AND	$0x7,%EDX

0x4748fe JE	474988

0x474904 CMP	$0x1,%RDX

0x474908 JE	474976

0x47490a CMP	$0x2,%RDX

0x47490e JE	474969

0x474910 CMP	$0x3,%RDX

0x474914 JE	47495c

0x474916 CMP	$0x4,%RDX

0x47491a JE	47494f

0x47491c CMP	$0x5,%RDX

0x474920 JE	474942

0x474922 CMP	$0x6,%RDX

0x474926 JE	474935

0x474928 VMULPD	(%RSI),%YMM14,%YMM13

0x47492c ADD	$0x20,%RSI

0x474930 VMOVUPD	%YMM13,-0x20(%RSI)

0x474935 VMULPD	(%RSI),%YMM14,%YMM2

0x474939 ADD	$0x20,%RSI

0x47493d VMOVUPD	%YMM2,-0x20(%RSI)

0x474942 VMULPD	(%RSI),%YMM14,%YMM12

0x474946 ADD	$0x20,%RSI

0x47494a VMOVUPD	%YMM12,-0x20(%RSI)

0x47494f VMULPD	(%RSI),%YMM14,%YMM4

0x474953 ADD	$0x20,%RSI

0x474957 VMOVUPD	%YMM4,-0x20(%RSI)

0x47495c VMULPD	(%RSI),%YMM14,%YMM0

0x474960 ADD	$0x20,%RSI

0x474964 VMOVUPD	%YMM0,-0x20(%RSI)

0x474969 VMULPD	(%RSI),%YMM14,%YMM1

0x47496d ADD	$0x20,%RSI

0x474971 VMOVUPD	%YMM1,-0x20(%RSI)

0x474976 VMULPD	(%RSI),%YMM14,%YMM10

0x47497a ADD	$0x20,%RSI

0x47497e VMOVUPD	%YMM10,-0x20(%RSI)

0x474983 CMP	%RSI,%RDI

0x474986 JE	4749f5

  (644) 0x474988 VMULPD	(%RSI),%YMM14,%YMM15

  (644) 0x47498c VMULPD	0x20(%RSI),%YMM14,%YMM5

  (644) 0x474991 ADD	$0x100,%RSI

  (644) 0x474998 VMULPD	-0xc0(%RSI),%YMM14,%YMM6

  (644) 0x4749a0 VMULPD	-0xa0(%RSI),%YMM14,%YMM13

  (644) 0x4749a8 VMULPD	-0x80(%RSI),%YMM14,%YMM2

  (644) 0x4749ad VMULPD	-0x60(%RSI),%YMM14,%YMM12

  (644) 0x4749b2 VMULPD	-0x40(%RSI),%YMM14,%YMM4

  (644) 0x4749b7 VMULPD	-0x20(%RSI),%YMM14,%YMM0

  (644) 0x4749bc VMOVUPD	%YMM15,-0x100(%RSI)

  (644) 0x4749c4 VMOVUPD	%YMM5,-0xe0(%RSI)

  (644) 0x4749cc VMOVUPD	%YMM6,-0xc0(%RSI)

  (644) 0x4749d4 VMOVUPD	%YMM13,-0xa0(%RSI)

  (644) 0x4749dc VMOVUPD	%YMM2,-0x80(%RSI)

  (644) 0x4749e1 VMOVUPD	%YMM12,-0x60(%RSI)

  (644) 0x4749e6 VMOVUPD	%YMM4,-0x40(%RSI)

  (644) 0x4749eb VMOVUPD	%YMM0,-0x20(%RSI)

  (644) 0x4749f0 CMP	%RSI,%RDI

  (644) 0x4749f3 JNE	474988

0x4749f5 MOV	%RBX,%R15

0x4749f8 AND	$-0x4,%R15

0x4749fc ADD	%R15,%R12

0x4749ff AND	$0x3,%EBX

0x474a02 JE	474a49

0x474a04 LEA	(,%R12,8),%RBX

0x474a0c LEA	0x1(%R12),%RSI

0x474a11 LEA	(%R10,%RBX,1),%RAX

0x474a15 VMULSD	(%RAX),%XMM11,%XMM14

0x474a19 VMOVSD	%XMM14,(%RAX)

0x474a1d CMP	%RCX,%RSI

0x474a20 JGE	474a49

0x474a22 LEA	0x8(%R10,%RBX,1),%RDX

0x474a27 ADD	$0x2,%R12

0x474a2b VMULSD	(%RDX),%XMM11,%XMM1

0x474a2f VMOVSD	%XMM1,(%RDX)

0x474a33 CMP	%R12,%RCX

0x474a36 JLE	474a49

0x474a38 LEA	0x10(%R10,%RBX,1),%R12

0x474a3d VMULSD	(%R12),%XMM11,%XMM10

0x474a43 VMOVSD	%XMM10,(%R12)

0x474a49 ADDQ	$0x8,0xf8(%RSP)

0x474a52 MOV	0xf8(%RSP),%RCX

0x474a5a CMP	%RCX,0x88(%RSP)

0x474a62 JNE	473f40

  (651) 0x474ab0 MOV	0x118(%RSP),%RSI

  (651) 0x474ab8 VMOVQ	%XMM2,%RDX

  (651) 0x474abd INC	%RAX

  (651) 0x474ac0 MOV	%R12,(%RSI,%RCX,1)

  (651) 0x474ac4 MOV	(%RDX),%RSI

  (651) 0x474ac7 CMP	%RAX,%RSI

  (651) 0x474aca JG	474480

0x474ad0 JMP	4744ae

  (652) 0x474ae0 MOV	0xf0(%RSP),%RSI

  (652) 0x474ae8 VMOVQ	%XMM1,%RDX

  (652) 0x474aed INC	%RAX

  (652) 0x474af0 MOV	%R12,(%RSI,%RCX,1)

  (652) 0x474af4 MOV	(%RDX),%RSI

  (652) 0x474af7 CMP	%RAX,%RSI

  (652) 0x474afa JG	474400

0x474b00 JMP	47442e

  (648) 0x474b10 MOV	0xd8(%RSP),%RDI

  (648) 0x474b18 LEA	0x8(%R9),%R11

  (648) 0x474b1c VMOVQ	%R11,%XMM12

  (648) 0x474b21 MOV	(%RDI,%R9,1),%RDX

  (648) 0x474b25 MOV	0x8(%RDI,%R9,1),%RDI

  (648) 0x474b2a CMP	%RDI,%RDX

  (648) 0x474b2d JGE	474cc2

  (648) 0x474b33 MOV	%RDI,%R11

  (648) 0x474b36 SUB	%RDX,%R11

  (648) 0x474b39 AND	$0x3,%R11D

  (648) 0x474b3d JE	474bf0

  (648) 0x474b43 CMP	$0x1,%R11

  (648) 0x474b47 JE	474bb3

  (648) 0x474b49 CMP	$0x2,%R11

  (648) 0x474b4d JE	474b81

  (648) 0x474b4f MOV	(%R12,%RDX,8),%R11

  (648) 0x474b53 VMOVSD	(%RAX),%XMM11

  (648) 0x474b57 VMULSD	(%R8,%RDX,8),%XMM11,%XMM6

  (648) 0x474b5d INC	%RDX

  (648) 0x474b60 VADDSD	%XMM6,%XMM1,%XMM1

  (648) 0x474b64 VADDSD	%XMM6,%XMM0,%XMM0

  (648) 0x474b68 VMOVQ	(%R14,%R11,8),%XMM2

  (648) 0x474b6e VMOVQ	%XMM2,%R11

  (648) 0x474b73 LEA	(%R8,%R11,8),%R11

  (648) 0x474b77 VADDSD	(%R11),%XMM6,%XMM10

  (648) 0x474b7c VMOVSD	%XMM10,(%R11)

  (648) 0x474b81 MOV	(%R12,%RDX,8),%R11

  (648) 0x474b85 VMOVSD	(%RAX),%XMM11

  (648) 0x474b89 VMULSD	(%R8,%RDX,8),%XMM11,%XMM6

  (648) 0x474b8f INC	%RDX

  (648) 0x474b92 VADDSD	%XMM6,%XMM1,%XMM1

  (648) 0x474b96 VADDSD	%XMM6,%XMM0,%XMM0

  (648) 0x474b9a VMOVQ	(%R14,%R11,8),%XMM2

  (648) 0x474ba0 VMOVQ	%XMM2,%R11

  (648) 0x474ba5 LEA	(%R8,%R11,8),%R11

  (648) 0x474ba9 VADDSD	(%R11),%XMM6,%XMM10

  (648) 0x474bae VMOVSD	%XMM10,(%R11)

  (648) 0x474bb3 MOV	(%R12,%RDX,8),%R11

  (648) 0x474bb7 VMOVSD	(%RAX),%XMM11

  (648) 0x474bbb VMULSD	(%R8,%RDX,8),%XMM11,%XMM11

  (648) 0x474bc1 INC	%RDX

  (648) 0x474bc4 VADDSD	%XMM11,%XMM1,%XMM1

  (648) 0x474bc9 VADDSD	%XMM11,%XMM0,%XMM0

  (648) 0x474bce VMOVQ	(%R14,%R11,8),%XMM6

  (648) 0x474bd4 VMOVQ	%XMM6,%R11

  (648) 0x474bd9 LEA	(%R8,%R11,8),%R11

  (648) 0x474bdd VADDSD	(%R11),%XMM11,%XMM2

  (648) 0x474be2 VMOVSD	%XMM2,(%R11)

  (648) 0x474be7 CMP	%RDI,%RDX

  (648) 0x474bea JE	474cc2

  (648) 0x474bf0 MOV	%RSI,0xc8(%RSP)

  (648) 0x474bf8 VMOVQ	%XMM5,%R11

  (648) 0x474bfd MOV	%RCX,%RSI

  (648) 0x474c00 MOV	%RDI,%RCX

    (650) 0x474c03 MOV	(%R12,%RDX,8),%RDI

    (650) 0x474c07 VMOVSD	(%RAX),%XMM5

    (650) 0x474c0b VMULSD	(%R8,%RDX,8),%XMM5,%XMM11

    (650) 0x474c11 VADDSD	%XMM11,%XMM1,%XMM6

    (650) 0x474c16 VADDSD	%XMM11,%XMM0,%XMM0

    (650) 0x474c1b MOV	(%R14,%RDI,8),%RDI

    (650) 0x474c1f LEA	(%R8,%RDI,8),%RDI

    (650) 0x474c23 VADDSD	(%RDI),%XMM11,%XMM10

    (650) 0x474c27 VMOVSD	%XMM10,(%RDI)

    (650) 0x474c2b MOV	0x8(%R12,%RDX,8),%RDI

    (650) 0x474c30 VMOVSD	(%RAX),%XMM2

    (650) 0x474c34 VMULSD	0x8(%R8,%RDX,8),%XMM2,%XMM5

    (650) 0x474c3b VADDSD	%XMM5,%XMM6,%XMM11

    (650) 0x474c3f VADDSD	%XMM5,%XMM0,%XMM6

    (650) 0x474c43 MOV	(%R14,%RDI,8),%RDI

    (650) 0x474c47 LEA	(%R8,%RDI,8),%RDI

    (650) 0x474c4b VADDSD	(%RDI),%XMM5,%XMM1

    (650) 0x474c4f VMOVSD	%XMM1,(%RDI)

    (650) 0x474c53 MOV	0x10(%R12,%RDX,8),%RDI

    (650) 0x474c58 VMOVSD	(%RAX),%XMM10

    (650) 0x474c5c VMULSD	0x10(%R8,%RDX,8),%XMM10,%XMM0

    (650) 0x474c63 VADDSD	%XMM0,%XMM11,%XMM5

    (650) 0x474c67 VADDSD	%XMM0,%XMM6,%XMM6

    (650) 0x474c6b MOV	(%R14,%RDI,8),%RDI

    (650) 0x474c6f LEA	(%R8,%RDI,8),%RDI

    (650) 0x474c73 VADDSD	(%RDI),%XMM0,%XMM2

    (650) 0x474c77 VMOVSD	%XMM2,(%RDI)

    (650) 0x474c7b MOV	0x18(%R12,%RDX,8),%RDI

    (650) 0x474c80 VMOVSD	(%RAX),%XMM1

    (650) 0x474c84 VMULSD	0x18(%R8,%RDX,8),%XMM1,%XMM11

    (650) 0x474c8b ADD	$0x4,%RDX

    (650) 0x474c8f VADDSD	%XMM11,%XMM5,%XMM1

    (650) 0x474c94 VADDSD	%XMM11,%XMM6,%XMM0

    (650) 0x474c99 MOV	(%R14,%RDI,8),%RDI

    (650) 0x474c9d LEA	(%R8,%RDI,8),%RDI

    (650) 0x474ca1 VADDSD	(%RDI),%XMM11,%XMM10

    (650) 0x474ca5 VMOVSD	%XMM10,(%RDI)

    (650) 0x474ca9 CMP	%RCX,%RDX

    (650) 0x474cac JNE	474c03

  (648) 0x474cb2 MOV	%RSI,%RCX

  (648) 0x474cb5 MOV	0xc8(%RSP),%RSI

  (648) 0x474cbd VMOVQ	%R11,%XMM5

  (648) 0x474cc2 MOV	0xe0(%RSP),%RDI

  (648) 0x474cca MOV	(%RDI,%R9,1),%RDX

  (648) 0x474cce VMOVQ	%XMM12,%R9

  (648) 0x474cd3 MOV	(%RDI,%R9,1),%RDI

  (648) 0x474cd7 CMP	%RDI,%RDX

  (648) 0x474cda JGE	474547

  (648) 0x474ce0 MOV	%RDI,%R11

  (648) 0x474ce3 SUB	%RDX,%R11

  (648) 0x474ce6 AND	$0x3,%R11D

  (648) 0x474cea JE	474d9e

  (648) 0x474cf0 CMP	$0x1,%R11

  (648) 0x474cf4 JE	474d62

  (648) 0x474cf6 CMP	$0x2,%R11

  (648) 0x474cfa JE	474d2f

  (648) 0x474cfc VMOVQ	%XMM5,%R9

  (648) 0x474d01 VMOVSD	(%RAX),%XMM12

  (648) 0x474d05 VMULSD	(%R10,%RDX,8),%XMM12,%XMM11

  (648) 0x474d0b VADDSD	%XMM11,%XMM1,%XMM1

  (648) 0x474d10 MOV	(%R9,%RDX,8),%R11

  (648) 0x474d14 INC	%RDX

  (648) 0x474d17 VADDSD	%XMM11,%XMM0,%XMM0

  (648) 0x474d1c MOV	(%R13,%R11,8),%R9

  (648) 0x474d21 LEA	(%R10,%R9,8),%R11

  (648) 0x474d25 VADDSD	(%R11),%XMM11,%XMM2

  (648) 0x474d2a VMOVSD	%XMM2,(%R11)

  (648) 0x474d2f VMOVQ	%XMM5,%R9

  (648) 0x474d34 VMOVSD	(%RAX),%XMM6

  (648) 0x474d38 VMULSD	(%R10,%RDX,8),%XMM6,%XMM10

  (648) 0x474d3e VADDSD	%XMM10,%XMM1,%XMM1

  (648) 0x474d43 MOV	(%R9,%RDX,8),%R11

  (648) 0x474d47 INC	%RDX

  (648) 0x474d4a VADDSD	%XMM10,%XMM0,%XMM0

  (648) 0x474d4f MOV	(%R13,%R11,8),%R9

  (648) 0x474d54 LEA	(%R10,%R9,8),%R11

  (648) 0x474d58 VADDSD	(%R11),%XMM10,%XMM12

  (648) 0x474d5d VMOVSD	%XMM12,(%R11)

  (648) 0x474d62 VMOVQ	%XMM5,%R9

  (648) 0x474d67 VMOVSD	(%RAX),%XMM11

  (648) 0x474d6b VMULSD	(%R10,%RDX,8),%XMM11,%XMM11

  (648) 0x474d71 VADDSD	%XMM11,%XMM1,%XMM1

  (648) 0x474d76 MOV	(%R9,%RDX,8),%R11

  (648) 0x474d7a INC	%RDX

  (648) 0x474d7d VADDSD	%XMM11,%XMM0,%XMM0

  (648) 0x474d82 MOV	(%R13,%R11,8),%R9

  (648) 0x474d87 LEA	(%R10,%R9,8),%R11

  (648) 0x474d8b VADDSD	(%R11),%XMM11,%XMM2

  (648) 0x474d90 VMOVSD	%XMM2,(%R11)

  (648) 0x474d95 CMP	%RDI,%RDX

  (648) 0x474d98 JE	474547

  (648) 0x474d9e VMOVQ	%XMM5,%R11

    (649) 0x474da3 MOV	(%R11,%RDX,8),%R9

    (649) 0x474da7 VMOVSD	(%RAX),%XMM5

    (649) 0x474dab VMULSD	(%R10,%RDX,8),%XMM5,%XMM10

    (649) 0x474db1 VADDSD	%XMM10,%XMM1,%XMM1

    (649) 0x474db6 VADDSD	%XMM10,%XMM0,%XMM0

    (649) 0x474dbb MOV	(%R13,%R9,8),%R9

    (649) 0x474dc0 LEA	(%R10,%R9,8),%R9

    (649) 0x474dc4 VADDSD	(%R9),%XMM10,%XMM6

    (649) 0x474dc9 VMOVSD	%XMM6,(%R9)

    (649) 0x474dce MOV	0x8(%R11,%RDX,8),%R9

    (649) 0x474dd3 VMOVSD	(%RAX),%XMM12

    (649) 0x474dd7 VMULSD	0x8(%R10,%RDX,8),%XMM12,%XMM11

    (649) 0x474dde VADDSD	%XMM11,%XMM1,%XMM5

    (649) 0x474de3 VADDSD	%XMM11,%XMM0,%XMM10

    (649) 0x474de8 MOV	(%R13,%R9,8),%R9

    (649) 0x474ded LEA	(%R10,%R9,8),%R9

    (649) 0x474df1 VADDSD	(%R9),%XMM11,%XMM2

    (649) 0x474df6 VMOVSD	%XMM2,(%R9)

    (649) 0x474dfb MOV	0x10(%R11,%RDX,8),%R9

    (649) 0x474e00 VMOVSD	(%RAX),%XMM6

    (649) 0x474e04 VMULSD	0x10(%R10,%RDX,8),%XMM6,%XMM0

    (649) 0x474e0b VADDSD	%XMM0,%XMM5,%XMM12

    (649) 0x474e0f VADDSD	%XMM0,%XMM10,%XMM5

    (649) 0x474e13 MOV	(%R13,%R9,8),%R9

    (649) 0x474e18 LEA	(%R10,%R9,8),%R9

    (649) 0x474e1c VADDSD	(%R9),%XMM0,%XMM1

    (649) 0x474e21 VMOVSD	%XMM1,(%R9)

    (649) 0x474e26 MOV	0x18(%R11,%RDX,8),%R9

    (649) 0x474e2b VMOVSD	(%RAX),%XMM11

    (649) 0x474e2f VMULSD	0x18(%R10,%RDX,8),%XMM11,%XMM11

    (649) 0x474e36 ADD	$0x4,%RDX

    (649) 0x474e3a VADDSD	%XMM11,%XMM12,%XMM1

    (649) 0x474e3f VADDSD	%XMM11,%XMM5,%XMM0

    (649) 0x474e44 MOV	(%R13,%R9,8),%R9

    (649) 0x474e49 LEA	(%R10,%R9,8),%R9

    (649) 0x474e4d VADDSD	(%R9),%XMM11,%XMM2

    (649) 0x474e52 VMOVSD	%XMM2,(%R9)

    (649) 0x474e57 CMP	%RDI,%RDX

    (649) 0x474e5a JNE	474da3

  (648) 0x474e60 VMOVQ	%R11,%XMM5

  (648) 0x474e65 JMP	474547

  (646) 0x474e70 MOV	0x38(%RSP),%RCX

  (646) 0x474e75 MOV	0x40(%RSP),%R13

  (646) 0x474e7a MOV	(%RCX,%R15,1),%RCX

  (646) 0x474e7e MOV	0x8(%R13,%R15,1),%R15

  (646) 0x474e83 ADD	%RCX,%R15

  (646) 0x474e86 CMP	%R15,%RCX

  (646) 0x474e89 JGE	47462f

  (646) 0x474e8f MOV	0x30(%RSP),%R9

  (646) 0x474e94 VMOVQ	%XMM7,%R13

  (646) 0x474e99 VMOVQ	(%R9,%R13,1),%XMM10

  (646) 0x474e9f MOV	%R15,%R9

  (646) 0x474ea2 SUB	%RCX,%R9

  (646) 0x474ea5 AND	$0x3,%R9D

  (646) 0x474ea9 JE	474fae

  (646) 0x474eaf CMP	$0x1,%R9

  (646) 0x474eb3 JE	474f58

  (646) 0x474eb9 CMP	$0x2,%R9

  (646) 0x474ebd JE	474f0d

  (646) 0x474ebf VMOVQ	%XMM10,%R13

  (646) 0x474ec4 VMOVSD	(%RDX),%XMM12

  (646) 0x474ec8 MOV	(%R13,%RCX,8),%R9

  (646) 0x474ecd MOV	0xc0(%RSP),%R13

  (646) 0x474ed5 VMULSD	(%R13,%RCX,8),%XMM12,%XMM11

  (646) 0x474edc TEST	%R9,%R9

  (646) 0x474edf JS	4751b3

  (646) 0x474ee5 VMOVQ	(%RDI,%R9,8),%XMM2

  (646) 0x474eeb VMOVQ	%XMM2,%R9

  (646) 0x474ef0 LEA	(%R10,%R9,8),%R13

  (646) 0x474ef4 VADDSD	(%R13),%XMM11,%XMM4

  (646) 0x474efa VMOVSD	%XMM4,(%R13)

  (646) 0x474f00 INC	%RCX

  (646) 0x474f03 VADDSD	%XMM11,%XMM1,%XMM1

  (646) 0x474f08 VADDSD	%XMM11,%XMM0,%XMM0

  (646) 0x474f0d VMOVQ	%XMM10,%R13

  (646) 0x474f12 MOV	0xc0(%RSP),%R9

  (646) 0x474f1a VMOVSD	(%RDX),%XMM11

  (646) 0x474f1e MOV	(%R13,%RCX,8),%R13

  (646) 0x474f23 VMULSD	(%R9,%RCX,8),%XMM11,%XMM4

  (646) 0x474f29 TEST	%R13,%R13

  (646) 0x474f2c JS	475180

  (646) 0x474f32 VMOVQ	(%RDI,%R13,8),%XMM12

  (646) 0x474f38 VMOVQ	%XMM12,%R9

  (646) 0x474f3d LEA	(%R10,%R9,8),%R13

  (646) 0x474f41 VADDSD	(%R13),%XMM4,%XMM2

  (646) 0x474f47 VMOVSD	%XMM2,(%R13)

  (646) 0x474f4d INC	%RCX

  (646) 0x474f50 VADDSD	%XMM4,%XMM1,%XMM1

  (646) 0x474f54 VADDSD	%XMM4,%XMM0,%XMM0

  (646) 0x474f58 VMOVQ	%XMM10,%R13

  (646) 0x474f5d MOV	0xc0(%RSP),%R9

  (646) 0x474f65 VMOVSD	(%RDX),%XMM4

  (646) 0x474f69 MOV	(%R13,%RCX,8),%R13

  (646) 0x474f6e VMULSD	(%R9,%RCX,8),%XMM4,%XMM11

  (646) 0x474f74 TEST	%R13,%R13

  (646) 0x474f77 JS	475140

  (646) 0x474f7d VMOVQ	(%RDI,%R13,8),%XMM2

  (646) 0x474f83 VMOVQ	%XMM2,%R9

  (646) 0x474f88 LEA	(%R10,%R9,8),%R13

  (646) 0x474f8c VADDSD	(%R13),%XMM11,%XMM12

  (646) 0x474f92 VMOVSD	%XMM12,(%R13)

  (646) 0x474f98 INC	%RCX

  (646) 0x474f9b VADDSD	%XMM11,%XMM1,%XMM1

  (646) 0x474fa0 VADDSD	%XMM11,%XMM0,%XMM0

  (646) 0x474fa5 CMP	%RCX,%R15

  (646) 0x474fa8 JE	47462f

  (646) 0x474fae MOV	0xc0(%RSP),%R13

  (646) 0x474fb6 VMOVQ	%XMM10,%R9

  (646) 0x474fbb MOV	%R15,0xc8(%RSP)

  (646) 0x474fc3 MOV	%RAX,0x28(%RSP)

  (646) 0x474fc8 JMP	47509d

    (647) 0x474fd0 MOV	(%RDI,%RAX,8),%R15

    (647) 0x474fd4 LEA	(%R10,%R15,8),%RAX

    (647) 0x474fd8 VADDSD	(%RAX),%XMM11,%XMM12

    (647) 0x474fdc VMOVSD	%XMM12,(%RAX)

    (647) 0x474fe0 INC	%RCX

    (647) 0x474fe3 VMOVSD	(%RDX),%XMM2

    (647) 0x474fe7 VADDSD	%XMM11,%XMM1,%XMM1

    (647) 0x474fec VADDSD	%XMM11,%XMM0,%XMM0

    (647) 0x474ff1 MOV	(%R9,%RCX,8),%R15

    (647) 0x474ff5 VMULSD	(%R13,%RCX,8),%XMM2,%XMM10

    (647) 0x474ffc TEST	%R15,%R15

    (647) 0x474fff JS	475120

    (647) 0x475005 MOV	(%RDI,%R15,8),%RAX

    (647) 0x475009 LEA	(%R10,%RAX,8),%R15

    (647) 0x47500d VADDSD	(%R15),%XMM10,%XMM11

    (647) 0x475012 VMOVSD	%XMM11,(%R15)

    (647) 0x475017 LEA	0x1(%RCX),%R15

    (647) 0x47501b VADDSD	%XMM10,%XMM1,%XMM4

    (647) 0x475020 VADDSD	%XMM10,%XMM0,%XMM0

    (647) 0x475025 VMOVSD	(%RDX),%XMM1

    (647) 0x475029 MOV	(%R9,%R15,8),%RAX

    (647) 0x47502d VMULSD	(%R13,%R15,8),%XMM1,%XMM10

    (647) 0x475034 TEST	%RAX,%RAX

    (647) 0x475037 JS	475100

    (647) 0x47503d MOV	(%RDI,%RAX,8),%R15

    (647) 0x475041 LEA	(%R10,%R15,8),%RAX

    (647) 0x475045 VADDSD	(%RAX),%XMM10,%XMM2

    (647) 0x475049 VMOVSD	%XMM2,(%RAX)

    (647) 0x47504d LEA	0x2(%RCX),%RAX

    (647) 0x475051 VADDSD	%XMM10,%XMM4,%XMM12

    (647) 0x475056 VADDSD	%XMM10,%XMM0,%XMM4

    (647) 0x47505b VMOVSD	(%RDX),%XMM0

    (647) 0x47505f MOV	(%R9,%RAX,8),%R15

    (647) 0x475063 VMULSD	(%R13,%RAX,8),%XMM0,%XMM11

    (647) 0x47506a TEST	%R15,%R15

    (647) 0x47506d JS	4750e0

    (647) 0x47506f MOV	(%RDI,%R15,8),%RAX

    (647) 0x475073 LEA	(%R10,%RAX,8),%R15

    (647) 0x475077 VADDSD	(%R15),%XMM11,%XMM1

    (647) 0x47507c VMOVSD	%XMM1,(%R15)

    (647) 0x475081 ADD	$0x3,%RCX

    (647) 0x475085 VADDSD	%XMM11,%XMM12,%XMM1

    (647) 0x47508a VADDSD	%XMM11,%XMM4,%XMM0

    (647) 0x47508f CMP	%RCX,0xc8(%RSP)

    (647) 0x475097 JE	475170

    (647) 0x47509d MOV	(%R9,%RCX,8),%RAX

    (647) 0x4750a1 VMOVSD	(%RDX),%XMM10

    (647) 0x4750a5 VMULSD	(%R13,%RCX,8),%XMM10,%XMM11

    (647) 0x4750ac TEST	%RAX,%RAX

    (647) 0x4750af JNS	474fd0

    (647) 0x4750b5 NOT	%RAX

    (647) 0x4750b8 VMOVQ	%XMM5,%R15

    (647) 0x4750bd MOV	(%R12,%RAX,8),%RAX

    (647) 0x4750c1 LEA	(%R15,%RAX,8),%RAX

    (647) 0x4750c5 VADDSD	(%RAX),%XMM11,%XMM4

    (647) 0x4750c9 VMOVSD	%XMM4,(%RAX)

    (647) 0x4750cd JMP	474fe0

    (647) 0x4750e0 NOT	%R15

    (647) 0x4750e3 MOV	(%R12,%R15,8),%RAX

    (647) 0x4750e7 VMOVQ	%XMM5,%R15

    (647) 0x4750ec LEA	(%R15,%RAX,8),%RAX

    (647) 0x4750f0 VADDSD	(%RAX),%XMM11,%XMM10

    (647) 0x4750f4 VMOVSD	%XMM10,(%RAX)

    (647) 0x4750f8 JMP	475081

    (647) 0x475100 NOT	%RAX

    (647) 0x475103 VMOVQ	%XMM5,%R15

    (647) 0x475108 MOV	(%R12,%RAX,8),%RAX

    (647) 0x47510c LEA	(%R15,%RAX,8),%RAX

    (647) 0x475110 VADDSD	(%RAX),%XMM10,%XMM11

    (647) 0x475114 VMOVSD	%XMM11,(%RAX)

    (647) 0x475118 JMP	47504d

    (647) 0x475120 NOT	%R15

    (647) 0x475123 MOV	(%R12,%R15,8),%RAX

    (647) 0x475127 VMOVQ	%XMM5,%R15

    (647) 0x47512c LEA	(%R15,%RAX,8),%RAX

    (647) 0x475130 VADDSD	(%RAX),%XMM10,%XMM12

    (647) 0x475134 VMOVSD	%XMM12,(%RAX)

    (647) 0x475138 JMP	475017

  (646) 0x475140 NOT	%R13

  (646) 0x475143 VMOVQ	%XMM5,%R9

  (646) 0x475148 VMOVQ	(%R12,%R13,8),%XMM4

  (646) 0x47514e VMOVQ	%XMM4,%R13

  (646) 0x475153 LEA	(%R9,%R13,8),%R9

  (646) 0x475157 VADDSD	(%R9),%XMM11,%XMM2

  (646) 0x47515c VMOVSD	%XMM2,(%R9)

  (646) 0x475161 JMP	474f98

  (646) 0x475170 MOV	0x28(%RSP),%RAX

  (646) 0x475175 JMP	47462f

  (646) 0x475180 NOT	%R13

  (646) 0x475183 VMOVQ	%XMM5,%R9

  (646) 0x475188 VMOVQ	(%R12,%R13,8),%XMM11

  (646) 0x47518e VMOVQ	%XMM11,%R13

  (646) 0x475193 LEA	(%R9,%R13,8),%R9

  (646) 0x475197 VADDSD	(%R9),%XMM4,%XMM12

  (646) 0x47519c VMOVSD	%XMM12,(%R9)

  (646) 0x4751a1 JMP	474f4d

0x4751a6 VXORPD	%XMM0,%XMM0,%XMM0

0x4751aa VMOVAPD	%XMM0,%XMM1

0x4751ae JMP	4745a9

  (646) 0x4751b3 NOT	%R9

  (646) 0x4751b6 VMOVQ	(%R12,%R9,8),%XMM12

  (646) 0x4751bc VMOVQ	%XMM5,%R9

  (646) 0x4751c1 VMOVQ	%XMM12,%R13

  (646) 0x4751c6 LEA	(%R9,%R13,8),%R9

  (646) 0x4751ca VADDSD	(%R9),%XMM11,%XMM2

  (646) 0x4751cf VMOVSD	%XMM2,(%R9)

  (646) 0x4751d4 JMP	474f00

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►96.46+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.84+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.35
CQA speedup if FP arith vectorized	2.23
CQA speedup if fully vectorized	8.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1840-1840,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	51.63
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	23.16
CQA cycles if fully vectorized	6.02
Front-end cycles	51.63
P0 cycles	35.83
P1 cycles	35.83
P2 cycles	35.83
P3 cycles	35.83
P4 cycles	35.83
P5 cycles	35.83
P6 cycles	36.50
P7 cycles	36.50
P8 cycles	36.50
P9 cycles	36.50
P10 cycles	11.50
P11 cycles	11.00
P12 cycles	2.00
P13 cycles	1.50
P14 cycles	22.00
P15 cycles	22.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	414.00
Nb uops	413.00
Nb loads	96.00
Nb stores	63.00
Nb stack references	20.00
FLOP/cycle	1.24
Nb FLOP add-sub	0.00
Nb FLOP mul	63.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.02
Bytes prefetched	0.00
Bytes loaded	968.00
Bytes stored	840.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.75
Vectorization ratio load	60.87
Vectorization ratio store	22.22
Vectorization ratio mul	66.67
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	5.56
Vector-efficiency ratio all	18.32
Vector-efficiency ratio load	35.33
Vector-efficiency ratio store	19.44
Vector-efficiency ratio mul	37.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	13.19

Metric	Value
CQA speedup if no scalar integer	2.35
CQA speedup if FP arith vectorized	2.23
CQA speedup if fully vectorized	8.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1840-1840,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	51.63
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	23.16
CQA cycles if fully vectorized	6.02
Front-end cycles	51.63
P0 cycles	35.83
P1 cycles	35.83
P2 cycles	35.83
P3 cycles	35.83
P4 cycles	35.83
P5 cycles	35.83
P6 cycles	36.50
P7 cycles	36.50
P8 cycles	36.50
P9 cycles	36.50
P10 cycles	11.50
P11 cycles	11.00
P12 cycles	2.00
P13 cycles	1.50
P14 cycles	22.00
P15 cycles	22.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	414.00
Nb uops	413.00
Nb loads	96.00
Nb stores	63.00
Nb stack references	20.00
FLOP/cycle	1.24
Nb FLOP add-sub	0.00
Nb FLOP mul	63.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.02
Bytes prefetched	0.00
Bytes loaded	968.00
Bytes stored	840.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.75
Vectorization ratio load	60.87
Vectorization ratio store	22.22
Vectorization ratio mul	66.67
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	5.56
Vector-efficiency ratio all	18.32
Vector-efficiency ratio load	35.33
Vector-efficiency ratio store	19.44
Vector-efficiency ratio mul	37.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	13.19

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1876.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1799,1805,1811,1840,1871-1876.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 51.63 to 22.00 cycles (2.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1780
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1874
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1874
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1876
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1876
VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1871

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 14 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

63: multiply
1: divide

The binary loop is loading 968 bytes (121 double precision FP elements). The binary loop is storing 840 bytes (105 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	414
nb uops	413
loop length	1859
used x86 registers	15
used mmx registers	0
used xmm registers	18
used ymm registers	11
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.63 cycles
front end	51.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	35.83	35.83	35.83	35.83	35.83	35.83	36.50	36.50	36.50	36.50	11.50	11.00	2.00	1.50	22.00	22.00
cycles	35.83	35.83	35.83	35.83	35.83	35.83	36.50	36.50	36.50	36.50	11.50	11.00	2.00	1.50	22.00	22.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	51.63
Dispatch	36.50
DIV/SQRT	4.00
Overall L1	51.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	66%
store	70%
mul	66%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	62%

INT+FP

all	18%
load	60%
store	22%
mul	66%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	5%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	34%
load	37%
store	38%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

INT+FP

all	18%
load	35%
store	19%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 51.63 cycles. At this rate:

7% of peak load performance is reached (18.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 51.63 to 36.50 cycles (1.41x speedup).

ASM code

In the binary file, the address of the loop is: 473f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R12,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%RAX,%RBX,1),%RDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV (%RCX,%RBX,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %RBX,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%RBX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47416d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SUB %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX,%RCX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 47409c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x54c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47407b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x52b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474063 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47404b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474033 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47401b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4cb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474003 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47416d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%R15,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX,%RSI,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RBX,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RCX,%XMM17	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47439b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x84b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RBX,%RCX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4742c2 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x772>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4742a0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474287 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x737>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47426e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x71e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474255 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x705>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47423c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474223 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47439b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x84b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xa0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %R8,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RDI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RSI,%R15,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RSI,%RAX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RBX,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM3,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47443d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RBX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM5,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RBX,%R15,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RAX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RCX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4744b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x968>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R8,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RDI,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVQ %XMM6,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ (%RBX,%RAX,1),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX,%R15,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4751a6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1656>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R15,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R11,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RBX,%RAX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 474554 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa04>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM5,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x98(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RCX,%RSI,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R15,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4746a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R9,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R8,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x48(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%R15,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 47463c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xaec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM5,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM18,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD (%RCX,%R15,8),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 4746cd <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM9,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VDIVSD %XMM13,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMOVQ %XMM15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 474869 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%R12,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4747c9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc79>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4747af <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc5f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47479e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc4e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47478d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47477c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc2c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47476b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc1b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47475a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%R12),%YMM15,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM12,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM4,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM1,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM10,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM5,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM6,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
CMP %R12,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47485a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RSI,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RSI),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM11,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM15,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%RBX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
ADD $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RCX),%XMM11,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x10(%R8,%RBX,1),%RSI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
VMULSD (%RSI),%XMM11,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM16,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 474a04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xeb4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RSI,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 474988 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe38>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474976 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe26>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474969 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47495c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47494f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474942 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdf2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474935 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xde5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RSI),%YMM14,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM13,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM2,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM12,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM4,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM1,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM10,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
CMP %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4749f5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%R12,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R12),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RAX),%XMM11,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM14,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R10,%RBX,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
ADD $0x2,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RDX),%XMM11,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x10(%R10,%RBX,1),%R12	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
VMULSD (%R12),%XMM11,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADDQ $0x8,0xf8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,0x88(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 473f40 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 4744ae <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x95e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 47442e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8de>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4745a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1780
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1874
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1874
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1876
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1876
VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1871

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

63: multiply
1: divide

The binary loop is loading 968 bytes (121 double precision FP elements). The binary loop is storing 840 bytes (105 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	414
nb uops	413
loop length	1859
used x86 registers	15
used mmx registers	0
used xmm registers	18
used ymm registers	11
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.63 cycles
front end	51.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	35.83	35.83	35.83	35.83	35.83	35.83	36.50	36.50	36.50	36.50	11.50	11.00	2.00	1.50	22.00	22.00
cycles	35.83	35.83	35.83	35.83	35.83	35.83	36.50	36.50	36.50	36.50	11.50	11.00	2.00	1.50	22.00	22.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	51.63
Dispatch	36.50
DIV/SQRT	4.00
Overall L1	51.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	66%
store	70%
mul	66%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	62%

INT+FP

all	18%
load	60%
store	22%
mul	66%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	5%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	34%
load	37%
store	38%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

INT+FP

all	18%
load	35%
store	19%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 51.63 cycles. At this rate:

7% of peak load performance is reached (18.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 473f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R12,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%RAX,%RBX,1),%RDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV (%RCX,%RBX,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %RBX,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%RBX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47416d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SUB %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX,%RCX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 47409c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x54c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47407b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x52b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474063 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47404b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474033 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47401b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4cb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474003 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R9,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47416d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%R15,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX,%RSI,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RBX,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RCX,%XMM17	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47439b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x84b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RBX,%RCX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4742c2 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x772>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4742a0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474287 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x737>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47426e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x71e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474255 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x705>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47423c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474223 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX,%RAX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%R13,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x8(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47439b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x84b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xa0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %R8,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RDI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RSI,%R15,1),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RSI,%RAX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RBX,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM3,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 47443d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RBX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM5,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RBX,%R15,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RAX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RCX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4744b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x968>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R8,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %RDI,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVQ %XMM6,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ (%RBX,%RAX,1),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX,%R15,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4751a6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1656>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R15,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R11,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RBX,%RAX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 474554 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa04>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM5,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x98(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RCX,%RSI,1),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R15,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4746a8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %R9,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R8,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x48(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%R15,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 47463c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xaec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM5,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM18,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD (%RCX,%R15,8),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 4746cd <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM9,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VDIVSD %XMM13,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMOVQ %XMM15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 474869 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%R12,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4747c9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc79>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4747af <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc5f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47479e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc4e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47478d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47477c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc2c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47476b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc1b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47475a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%R12),%YMM15,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM12,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM4,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM1,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM10,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM5,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%R12),%YMM15,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM6,-0x20(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
CMP %R12,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47485a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RSI,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RSI),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RDX),%XMM11,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM15,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%RBX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
ADD $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RCX),%XMM11,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4748a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x10(%R8,%RBX,1),%RSI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
VMULSD (%RSI),%XMM11,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM17,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM16,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 474a04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xeb4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RDX,%RSI,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 474988 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe38>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474976 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe26>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474969 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47495c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47494f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474942 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdf2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 474935 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xde5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RSI),%YMM14,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM13,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM2,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM12,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM4,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM1,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RSI),%YMM14,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM10,-0x20(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
CMP %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4749f5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%R12,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R12),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RAX),%XMM11,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM14,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R10,%RBX,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
ADD $0x2,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%RDX),%XMM11,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 474a49 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xef9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x10(%R10,%RBX,1),%R12	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
VMULSD (%R12),%XMM11,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADDQ $0x8,0xf8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,0x88(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 473f40 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x3f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 4744ae <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x95e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 47442e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8de>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4745a9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa59>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code