OV - exec - Loop 615

	Loop Id: 615	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.06%

0x46f290 MOV	-0xc0(%RBP),%R14

0x46f297 MOV	-0x40(%RBP),%R13

0x46f29b MOV	-0xd0(%RBP),%R8

0x46f2a2 MOV	-0x70(%RBP),%R11

0x46f2a6 MOV	-0x68(%RBP),%RDI

0x46f2aa MOV	(%R14,%R13,8),%R15

0x46f2ae LEA	(,%R15,8),%RSI

0x46f2b6 LEA	0x8(%R8,%RSI,1),%R14

0x46f2bb MOV	%RCX,(%R11,%RSI,1)

0x46f2bf MOV	%RDX,(%RDI,%RSI,1)

0x46f2c3 MOV	-0x48(%RBP),%RDI

0x46f2c7 MOV	(%R8,%RSI,1),%RAX

0x46f2cb MOV	(%R14),%R13

0x46f2ce VMOVQ	%R14,%XMM7

0x46f2d3 MOV	-0x50(%RBP),%R14

0x46f2d7 LEA	0x8(%RSI),%R11

0x46f2db MOV	%R11,-0x90(%RBP)

0x46f2e2 LEA	(%RDI,%R11,1),%R8

0x46f2e6 ADD	%R11,%R14

0x46f2e9 CMP	%R13,%RAX

0x46f2ec JGE	46f7d1

0x46f2f2 VMOVQ	%RSI,%XMM3

0x46f2f7 MOV	-0x38(%RBP),%RDI

0x46f2fb MOV	%R12,%RSI

0x46f2fe VMOVQ	%R8,%XMM1

0x46f303 MOV	%RBX,%R12

0x46f306 MOV	%RCX,%RBX

0x46f309 MOV	%RDX,%RCX

0x46f30c JMP	46f32c

  (618) 0x46f320 INC	%RAX

  (618) 0x46f323 CMP	%R13,%RAX

  (618) 0x46f326 JGE	46f7c0

  (618) 0x46f32c MOV	(%R10,%RAX,8),%RDX

  (618) 0x46f330 LEA	(,%RDX,8),%R8

  (618) 0x46f338 CMP	%R9,(%RDI,%RDX,8)

  (618) 0x46f33c JNE	46f320

  (618) 0x46f33e MOV	-0x70(%RBP),%R13

  (618) 0x46f342 MOV	-0x50(%RBP),%RDX

  (618) 0x46f346 LEA	0x8(%R8),%R11

  (618) 0x46f34a VMOVQ	%R11,%XMM4

  (618) 0x46f34f MOV	(%R13,%R8,1),%R13

  (618) 0x46f354 MOV	0x8(%RDX,%R8,1),%R11

  (618) 0x46f359 ADD	%R13,%R11

  (618) 0x46f35c VMOVQ	%R11,%XMM5

  (618) 0x46f361 CMP	%R11,%R13

  (618) 0x46f364 JGE	46f567

  (618) 0x46f36a MOV	-0x80(%RBP),%R11

  (618) 0x46f36e VMOVQ	%XMM6,%RDX

  (618) 0x46f373 MOV	-0x8(%R11,%RDX,1),%R11

  (618) 0x46f378 VMOVQ	%XMM5,%RDX

  (618) 0x46f37d LEA	(%R11,%R13,8),%R13

  (618) 0x46f381 LEA	(%R11,%RDX,8),%R11

  (618) 0x46f385 MOV	%R11,-0x60(%RBP)

  (618) 0x46f389 SUB	%R13,%R11

  (618) 0x46f38c SUB	$0x8,%R11

  (618) 0x46f390 SHR	$0x3,%R11

  (618) 0x46f394 INC	%R11

  (618) 0x46f397 AND	$0x7,%R11D

  (618) 0x46f39b JE	46f48d

  (618) 0x46f3a1 CMP	$0x1,%R11

  (618) 0x46f3a5 JE	46f469

  (618) 0x46f3ab CMP	$0x2,%R11

  (618) 0x46f3af JE	46f44f

  (618) 0x46f3b5 CMP	$0x3,%R11

  (618) 0x46f3b9 JE	46f435

  (618) 0x46f3bb CMP	$0x4,%R11

  (618) 0x46f3bf JE	46f41b

  (618) 0x46f3c1 CMP	$0x5,%R11

  (618) 0x46f3c5 JE	46f401

  (618) 0x46f3c7 CMP	$0x6,%R11

  (618) 0x46f3cb JE	46f3e7

  (618) 0x46f3cd MOV	(%R13),%RDX

  (618) 0x46f3d1 LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f3d5 CMP	(%R11),%R15

  (618) 0x46f3d8 JE	46f3e3

  (618) 0x46f3da INC	%RBX

  (618) 0x46f3dd INCQ	(%R14)

  (618) 0x46f3e0 MOV	%R15,(%R11)

  (618) 0x46f3e3 ADD	$0x8,%R13

  (618) 0x46f3e7 MOV	(%R13),%RDX

  (618) 0x46f3eb LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f3ef CMP	(%R11),%R15

  (618) 0x46f3f2 JE	46f3fd

  (618) 0x46f3f4 INC	%RBX

  (618) 0x46f3f7 INCQ	(%R14)

  (618) 0x46f3fa MOV	%R15,(%R11)

  (618) 0x46f3fd ADD	$0x8,%R13

  (618) 0x46f401 MOV	(%R13),%RDX

  (618) 0x46f405 LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f409 CMP	(%R11),%R15

  (618) 0x46f40c JE	46f417

  (618) 0x46f40e INC	%RBX

  (618) 0x46f411 INCQ	(%R14)

  (618) 0x46f414 MOV	%R15,(%R11)

  (618) 0x46f417 ADD	$0x8,%R13

  (618) 0x46f41b MOV	(%R13),%RDX

  (618) 0x46f41f LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f423 CMP	(%R11),%R15

  (618) 0x46f426 JE	46f431

  (618) 0x46f428 INC	%RBX

  (618) 0x46f42b INCQ	(%R14)

  (618) 0x46f42e MOV	%R15,(%R11)

  (618) 0x46f431 ADD	$0x8,%R13

  (618) 0x46f435 MOV	(%R13),%RDX

  (618) 0x46f439 LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f43d CMP	(%R11),%R15

  (618) 0x46f440 JE	46f44b

  (618) 0x46f442 INC	%RBX

  (618) 0x46f445 INCQ	(%R14)

  (618) 0x46f448 MOV	%R15,(%R11)

  (618) 0x46f44b ADD	$0x8,%R13

  (618) 0x46f44f MOV	(%R13),%RDX

  (618) 0x46f453 LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f457 CMP	(%R11),%R15

  (618) 0x46f45a JE	46f465

  (618) 0x46f45c INC	%RBX

  (618) 0x46f45f INCQ	(%R14)

  (618) 0x46f462 MOV	%R15,(%R11)

  (618) 0x46f465 ADD	$0x8,%R13

  (618) 0x46f469 MOV	(%R13),%RDX

  (618) 0x46f46d LEA	(%RSI,%RDX,8),%R11

  (618) 0x46f471 CMP	(%R11),%R15

  (618) 0x46f474 JE	46f47f

  (618) 0x46f476 INC	%RBX

  (618) 0x46f479 INCQ	(%R14)

  (618) 0x46f47c MOV	%R15,(%R11)

  (618) 0x46f47f ADD	$0x8,%R13

  (618) 0x46f483 CMP	%R13,-0x60(%RBP)

  (618) 0x46f487 JE	46f567

  (618) 0x46f48d VMOVQ	%XMM1,%R11

    (620) 0x46f492 MOV	(%R13),%RDX

    (620) 0x46f496 LEA	(%RSI,%RDX,8),%RDX

    (620) 0x46f49a CMP	(%RDX),%R15

    (620) 0x46f49d JE	46f4a8

    (620) 0x46f49f INC	%RBX

    (620) 0x46f4a2 INCQ	(%R14)

    (620) 0x46f4a5 MOV	%R15,(%RDX)

    (620) 0x46f4a8 LEA	0x8(%R13),%RDX

    (620) 0x46f4ac MOV	0x8(%R13),%R13

    (620) 0x46f4b0 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f4b4 CMP	(%R13),%R15

    (620) 0x46f4b8 JE	46f4c4

    (620) 0x46f4ba INC	%RBX

    (620) 0x46f4bd INCQ	(%R14)

    (620) 0x46f4c0 MOV	%R15,(%R13)

    (620) 0x46f4c4 MOV	0x8(%RDX),%R13

    (620) 0x46f4c8 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f4cc CMP	(%R13),%R15

    (620) 0x46f4d0 JE	46f4dc

    (620) 0x46f4d2 INC	%RBX

    (620) 0x46f4d5 INCQ	(%R14)

    (620) 0x46f4d8 MOV	%R15,(%R13)

    (620) 0x46f4dc MOV	0x10(%RDX),%R13

    (620) 0x46f4e0 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f4e4 CMP	(%R13),%R15

    (620) 0x46f4e8 JE	46f4f4

    (620) 0x46f4ea INC	%RBX

    (620) 0x46f4ed INCQ	(%R14)

    (620) 0x46f4f0 MOV	%R15,(%R13)

    (620) 0x46f4f4 MOV	0x18(%RDX),%R13

    (620) 0x46f4f8 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f4fc CMP	(%R13),%R15

    (620) 0x46f500 JE	46f50c

    (620) 0x46f502 INC	%RBX

    (620) 0x46f505 INCQ	(%R14)

    (620) 0x46f508 MOV	%R15,(%R13)

    (620) 0x46f50c MOV	0x20(%RDX),%R13

    (620) 0x46f510 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f514 CMP	(%R13),%R15

    (620) 0x46f518 JE	46f524

    (620) 0x46f51a INC	%RBX

    (620) 0x46f51d INCQ	(%R14)

    (620) 0x46f520 MOV	%R15,(%R13)

    (620) 0x46f524 MOV	0x28(%RDX),%R13

    (620) 0x46f528 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f52c CMP	(%R13),%R15

    (620) 0x46f530 JE	46f53c

    (620) 0x46f532 INC	%RBX

    (620) 0x46f535 INCQ	(%R14)

    (620) 0x46f538 MOV	%R15,(%R13)

    (620) 0x46f53c MOV	0x30(%RDX),%R13

    (620) 0x46f540 LEA	(%RSI,%R13,8),%R13

    (620) 0x46f544 CMP	(%R13),%R15

    (620) 0x46f548 JE	46f554

    (620) 0x46f54a INC	%RBX

    (620) 0x46f54d INCQ	(%R14)

    (620) 0x46f550 MOV	%R15,(%R13)

    (620) 0x46f554 LEA	0x38(%RDX),%R13

    (620) 0x46f558 CMP	%R13,-0x60(%RBP)

    (620) 0x46f55c JNE	46f492

  (618) 0x46f562 VMOVQ	%R11,%XMM1

  (618) 0x46f567 MOV	-0x68(%RBP),%R11

  (618) 0x46f56b VMOVQ	%XMM4,%RDX

  (618) 0x46f570 MOV	(%R11,%R8,1),%R13

  (618) 0x46f574 MOV	-0x48(%RBP),%R8

  (618) 0x46f578 MOV	(%R8,%RDX,1),%R8

  (618) 0x46f57c ADD	%R13,%R8

  (618) 0x46f57f CMP	%R8,%R13

  (618) 0x46f582 JGE	46f7a4

  (618) 0x46f588 MOV	-0x78(%RBP),%RDX

  (618) 0x46f58c VMOVQ	%XMM6,%R11

  (618) 0x46f591 MOV	-0x8(%RDX,%R11,1),%RDX

  (618) 0x46f596 LEA	(%RDX,%R8,8),%R8

  (618) 0x46f59a LEA	(%RDX,%R13,8),%R13

  (618) 0x46f59e MOV	%R8,%R11

  (618) 0x46f5a1 SUB	%R13,%R11

  (618) 0x46f5a4 SUB	$0x8,%R11

  (618) 0x46f5a8 SHR	$0x3,%R11

  (618) 0x46f5ac INC	%R11

  (618) 0x46f5af AND	$0x7,%R11D

  (618) 0x46f5b3 JE	46f6cb

  (618) 0x46f5b9 CMP	$0x1,%R11

  (618) 0x46f5bd JE	46f6a3

  (618) 0x46f5c3 CMP	$0x2,%R11

  (618) 0x46f5c7 JE	46f684

  (618) 0x46f5cd CMP	$0x3,%R11

  (618) 0x46f5d1 JE	46f665

  (618) 0x46f5d7 CMP	$0x4,%R11

  (618) 0x46f5db JE	46f646

  (618) 0x46f5dd CMP	$0x5,%R11

  (618) 0x46f5e1 JE	46f627

  (618) 0x46f5e3 CMP	$0x6,%R11

  (618) 0x46f5e7 JE	46f608

  (618) 0x46f5e9 MOV	(%R13),%RDX

  (618) 0x46f5ed LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f5f1 CMP	(%RDX),%R15

  (618) 0x46f5f4 JE	46f604

  (618) 0x46f5f6 VMOVQ	%XMM1,%R11

  (618) 0x46f5fb INC	%RCX

  (618) 0x46f5fe INCQ	(%R11)

  (618) 0x46f601 MOV	%R15,(%RDX)

  (618) 0x46f604 ADD	$0x8,%R13

  (618) 0x46f608 MOV	(%R13),%RDX

  (618) 0x46f60c LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f610 CMP	(%RDX),%R15

  (618) 0x46f613 JE	46f623

  (618) 0x46f615 VMOVQ	%XMM1,%R11

  (618) 0x46f61a INC	%RCX

  (618) 0x46f61d INCQ	(%R11)

  (618) 0x46f620 MOV	%R15,(%RDX)

  (618) 0x46f623 ADD	$0x8,%R13

  (618) 0x46f627 MOV	(%R13),%RDX

  (618) 0x46f62b LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f62f CMP	(%RDX),%R15

  (618) 0x46f632 JE	46f642

  (618) 0x46f634 VMOVQ	%XMM1,%R11

  (618) 0x46f639 INC	%RCX

  (618) 0x46f63c INCQ	(%R11)

  (618) 0x46f63f MOV	%R15,(%RDX)

  (618) 0x46f642 ADD	$0x8,%R13

  (618) 0x46f646 MOV	(%R13),%RDX

  (618) 0x46f64a LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f64e CMP	(%RDX),%R15

  (618) 0x46f651 JE	46f661

  (618) 0x46f653 VMOVQ	%XMM1,%R11

  (618) 0x46f658 INC	%RCX

  (618) 0x46f65b INCQ	(%R11)

  (618) 0x46f65e MOV	%R15,(%RDX)

  (618) 0x46f661 ADD	$0x8,%R13

  (618) 0x46f665 MOV	(%R13),%RDX

  (618) 0x46f669 LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f66d CMP	(%RDX),%R15

  (618) 0x46f670 JE	46f680

  (618) 0x46f672 VMOVQ	%XMM1,%R11

  (618) 0x46f677 INC	%RCX

  (618) 0x46f67a INCQ	(%R11)

  (618) 0x46f67d MOV	%R15,(%RDX)

  (618) 0x46f680 ADD	$0x8,%R13

  (618) 0x46f684 MOV	(%R13),%RDX

  (618) 0x46f688 LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f68c CMP	(%RDX),%R15

  (618) 0x46f68f JE	46f69f

  (618) 0x46f691 VMOVQ	%XMM1,%R11

  (618) 0x46f696 INC	%RCX

  (618) 0x46f699 INCQ	(%R11)

  (618) 0x46f69c MOV	%R15,(%RDX)

  (618) 0x46f69f ADD	$0x8,%R13

  (618) 0x46f6a3 MOV	(%R13),%RDX

  (618) 0x46f6a7 LEA	(%R12,%RDX,8),%RDX

  (618) 0x46f6ab CMP	(%RDX),%R15

  (618) 0x46f6ae JE	46f6be

  (618) 0x46f6b0 VMOVQ	%XMM1,%R11

  (618) 0x46f6b5 INC	%RCX

  (618) 0x46f6b8 INCQ	(%R11)

  (618) 0x46f6bb MOV	%R15,(%RDX)

  (618) 0x46f6be ADD	$0x8,%R13

  (618) 0x46f6c2 CMP	%R8,%R13

  (618) 0x46f6c5 JE	46f7a4

  (618) 0x46f6cb VMOVQ	%XMM1,%R11

    (619) 0x46f6d0 MOV	(%R13),%RDX

    (619) 0x46f6d4 LEA	(%R12,%RDX,8),%RDX

    (619) 0x46f6d8 CMP	(%RDX),%R15

    (619) 0x46f6db JE	46f6e6

    (619) 0x46f6dd INC	%RCX

    (619) 0x46f6e0 INCQ	(%R11)

    (619) 0x46f6e3 MOV	%R15,(%RDX)

    (619) 0x46f6e6 LEA	0x8(%R13),%RDX

    (619) 0x46f6ea MOV	0x8(%R13),%R13

    (619) 0x46f6ee LEA	(%R12,%R13,8),%R13

    (619) 0x46f6f2 CMP	(%R13),%R15

    (619) 0x46f6f6 JE	46f702

    (619) 0x46f6f8 INC	%RCX

    (619) 0x46f6fb INCQ	(%R11)

    (619) 0x46f6fe MOV	%R15,(%R13)

    (619) 0x46f702 MOV	0x8(%RDX),%R13

    (619) 0x46f706 LEA	(%R12,%R13,8),%R13

    (619) 0x46f70a CMP	(%R13),%R15

    (619) 0x46f70e JE	46f71a

    (619) 0x46f710 INC	%RCX

    (619) 0x46f713 INCQ	(%R11)

    (619) 0x46f716 MOV	%R15,(%R13)

    (619) 0x46f71a MOV	0x10(%RDX),%R13

    (619) 0x46f71e LEA	(%R12,%R13,8),%R13

    (619) 0x46f722 CMP	(%R13),%R15

    (619) 0x46f726 JE	46f732

    (619) 0x46f728 INC	%RCX

    (619) 0x46f72b INCQ	(%R11)

    (619) 0x46f72e MOV	%R15,(%R13)

    (619) 0x46f732 MOV	0x18(%RDX),%R13

    (619) 0x46f736 LEA	(%R12,%R13,8),%R13

    (619) 0x46f73a CMP	(%R13),%R15

    (619) 0x46f73e JE	46f74a

    (619) 0x46f740 INC	%RCX

    (619) 0x46f743 INCQ	(%R11)

    (619) 0x46f746 MOV	%R15,(%R13)

    (619) 0x46f74a MOV	0x20(%RDX),%R13

    (619) 0x46f74e LEA	(%R12,%R13,8),%R13

    (619) 0x46f752 CMP	(%R13),%R15

    (619) 0x46f756 JE	46f762

    (619) 0x46f758 INC	%RCX

    (619) 0x46f75b INCQ	(%R11)

    (619) 0x46f75e MOV	%R15,(%R13)

    (619) 0x46f762 MOV	0x28(%RDX),%R13

    (619) 0x46f766 LEA	(%R12,%R13,8),%R13

    (619) 0x46f76a CMP	(%R13),%R15

    (619) 0x46f76e JE	46f77a

    (619) 0x46f770 INC	%RCX

    (619) 0x46f773 INCQ	(%R11)

    (619) 0x46f776 MOV	%R15,(%R13)

    (619) 0x46f77a MOV	0x30(%RDX),%R13

    (619) 0x46f77e LEA	(%R12,%R13,8),%R13

    (619) 0x46f782 CMP	(%R13),%R15

    (619) 0x46f786 JE	46f792

    (619) 0x46f788 INC	%RCX

    (619) 0x46f78b INCQ	(%R11)

    (619) 0x46f78e MOV	%R15,(%R13)

    (619) 0x46f792 LEA	0x38(%RDX),%R13

    (619) 0x46f796 CMP	%R8,%R13

    (619) 0x46f799 JNE	46f6d0

  (618) 0x46f79f VMOVQ	%R11,%XMM1

  (618) 0x46f7a4 VMOVQ	%XMM7,%R8

  (618) 0x46f7a9 INC	%RAX

  (618) 0x46f7ac MOV	(%R8),%R13

  (618) 0x46f7af CMP	%R13,%RAX

  (618) 0x46f7b2 JL	46f32c

0x46f7b8 NOPL	(%RAX,%RAX,1)

0x46f7c0 MOV	%RCX,%RDX

0x46f7c3 MOV	%RBX,%RCX

0x46f7c6 MOV	%R12,%RBX

0x46f7c9 MOV	%RSI,%R12

0x46f7cc VMOVQ	%XMM3,%RSI

0x46f7d1 MOV	-0x88(%RBP),%R14

0x46f7d8 MOV	-0x90(%RBP),%RDI

0x46f7df MOV	-0x50(%RBP),%R8

0x46f7e3 MOV	%R14,%R11

0x46f7e6 MOV	(%R14,%RSI,1),%RAX

0x46f7ea MOV	-0x48(%RBP),%RSI

0x46f7ee ADD	%RDI,%R8

0x46f7f1 ADD	%RDI,%R11

0x46f7f4 VMOVQ	%R8,%XMM2

0x46f7f9 MOV	(%R11),%R13

0x46f7fc VMOVQ	%R11,%XMM11

0x46f801 LEA	(%RSI,%RDI,1),%R14

0x46f805 CMP	%R13,%RAX

0x46f808 JGE	46fabb

0x46f80e MOV	%R12,%R8

0x46f811 MOV	-0x98(%RBP),%RDI

0x46f818 MOV	%RCX,%R12

0x46f81b VMOVQ	%R10,%XMM10

0x46f820 MOV	-0xa0(%RBP),%RCX

0x46f827 VMOVDQA	%XMM2,%XMM12

0x46f82b MOV	%R14,-0x60(%RBP)

0x46f82f JMP	46f84c

  (616) 0x46f840 INC	%RAX

  (616) 0x46f843 CMP	%R13,%RAX

  (616) 0x46f846 JGE	46fab0

  (616) 0x46f84c MOV	(%RCX,%RAX,8),%R10

  (616) 0x46f850 LEA	(,%R10,8),%R11

  (616) 0x46f858 CMP	%R9,(%RDI,%R10,8)

  (616) 0x46f85c JNE	46f840

  (616) 0x46f85e MOV	-0xb0(%RBP),%RSI

  (616) 0x46f865 MOV	-0xa8(%RBP),%R14

  (616) 0x46f86c MOV	(%RSI,%R11,1),%RSI

  (616) 0x46f870 MOV	0x8(%R14,%R11,1),%R14

  (616) 0x46f875 ADD	%RSI,%R14

  (616) 0x46f878 CMP	%R14,%RSI

  (616) 0x46f87b JGE	46f840

  (616) 0x46f87d MOV	-0xb8(%RBP),%R13

  (616) 0x46f884 VMOVQ	%XMM6,%R10

  (616) 0x46f889 MOV	(%R13,%R10,1),%R11

  (616) 0x46f88e LEA	(%R11,%R14,8),%R14

  (616) 0x46f892 LEA	(%R11,%RSI,8),%RSI

  (616) 0x46f896 MOV	%R14,%R13

  (616) 0x46f899 SUB	%RSI,%R13

  (616) 0x46f89c SUB	$0x8,%R13

  (616) 0x46f8a0 SHR	$0x3,%R13

  (616) 0x46f8a4 INC	%R13

  (616) 0x46f8a7 AND	$0x3,%R13D

  (616) 0x46f8ab JE	46f93b

  (616) 0x46f8b1 CMP	$0x1,%R13

  (616) 0x46f8b5 JE	46f90a

  (616) 0x46f8b7 CMP	$0x2,%R13

  (616) 0x46f8bb JE	46f8e4

  (616) 0x46f8bd MOV	(%RSI),%R10

  (616) 0x46f8c0 TEST	%R10,%R10

  (616) 0x46f8c3 JS	46fc80

  (616) 0x46f8c9 LEA	(%RBX,%R10,8),%R11

  (616) 0x46f8cd CMP	(%R11),%R15

  (616) 0x46f8d0 JE	46f8e0

  (616) 0x46f8d2 MOV	-0x60(%RBP),%R13

  (616) 0x46f8d6 INC	%RDX

  (616) 0x46f8d9 INCQ	(%R13)

  (616) 0x46f8dd MOV	%R15,(%R11)

  (616) 0x46f8e0 ADD	$0x8,%RSI

  (616) 0x46f8e4 MOV	(%RSI),%R13

  (616) 0x46f8e7 TEST	%R13,%R13

  (616) 0x46f8ea JS	46fc50

  (616) 0x46f8f0 LEA	(%RBX,%R13,8),%R11

  (616) 0x46f8f4 CMP	(%R11),%R15

  (616) 0x46f8f7 JE	46f906

  (616) 0x46f8f9 MOV	-0x60(%RBP),%R10

  (616) 0x46f8fd INC	%RDX

  (616) 0x46f900 INCQ	(%R10)

  (616) 0x46f903 MOV	%R15,(%R11)

  (616) 0x46f906 ADD	$0x8,%RSI

  (616) 0x46f90a MOV	(%RSI),%R10

  (616) 0x46f90d TEST	%R10,%R10

  (616) 0x46f910 JS	46fc20

  (616) 0x46f916 LEA	(%RBX,%R10,8),%R13

  (616) 0x46f91a CMP	(%R13),%R15

  (616) 0x46f91e JE	46f92e

  (616) 0x46f920 MOV	-0x60(%RBP),%R11

  (616) 0x46f924 INC	%RDX

  (616) 0x46f927 INCQ	(%R11)

  (616) 0x46f92a MOV	%R15,(%R13)

  (616) 0x46f92e ADD	$0x8,%RSI

  (616) 0x46f932 CMP	%R14,%RSI

  (616) 0x46f935 JE	46fa9c

  (616) 0x46f93b MOV	%RAX,-0x90(%RBP)

  (616) 0x46f942 MOV	-0x60(%RBP),%R11

  (616) 0x46f946 MOV	%R14,%RAX

  (616) 0x46f949 VMOVQ	%XMM10,%R10

  (616) 0x46f94e VMOVQ	%XMM12,%R14

  (616) 0x46f953 JMP	46f9e2

    (617) 0x46f960 LEA	(%RBX,%R13,8),%R13

    (617) 0x46f964 CMP	(%R13),%R15

    (617) 0x46f968 JE	46f974

    (617) 0x46f96a INC	%RDX

    (617) 0x46f96d INCQ	(%R11)

    (617) 0x46f970 MOV	%R15,(%R13)

    (617) 0x46f974 LEA	0x8(%RSI),%R13

    (617) 0x46f978 MOV	0x8(%RSI),%RSI

    (617) 0x46f97c TEST	%RSI,%RSI

    (617) 0x46f97f JS	46fa1a

    (617) 0x46f985 LEA	(%RBX,%RSI,8),%RSI

    (617) 0x46f989 CMP	(%RSI),%R15

    (617) 0x46f98c JE	46f997

    (617) 0x46f98e INC	%RDX

    (617) 0x46f991 INCQ	(%R11)

    (617) 0x46f994 MOV	%R15,(%RSI)

    (617) 0x46f997 MOV	0x8(%R13),%RSI

    (617) 0x46f99b TEST	%RSI,%RSI

    (617) 0x46f99e JS	46fa40

    (617) 0x46f9a4 LEA	(%RBX,%RSI,8),%RSI

    (617) 0x46f9a8 CMP	(%RSI),%R15

    (617) 0x46f9ab JE	46f9b6

    (617) 0x46f9ad INC	%RDX

    (617) 0x46f9b0 INCQ	(%R11)

    (617) 0x46f9b3 MOV	%R15,(%RSI)

    (617) 0x46f9b6 MOV	0x10(%R13),%RSI

    (617) 0x46f9ba TEST	%RSI,%RSI

    (617) 0x46f9bd JS	46fa66

    (617) 0x46f9c3 LEA	(%RBX,%RSI,8),%RSI

    (617) 0x46f9c7 CMP	(%RSI),%R15

    (617) 0x46f9ca JE	46f9d5

    (617) 0x46f9cc INC	%RDX

    (617) 0x46f9cf INCQ	(%R11)

    (617) 0x46f9d2 MOV	%R15,(%RSI)

    (617) 0x46f9d5 LEA	0x18(%R13),%RSI

    (617) 0x46f9d9 CMP	%RAX,%RSI

    (617) 0x46f9dc JE	46fa8c

    (617) 0x46f9e2 MOV	(%RSI),%R13

    (617) 0x46f9e5 TEST	%R13,%R13

    (617) 0x46f9e8 JNS	46f960

    (617) 0x46f9ee NOT	%R13

    (617) 0x46f9f1 LEA	(%R8,%R13,8),%R13

    (617) 0x46f9f5 CMP	(%R13),%R15

    (617) 0x46f9f9 JE	46f974

    (617) 0x46f9ff INCQ	(%R14)

    (617) 0x46fa02 MOV	%R15,(%R13)

    (617) 0x46fa06 LEA	0x8(%RSI),%R13

    (617) 0x46fa0a MOV	0x8(%RSI),%RSI

    (617) 0x46fa0e INC	%R12

    (617) 0x46fa11 TEST	%RSI,%RSI

    (617) 0x46fa14 JNS	46f985

    (617) 0x46fa1a NOT	%RSI

    (617) 0x46fa1d LEA	(%R8,%RSI,8),%RSI

    (617) 0x46fa21 CMP	(%RSI),%R15

    (617) 0x46fa24 JE	46f997

    (617) 0x46fa2a INCQ	(%R14)

    (617) 0x46fa2d MOV	%R15,(%RSI)

    (617) 0x46fa30 MOV	0x8(%R13),%RSI

    (617) 0x46fa34 INC	%R12

    (617) 0x46fa37 TEST	%RSI,%RSI

    (617) 0x46fa3a JNS	46f9a4

    (617) 0x46fa40 NOT	%RSI

    (617) 0x46fa43 LEA	(%R8,%RSI,8),%RSI

    (617) 0x46fa47 CMP	(%RSI),%R15

    (617) 0x46fa4a JE	46f9b6

    (617) 0x46fa50 INCQ	(%R14)

    (617) 0x46fa53 MOV	%R15,(%RSI)

    (617) 0x46fa56 MOV	0x10(%R13),%RSI

    (617) 0x46fa5a INC	%R12

    (617) 0x46fa5d TEST	%RSI,%RSI

    (617) 0x46fa60 JNS	46f9c3

    (617) 0x46fa66 NOT	%RSI

    (617) 0x46fa69 LEA	(%R8,%RSI,8),%RSI

    (617) 0x46fa6d CMP	(%RSI),%R15

    (617) 0x46fa70 JE	46f9d5

    (617) 0x46fa76 INCQ	(%R14)

    (617) 0x46fa79 MOV	%R15,(%RSI)

    (617) 0x46fa7c LEA	0x18(%R13),%RSI

    (617) 0x46fa80 INC	%R12

    (617) 0x46fa83 CMP	%RAX,%RSI

    (617) 0x46fa86 JNE	46f9e2

  (616) 0x46fa8c MOV	-0x90(%RBP),%RAX

  (616) 0x46fa93 VMOVQ	%R10,%XMM10

  (616) 0x46fa98 MOV	%R11,-0x60(%RBP)

  (616) 0x46fa9c VMOVQ	%XMM11,%R10

  (616) 0x46faa1 INC	%RAX

  (616) 0x46faa4 MOV	(%R10),%R13

  (616) 0x46faa7 CMP	%R13,%RAX

  (616) 0x46faaa JL	46f84c

0x46fab0 MOV	%R12,%RCX

0x46fab3 VMOVQ	%XMM10,%R10

0x46fab8 MOV	%R8,%R12

0x46fabb INCQ	-0x40(%RBP)

0x46fabf MOV	-0x40(%RBP),%R14

0x46fac3 CMP	%R14,-0xc8(%RBP)

0x46faca JG	46f290

  (616) 0x46fc20 NOT	%R10

  (616) 0x46fc23 LEA	(%R8,%R10,8),%R10

  (616) 0x46fc27 CMP	(%R10),%R15

  (616) 0x46fc2a JE	46f92e

  (616) 0x46fc30 VMOVQ	%XMM12,%R13

  (616) 0x46fc35 INC	%R12

  (616) 0x46fc38 INCQ	(%R13)

  (616) 0x46fc3c MOV	%R15,(%R10)

  (616) 0x46fc3f JMP	46f92e

  (616) 0x46fc50 NOT	%R13

  (616) 0x46fc53 LEA	(%R8,%R13,8),%R13

  (616) 0x46fc57 CMP	(%R13),%R15

  (616) 0x46fc5b JE	46f906

  (616) 0x46fc61 VMOVQ	%XMM12,%R11

  (616) 0x46fc66 INC	%R12

  (616) 0x46fc69 INCQ	(%R11)

  (616) 0x46fc6c MOV	%R15,(%R13)

  (616) 0x46fc70 JMP	46f906

  (616) 0x46fc80 NOT	%R10

  (616) 0x46fc83 LEA	(%R8,%R10,8),%R11

  (616) 0x46fc87 CMP	(%R11),%R15

  (616) 0x46fc8a JE	46f8e0

  (616) 0x46fc90 VMOVQ	%XMM12,%R10

  (616) 0x46fc95 INC	%R12

  (616) 0x46fc98 INCQ	(%R10)

  (616) 0x46fc9b MOV	%R15,(%R11)

  (616) 0x46fc9e JMP	46f8e0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►97.17+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.83+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:957-957,par_multi_interp.c:969-969,par_multi_interp.c:976-976,par_multi_interp.c:991-991,par_multi_interp.c:998-998
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.88
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.88
CQA cycles if fully vectorized	0.98
Front-end cycles	7.88
P0 cycles	3.33
P1 cycles	3.17
P2 cycles	6.00
P3 cycles	3.17
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	28.00
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.70
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	4.76
Vector-efficiency ratio all	12.96
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.10

Metric	Value
CQA speedup if no scalar integer	1.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:957-957,par_multi_interp.c:969-969,par_multi_interp.c:976-976,par_multi_interp.c:991-991,par_multi_interp.c:998-998
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.88
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.88
CQA cycles if fully vectorized	0.98
Front-end cycles	7.88
P0 cycles	3.33
P1 cycles	3.17
P2 cycles	6.00
P3 cycles	3.17
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	28.00
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.70
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	4.76
Vector-efficiency ratio all	12.96
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,957,969,976,991,998.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.88 to 6.00 cycles (1.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.88 to 0.98 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 176 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	64
nb uops	63
loop length	279
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.17	6.00	3.17	3.17	3.17	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.33	3.17	6.00	3.17	3.17	3.17	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Dispatch	6.75
Overall L1	7.88

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.88 cycles. At this rate:

8% of peak load performance is reached (22.35 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.88 to 6.75 cycles (1.17x speedup).

ASM code

In the binary file, the address of the loop is: 46f290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xc0(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R14,%R13,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (,%R15,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R8,%RSI,1),%R14	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV %RCX,(%R11,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,(%RDI,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %R14,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%RSI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%R11,1),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
ADD %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46f7d1 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %RSI,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R8,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RBX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 46f32c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x31c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R8,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%R11),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %R11,%XMM11	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RSI,%RDI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46fabb <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xaab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %R10,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R14,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 46f84c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x83c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM10,%R10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
INCQ -0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R14,-0xc8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 46f290 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x280>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.88 to 6.00 cycles (1.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 176 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	64
nb uops	63
loop length	279
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.17	6.00	3.17	3.17	3.17	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.33	3.17	6.00	3.17	3.17	3.17	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Dispatch	6.75
Overall L1	7.88

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.88 cycles. At this rate:

8% of peak load performance is reached (22.35 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46f290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xc0(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R14,%R13,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (,%R15,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R8,%RSI,1),%R14	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV %RCX,(%R11,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,(%RDI,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %R14,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%RSI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%R11,1),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
ADD %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46f7d1 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %RSI,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R8,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RBX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 46f32c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x31c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R8,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV (%R11),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %R11,%XMM11	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RSI,%RDI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46fabb <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xaab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %R10,%XMM10	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R14,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 46f84c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x83c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM10,%R10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
INCQ -0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R14,-0xc8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 46f290 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x280>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code