OV - exec - Loop 607

	Loop Id: 607	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.05%

0x46fe70 MOV	-0xc0(%RBP),%R13

0x46fe77 MOV	-0x58(%RBP),%R14

0x46fe7b MOV	-0xd0(%RBP),%R10

0x46fe82 MOV	(%R13,%R14,8),%R14

0x46fe87 LEA	(,%R14,8),%RDI

0x46fe8f LEA	0x8(%R10,%RDI,1),%RAX

0x46fe94 MOV	(%R10,%RDI,1),%RCX

0x46fe98 LEA	0x8(%RDI),%R13

0x46fe9c MOV	(%RAX),%R9

0x46fe9f VMOVQ	%RAX,%XMM13

0x46fea4 MOV	%R14,%RAX

0x46fea7 NOT	%RAX

0x46feaa CMP	%R9,%RCX

0x46fead JGE	470269

0x46feb3 VMOVQ	%RDI,%XMM14

0x46feb8 MOV	-0x90(%RBP),%RDI

0x46febf MOV	%R8,%R11

0x46fec2 MOV	%R14,-0xd8(%RBP)

0x46fec9 MOV	-0x78(%RBP),%R10

0x46fecd MOV	-0x80(%RBP),%R15

0x46fed1 VMOVQ	%XMM6,%R14

0x46fed6 MOV	%RDX,%R8

0x46fed9 MOV	%R13,-0xe0(%RBP)

0x46fee0 MOV	%RDI,-0x40(%RBP)

0x46fee4 MOV	%R9,%RDI

0x46fee7 JMP	46ff0c

  (610) 0x46ff00 INC	%RCX

  (610) 0x46ff03 CMP	%RDI,%RCX

  (610) 0x46ff06 JGE	470250

  (610) 0x46ff0c MOV	(%R14,%RCX,8),%RDX

  (610) 0x46ff10 MOV	-0x38(%RBP),%R13

  (610) 0x46ff14 LEA	(,%RDX,8),%R9

  (610) 0x46ff1c CMP	%R11,(%R13,%RDX,8)

  (610) 0x46ff21 JNE	46ff00

  (610) 0x46ff23 MOV	-0x70(%RBP),%RDI

  (610) 0x46ff27 LEA	0x8(%R9),%R13

  (610) 0x46ff2b VMOVQ	%R13,%XMM15

  (610) 0x46ff30 MOV	(%RDI,%R9,1),%RDX

  (610) 0x46ff34 MOV	-0x50(%RBP),%RDI

  (610) 0x46ff38 MOV	0x8(%RDI,%R9,1),%RDI

  (610) 0x46ff3d ADD	%RDX,%RDI

  (610) 0x46ff40 CMP	%RDI,%RDX

  (610) 0x46ff43 JGE	4700bf

  (610) 0x46ff49 MOV	-0x8(%R15,%R12,1),%R13

  (610) 0x46ff4e LEA	(%R13,%RDX,8),%RDX

  (610) 0x46ff53 LEA	(%R13,%RDI,8),%R13

  (610) 0x46ff58 MOV	%R13,-0x60(%RBP)

  (610) 0x46ff5c SUB	%RDX,%R13

  (610) 0x46ff5f SUB	$0x8,%R13

  (610) 0x46ff63 SHR	$0x3,%R13

  (610) 0x46ff67 INC	%R13

  (610) 0x46ff6a AND	$0x3,%R13D

  (610) 0x46ff6e JE	47000b

  (610) 0x46ff74 CMP	$0x1,%R13

  (610) 0x46ff78 JE	46ffd6

  (610) 0x46ff7a CMP	$0x2,%R13

  (610) 0x46ff7e JE	46ffab

  (610) 0x46ff80 VMOVQ	(%RDX),%XMM0

  (610) 0x46ff84 MOV	-0x40(%RBP),%RDI

  (610) 0x46ff88 VMOVQ	%XMM0,%R13

  (610) 0x46ff8d LEA	(%RDI,%R13,8),%R13

  (610) 0x46ff91 CMP	%RAX,(%R13)

  (610) 0x46ff95 JE	46ffa7

  (610) 0x46ff97 MOV	(%R15,%R12,1),%RDI

  (610) 0x46ff9b VMOVQ	%XMM0,(%RDI,%RSI,8)

  (610) 0x46ffa0 INC	%RSI

  (610) 0x46ffa3 MOV	%RAX,(%R13)

  (610) 0x46ffa7 ADD	$0x8,%RDX

  (610) 0x46ffab VMOVQ	(%RDX),%XMM3

  (610) 0x46ffaf MOV	-0x40(%RBP),%RDI

  (610) 0x46ffb3 VMOVQ	%XMM3,%R13

  (610) 0x46ffb8 LEA	(%RDI,%R13,8),%R13

  (610) 0x46ffbc CMP	%RAX,(%R13)

  (610) 0x46ffc0 JE	46ffd2

  (610) 0x46ffc2 MOV	(%R15,%R12,1),%RDI

  (610) 0x46ffc6 VMOVQ	%XMM3,(%RDI,%RSI,8)

  (610) 0x46ffcb INC	%RSI

  (610) 0x46ffce MOV	%RAX,(%R13)

  (610) 0x46ffd2 ADD	$0x8,%RDX

  (610) 0x46ffd6 VMOVQ	(%RDX),%XMM5

  (610) 0x46ffda MOV	-0x40(%RBP),%RDI

  (610) 0x46ffde VMOVQ	%XMM5,%R13

  (610) 0x46ffe3 LEA	(%RDI,%R13,8),%R13

  (610) 0x46ffe7 CMP	%RAX,(%R13)

  (610) 0x46ffeb JE	46fffd

  (610) 0x46ffed MOV	(%R15,%R12,1),%RDI

  (610) 0x46fff1 VMOVQ	%XMM5,(%RDI,%RSI,8)

  (610) 0x46fff6 INC	%RSI

  (610) 0x46fff9 MOV	%RAX,(%R13)

  (610) 0x46fffd ADD	$0x8,%RDX

  (610) 0x470001 CMP	%RDX,-0x60(%RBP)

  (610) 0x470005 JE	4700bf

  (610) 0x47000b MOV	%R11,-0xf0(%RBP)

  (610) 0x470012 MOV	-0x40(%RBP),%R13

  (610) 0x470016 MOV	%R8,%R11

  (610) 0x470019 MOV	-0x60(%RBP),%R8

  (610) 0x47001d VMOVQ	%R9,%XMM2

  (610) 0x470022 MOV	%RCX,-0xe8(%RBP)

    (612) 0x470029 MOV	(%RDX),%RDI

    (612) 0x47002c LEA	(%R13,%RDI,8),%RCX

    (612) 0x470031 CMP	%RAX,(%RCX)

    (612) 0x470034 JE	470044

    (612) 0x470036 MOV	(%R15,%R12,1),%R9

    (612) 0x47003a MOV	%RDI,(%R9,%RSI,8)

    (612) 0x47003e INC	%RSI

    (612) 0x470041 MOV	%RAX,(%RCX)

    (612) 0x470044 MOV	0x8(%RDX),%RCX

    (612) 0x470048 LEA	0x8(%RDX),%RDI

    (612) 0x47004c LEA	(%R13,%RCX,8),%RDX

    (612) 0x470051 CMP	%RAX,(%RDX)

    (612) 0x470054 JE	470064

    (612) 0x470056 MOV	(%R15,%R12,1),%R9

    (612) 0x47005a MOV	%RCX,(%R9,%RSI,8)

    (612) 0x47005e INC	%RSI

    (612) 0x470061 MOV	%RAX,(%RDX)

    (612) 0x470064 MOV	0x8(%RDI),%RCX

    (612) 0x470068 LEA	(%R13,%RCX,8),%RDX

    (612) 0x47006d CMP	%RAX,(%RDX)

    (612) 0x470070 JE	470080

    (612) 0x470072 MOV	(%R15,%R12,1),%R9

    (612) 0x470076 MOV	%RCX,(%R9,%RSI,8)

    (612) 0x47007a INC	%RSI

    (612) 0x47007d MOV	%RAX,(%RDX)

    (612) 0x470080 MOV	0x10(%RDI),%RCX

    (612) 0x470084 LEA	(%R13,%RCX,8),%RDX

    (612) 0x470089 CMP	%RAX,(%RDX)

    (612) 0x47008c JE	47009c

    (612) 0x47008e MOV	(%R15,%R12,1),%R9

    (612) 0x470092 MOV	%RCX,(%R9,%RSI,8)

    (612) 0x470096 INC	%RSI

    (612) 0x470099 MOV	%RAX,(%RDX)

    (612) 0x47009c LEA	0x18(%RDI),%RDX

    (612) 0x4700a0 CMP	%RDX,%R8

    (612) 0x4700a3 JNE	470029

  (610) 0x4700a5 MOV	%R11,%R8

  (610) 0x4700a8 MOV	-0xe8(%RBP),%RCX

  (610) 0x4700af MOV	-0xf0(%RBP),%R11

  (610) 0x4700b6 VMOVQ	%XMM2,%R9

  (610) 0x4700bb MOV	%R13,-0x40(%RBP)

  (610) 0x4700bf MOV	-0x68(%RBP),%R13

  (610) 0x4700c3 MOV	-0x48(%RBP),%RDI

  (610) 0x4700c7 MOV	(%R13,%R9,1),%RDX

  (610) 0x4700cc VMOVQ	%XMM15,%R9

  (610) 0x4700d1 MOV	(%RDI,%R9,1),%R13

  (610) 0x4700d5 ADD	%RDX,%R13

  (610) 0x4700d8 CMP	%R13,%RDX

  (610) 0x4700db JGE	470232

  (610) 0x4700e1 MOV	-0x8(%R10,%R12,1),%RDI

  (610) 0x4700e6 LEA	(%RDI,%RDX,8),%RDX

  (610) 0x4700ea LEA	(%RDI,%R13,8),%RDI

  (610) 0x4700ee MOV	%RDI,%R9

  (610) 0x4700f1 SUB	%RDX,%R9

  (610) 0x4700f4 SUB	$0x8,%R9

  (610) 0x4700f8 SHR	$0x3,%R9

  (610) 0x4700fc INC	%R9

  (610) 0x4700ff AND	$0x3,%R9D

  (610) 0x470103 JE	470193

  (610) 0x470109 CMP	$0x1,%R9

  (610) 0x47010d JE	470163

  (610) 0x47010f CMP	$0x2,%R9

  (610) 0x470113 JE	47013c

  (610) 0x470115 VMOVQ	(%RDX),%XMM10

  (610) 0x470119 VMOVQ	%XMM10,%R13

  (610) 0x47011e LEA	(%RBX,%R13,8),%R9

  (610) 0x470122 CMP	%RAX,(%R9)

  (610) 0x470125 JE	470138

  (610) 0x470127 MOV	(%R10,%R12,1),%R13

  (610) 0x47012b VMOVQ	%XMM10,(%R13,%R8,8)

  (610) 0x470132 INC	%R8

  (610) 0x470135 MOV	%RAX,(%R9)

  (610) 0x470138 ADD	$0x8,%RDX

  (610) 0x47013c VMOVQ	(%RDX),%XMM11

  (610) 0x470140 VMOVQ	%XMM11,%R9

  (610) 0x470145 LEA	(%RBX,%R9,8),%R9

  (610) 0x470149 CMP	%RAX,(%R9)

  (610) 0x47014c JE	47015f

  (610) 0x47014e MOV	(%R10,%R12,1),%R13

  (610) 0x470152 VMOVQ	%XMM11,(%R13,%R8,8)

  (610) 0x470159 INC	%R8

  (610) 0x47015c MOV	%RAX,(%R9)

  (610) 0x47015f ADD	$0x8,%RDX

  (610) 0x470163 VMOVQ	(%RDX),%XMM12

  (610) 0x470167 VMOVQ	%XMM12,%R9

  (610) 0x47016c LEA	(%RBX,%R9,8),%R9

  (610) 0x470170 CMP	%RAX,(%R9)

  (610) 0x470173 JE	470186

  (610) 0x470175 MOV	(%R10,%R12,1),%R13

  (610) 0x470179 VMOVQ	%XMM12,(%R13,%R8,8)

  (610) 0x470180 INC	%R8

  (610) 0x470183 MOV	%RAX,(%R9)

  (610) 0x470186 ADD	$0x8,%RDX

  (610) 0x47018a CMP	%RDI,%RDX

  (610) 0x47018d JE	470232

  (610) 0x470193 MOV	-0x40(%RBP),%R13

  (610) 0x470197 MOV	%R11,-0xe8(%RBP)

  (610) 0x47019e MOV	%RCX,%R11

  (610) 0x4701a1 MOV	%RDI,%RCX

  (610) 0x4701a4 MOV	%RSI,-0x60(%RBP)

    (611) 0x4701a8 MOV	(%RDX),%R9

    (611) 0x4701ab LEA	(%RBX,%R9,8),%RDI

    (611) 0x4701af CMP	%RAX,(%RDI)

    (611) 0x4701b2 JE	4701c2

    (611) 0x4701b4 MOV	(%R10,%R12,1),%RSI

    (611) 0x4701b8 MOV	%R9,(%RSI,%R8,8)

    (611) 0x4701bc INC	%R8

    (611) 0x4701bf MOV	%RAX,(%RDI)

    (611) 0x4701c2 MOV	0x8(%RDX),%RDI

    (611) 0x4701c6 LEA	0x8(%RDX),%R9

    (611) 0x4701ca LEA	(%RBX,%RDI,8),%RDX

    (611) 0x4701ce CMP	%RAX,(%RDX)

    (611) 0x4701d1 JE	4701e1

    (611) 0x4701d3 MOV	(%R10,%R12,1),%RSI

    (611) 0x4701d7 MOV	%RDI,(%RSI,%R8,8)

    (611) 0x4701db INC	%R8

    (611) 0x4701de MOV	%RAX,(%RDX)

    (611) 0x4701e1 MOV	0x8(%R9),%RDI

    (611) 0x4701e5 LEA	(%RBX,%RDI,8),%RDX

    (611) 0x4701e9 CMP	%RAX,(%RDX)

    (611) 0x4701ec JE	4701fc

    (611) 0x4701ee MOV	(%R10,%R12,1),%RSI

    (611) 0x4701f2 MOV	%RDI,(%RSI,%R8,8)

    (611) 0x4701f6 INC	%R8

    (611) 0x4701f9 MOV	%RAX,(%RDX)

    (611) 0x4701fc MOV	0x10(%R9),%RDI

    (611) 0x470200 LEA	(%RBX,%RDI,8),%RDX

    (611) 0x470204 CMP	%RAX,(%RDX)

    (611) 0x470207 JE	470217

    (611) 0x470209 MOV	(%R10,%R12,1),%RSI

    (611) 0x47020d MOV	%RDI,(%RSI,%R8,8)

    (611) 0x470211 INC	%R8

    (611) 0x470214 MOV	%RAX,(%RDX)

    (611) 0x470217 LEA	0x18(%R9),%RDX

    (611) 0x47021b CMP	%RCX,%RDX

    (611) 0x47021e JNE	4701a8

  (610) 0x470220 MOV	%R11,%RCX

  (610) 0x470223 MOV	-0x60(%RBP),%RSI

  (610) 0x470227 MOV	-0xe8(%RBP),%R11

  (610) 0x47022e MOV	%R13,-0x40(%RBP)

  (610) 0x470232 VMOVQ	%XMM13,%R13

  (610) 0x470237 INC	%RCX

  (610) 0x47023a MOV	(%R13),%RDI

  (610) 0x47023e CMP	%RDI,%RCX

  (610) 0x470241 JL	46ff0c

0x470247 NOPW	(%RAX,%RAX,1)

0x470250 MOV	-0xd8(%RBP),%R14

0x470257 MOV	-0xe0(%RBP),%R13

0x47025e MOV	%R8,%RDX

0x470261 VMOVQ	%XMM14,%RDI

0x470266 MOV	%R11,%R8

0x470269 MOV	-0x88(%RBP),%R10

0x470270 LEA	(%R10,%R13,1),%R15

0x470274 MOV	(%R10,%RDI,1),%RAX

0x470278 MOV	%R14,%RDI

0x47027b MOV	(%R15),%R11

0x47027e NOT	%RDI

0x470281 MOV	%R15,-0x40(%RBP)

0x470285 CMP	%RAX,%R11

0x470288 JLE	470560

0x47028e MOV	-0x98(%RBP),%R14

0x470295 MOV	-0xa0(%RBP),%R15

0x47029c MOV	%R11,%R9

0x47029f JMP	4702cc

  (608) 0x4702c0 INC	%RAX

  (608) 0x4702c3 CMP	%R9,%RAX

  (608) 0x4702c6 JGE	470560

  (608) 0x4702cc MOV	(%R15,%RAX,8),%RCX

  (608) 0x4702d0 LEA	(,%RCX,8),%R13

  (608) 0x4702d8 CMP	%R8,(%R14,%RCX,8)

  (608) 0x4702dc JNE	4702c0

  (608) 0x4702de MOV	-0xb0(%RBP),%R10

  (608) 0x4702e5 MOV	-0xa8(%RBP),%R11

  (608) 0x4702ec MOV	(%R10,%R13,1),%RCX

  (608) 0x4702f0 MOV	0x8(%R11,%R13,1),%R13

  (608) 0x4702f5 ADD	%RCX,%R13

  (608) 0x4702f8 CMP	%R13,%RCX

  (608) 0x4702fb JGE	4702c0

  (608) 0x4702fd MOV	-0xb8(%RBP),%R9

  (608) 0x470304 MOV	(%R9,%R12,1),%R10

  (608) 0x470308 LEA	(%R10,%R13,8),%R9

  (608) 0x47030c LEA	(%R10,%RCX,8),%RCX

  (608) 0x470310 MOV	%R9,%R11

  (608) 0x470313 SUB	%RCX,%R11

  (608) 0x470316 SUB	$0x8,%R11

  (608) 0x47031a SHR	$0x3,%R11

  (608) 0x47031e INC	%R11

  (608) 0x470321 AND	$0x3,%R11D

  (608) 0x470325 JE	4703d7

  (608) 0x47032b CMP	$0x1,%R11

  (608) 0x47032f JE	470398

  (608) 0x470331 CMP	$0x2,%R11

  (608) 0x470335 JE	47036d

  (608) 0x470337 MOV	(%RCX),%R13

  (608) 0x47033a TEST	%R13,%R13

  (608) 0x47033d JS	470680

  (608) 0x470343 LEA	(%RBX,%R13,8),%R10

  (608) 0x470347 VMOVQ	%R10,%XMM8

  (608) 0x47034c CMP	%RDI,(%R10)

  (608) 0x47034f JE	470369

  (608) 0x470351 MOV	-0x78(%RBP),%R11

  (608) 0x470355 MOV	(%R11,%R12,1),%R10

  (608) 0x470359 MOV	%R13,(%R10,%RDX,8)

  (608) 0x47035d VMOVQ	%XMM8,%R13

  (608) 0x470362 INC	%RDX

  (608) 0x470365 MOV	%RDI,(%R13)

  (608) 0x470369 ADD	$0x8,%RCX

  (608) 0x47036d MOV	(%RCX),%R13

  (608) 0x470370 TEST	%R13,%R13

  (608) 0x470373 JS	470640

  (608) 0x470379 LEA	(%RBX,%R13,8),%R10

  (608) 0x47037d CMP	%RDI,(%R10)

  (608) 0x470380 JE	470394

  (608) 0x470382 MOV	-0x78(%RBP),%R11

  (608) 0x470386 MOV	(%R11,%R12,1),%R11

  (608) 0x47038a MOV	%R13,(%R11,%RDX,8)

  (608) 0x47038e INC	%RDX

  (608) 0x470391 MOV	%RDI,(%R10)

  (608) 0x470394 ADD	$0x8,%RCX

  (608) 0x470398 MOV	(%RCX),%R13

  (608) 0x47039b TEST	%R13,%R13

  (608) 0x47039e JS	470600

  (608) 0x4703a4 LEA	(%RBX,%R13,8),%R10

  (608) 0x4703a8 VMOVQ	%R10,%XMM15

  (608) 0x4703ad CMP	%RDI,(%R10)

  (608) 0x4703b0 JE	4703ca

  (608) 0x4703b2 MOV	-0x78(%RBP),%R11

  (608) 0x4703b6 MOV	(%R11,%R12,1),%R10

  (608) 0x4703ba MOV	%R13,(%R10,%RDX,8)

  (608) 0x4703be VMOVQ	%XMM15,%R13

  (608) 0x4703c3 INC	%RDX

  (608) 0x4703c6 MOV	%RDI,(%R13)

  (608) 0x4703ca ADD	$0x8,%RCX

  (608) 0x4703ce CMP	%R9,%RCX

  (608) 0x4703d1 JE	470543

  (608) 0x4703d7 VMOVQ	%R14,%XMM7

  (608) 0x4703dc MOV	%RAX,-0x60(%RBP)

  (608) 0x4703e0 MOV	-0x78(%RBP),%R11

  (608) 0x4703e4 MOV	%R9,%RAX

  (608) 0x4703e7 MOV	-0x80(%RBP),%R14

  (608) 0x4703eb MOV	-0x90(%RBP),%R9

  (608) 0x4703f2 MOV	%R8,-0xd8(%RBP)

  (608) 0x4703f9 JMP	47046c

    (609) 0x470400 LEA	(%RBX,%RCX,8),%R10

    (609) 0x470404 CMP	%RDI,(%R10)

    (609) 0x470407 JE	470417

    (609) 0x470409 MOV	(%R11,%R12,1),%R8

    (609) 0x47040d MOV	%RCX,(%R8,%RDX,8)

    (609) 0x470411 INC	%RDX

    (609) 0x470414 MOV	%RDI,(%R10)

    (609) 0x470417 MOV	0x8(%R13),%RCX

    (609) 0x47041b TEST	%RCX,%RCX

    (609) 0x47041e JS	4704d1

    (609) 0x470424 LEA	(%RBX,%RCX,8),%R10

    (609) 0x470428 CMP	%RDI,(%R10)

    (609) 0x47042b JE	47043b

    (609) 0x47042d MOV	(%R11,%R12,1),%R8

    (609) 0x470431 MOV	%RCX,(%R8,%RDX,8)

    (609) 0x470435 INC	%RDX

    (609) 0x470438 MOV	%RDI,(%R10)

    (609) 0x47043b MOV	0x10(%R13),%RCX

    (609) 0x47043f TEST	%RCX,%RCX

    (609) 0x470442 JS	470502

    (609) 0x470448 LEA	(%RBX,%RCX,8),%R10

    (609) 0x47044c CMP	%RDI,(%R10)

    (609) 0x47044f JE	47045f

    (609) 0x470451 MOV	(%R11,%R12,1),%R8

    (609) 0x470455 MOV	%RCX,(%R8,%RDX,8)

    (609) 0x470459 INC	%RDX

    (609) 0x47045c MOV	%RDI,(%R10)

    (609) 0x47045f LEA	0x18(%R13),%RCX

    (609) 0x470463 CMP	%RAX,%RCX

    (609) 0x470466 JE	470533

    (609) 0x47046c MOV	(%RCX),%R13

    (609) 0x47046f TEST	%R13,%R13

    (609) 0x470472 JS	4705d0

    (609) 0x470478 LEA	(%RBX,%R13,8),%R10

    (609) 0x47047c CMP	%RDI,(%R10)

    (609) 0x47047f JE	47048f

    (609) 0x470481 MOV	(%R11,%R12,1),%R8

    (609) 0x470485 MOV	%R13,(%R8,%RDX,8)

    (609) 0x470489 INC	%RDX

    (609) 0x47048c MOV	%RDI,(%R10)

    (609) 0x47048f LEA	0x8(%RCX),%R13

    (609) 0x470493 MOV	0x8(%RCX),%RCX

    (609) 0x470497 TEST	%RCX,%RCX

    (609) 0x47049a JNS	470400

    (609) 0x4704a0 MOV	%RCX,%R10

    (609) 0x4704a3 NOT	%R10

    (609) 0x4704a6 LEA	(%R9,%R10,8),%R10

    (609) 0x4704aa CMP	%RDI,(%R10)

    (609) 0x4704ad JE	470417

    (609) 0x4704b3 MOV	(%R14,%R12,1),%R8

    (609) 0x4704b7 NOT	%RCX

    (609) 0x4704ba MOV	%RCX,(%R8,%RSI,8)

    (609) 0x4704be MOV	%RDI,(%R10)

    (609) 0x4704c1 MOV	0x8(%R13),%RCX

    (609) 0x4704c5 INC	%RSI

    (609) 0x4704c8 TEST	%RCX,%RCX

    (609) 0x4704cb JNS	470424

    (609) 0x4704d1 MOV	%RCX,%R10

    (609) 0x4704d4 NOT	%R10

    (609) 0x4704d7 LEA	(%R9,%R10,8),%R10

    (609) 0x4704db CMP	%RDI,(%R10)

    (609) 0x4704de JE	47043b

    (609) 0x4704e4 MOV	(%R14,%R12,1),%R8

    (609) 0x4704e8 NOT	%RCX

    (609) 0x4704eb MOV	%RCX,(%R8,%RSI,8)

    (609) 0x4704ef MOV	%RDI,(%R10)

    (609) 0x4704f2 MOV	0x10(%R13),%RCX

    (609) 0x4704f6 INC	%RSI

    (609) 0x4704f9 TEST	%RCX,%RCX

    (609) 0x4704fc JNS	470448

    (609) 0x470502 MOV	%RCX,%R10

    (609) 0x470505 NOT	%R10

    (609) 0x470508 LEA	(%R9,%R10,8),%R10

    (609) 0x47050c CMP	%RDI,(%R10)

    (609) 0x47050f JE	47045f

    (609) 0x470515 MOV	(%R14,%R12,1),%R8

    (609) 0x470519 NOT	%RCX

    (609) 0x47051c MOV	%RCX,(%R8,%RSI,8)

    (609) 0x470520 LEA	0x18(%R13),%RCX

    (609) 0x470524 INC	%RSI

    (609) 0x470527 MOV	%RDI,(%R10)

    (609) 0x47052a CMP	%RAX,%RCX

    (609) 0x47052d JNE	47046c

  (608) 0x470533 MOV	-0x60(%RBP),%RAX

  (608) 0x470537 MOV	-0xd8(%RBP),%R8

  (608) 0x47053e VMOVQ	%XMM7,%R14

  (608) 0x470543 MOV	-0x40(%RBP),%R11

  (608) 0x470547 INC	%RAX

  (608) 0x47054a MOV	(%R11),%R9

  (608) 0x47054d CMP	%R9,%RAX

  (608) 0x470550 JL	4702cc

0x470556 NOPW	%CS:(%RAX,%RAX,1)

0x470560 INCQ	-0x58(%RBP)

0x470564 MOV	-0x58(%RBP),%R13

0x470568 CMP	%R13,-0xc8(%RBP)

0x47056f JG	46fe70

    (609) 0x4705d0 MOV	%R13,%R10

    (609) 0x4705d3 NOT	%R10

    (609) 0x4705d6 LEA	(%R9,%R10,8),%R10

    (609) 0x4705da CMP	%RDI,(%R10)

    (609) 0x4705dd JE	47048f

    (609) 0x4705e3 MOV	(%R14,%R12,1),%R8

    (609) 0x4705e7 NOT	%R13

    (609) 0x4705ea MOV	%R13,(%R8,%RSI,8)

    (609) 0x4705ee INC	%RSI

    (609) 0x4705f1 MOV	%RDI,(%R10)

    (609) 0x4705f4 JMP	47048f

  (608) 0x470600 MOV	-0x90(%RBP),%R11

  (608) 0x470607 NOT	%R13

  (608) 0x47060a LEA	(%R11,%R13,8),%R10

  (608) 0x47060e VMOVQ	%R10,%XMM0

  (608) 0x470613 CMP	%RDI,(%R10)

  (608) 0x470616 JE	4703ca

  (608) 0x47061c MOV	-0x80(%RBP),%R11

  (608) 0x470620 MOV	(%R11,%R12,1),%R10

  (608) 0x470624 MOV	%R13,(%R10,%RSI,8)

  (608) 0x470628 VMOVQ	%XMM0,%R13

  (608) 0x47062d INC	%RSI

  (608) 0x470630 MOV	%RDI,(%R13)

  (608) 0x470634 JMP	4703ca

  (608) 0x470640 MOV	-0x90(%RBP),%R10

  (608) 0x470647 MOV	%R13,%R11

  (608) 0x47064a NOT	%R11

  (608) 0x47064d LEA	(%R10,%R11,8),%R11

  (608) 0x470651 VMOVQ	%R11,%XMM14

  (608) 0x470656 CMP	%RDI,(%R11)

  (608) 0x470659 JE	470394

  (608) 0x47065f MOV	-0x80(%RBP),%R10

  (608) 0x470663 NOT	%R13

  (608) 0x470666 MOV	(%R10,%R12,1),%R11

  (608) 0x47066a MOV	%R13,(%R11,%RSI,8)

  (608) 0x47066e VMOVQ	%XMM14,%R13

  (608) 0x470673 INC	%RSI

  (608) 0x470676 MOV	%RDI,(%R13)

  (608) 0x47067a JMP	470394

  (608) 0x470680 MOV	-0x90(%RBP),%R10

  (608) 0x470687 MOV	%R13,%R11

  (608) 0x47068a NOT	%R11

  (608) 0x47068d LEA	(%R10,%R11,8),%R11

  (608) 0x470691 VMOVQ	%R11,%XMM9

  (608) 0x470696 CMP	%RDI,(%R11)

  (608) 0x470699 JE	470369

  (608) 0x47069f MOV	-0x80(%RBP),%R10

  (608) 0x4706a3 NOT	%R13

  (608) 0x4706a6 MOV	(%R10,%R12,1),%R11

  (608) 0x4706aa MOV	%R13,(%R11,%RSI,8)

  (608) 0x4706ae VMOVQ	%XMM9,%R13

  (608) 0x4706b3 INC	%RSI

  (608) 0x4706b6 MOV	%RDI,(%R13)

  (608) 0x4706ba JMP	470369

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►97.15+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.85+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.75
Front-end cycles	6.00
P0 cycles	2.67
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	48.00
Nb loads	21.00
Nb stores	5.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.75
Front-end cycles	6.00
P0 cycles	2.67
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	48.00
Nb loads	21.00
Nb stores	5.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 2.67 cycles (2.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	50
nb uops	48
loop length	242
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	1.00	1.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

9% of peak load performance is reached (25.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 2.67 cycles (2.25x speedup).

ASM code

In the binary file, the address of the loop is: 46fe70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xc0(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R13,%R14,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (,%R14,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R10,%RDI,1),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV (%R10,%RDI,1),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
LEA 0x8(%RDI),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %RAX,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 470269 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1259>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46ff0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xefc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xd8(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xe0(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R10,%R13,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%R10,%RDI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 470560 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1550>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x98(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 4702cc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x12bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INCQ -0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R13,-0xc8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 46fe70 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 2.67 cycles (2.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	50
nb uops	48
loop length	242
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	1.00	1.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

9% of peak load performance is reached (25.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46fe70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xc0(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R13,%R14,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (,%R14,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R10,%RDI,1),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV (%R10,%RDI,1),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
LEA 0x8(%RDI),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %RAX,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 470269 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1259>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %RDI,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46ff0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xefc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xd8(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xe0(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %XMM14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R10,%R13,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%R10,%RDI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 470560 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1550>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x98(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 4702cc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x12bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INCQ -0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R13,-0xc8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 46fe70 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code