OV - exec - Loop 3100

	Loop Id: 3100	Module: exec	Source: csr_matvec.c:183-196 [...]	Coverage: 0.06%

0x595ccc LEA	(,%RDI,8),%RDI

0x595cd4 MOV	(%RBX,%RDI,1),%R9

0x595cd8 MOV	0x8(%RBX,%RDI,1),%R13

0x595cdd CMP	%R9,%R13

0x595ce0 JLE	595f96

0x595ce6 MOV	%R13,%R11

0x595ce9 SUB	%R9,%R11

0x595cec LEA	-0x1(%R11),%RAX

0x595cf0 CMP	$0x2,%RAX

0x595cf4 JBE	595f9d

0x595cfa MOV	%R11,%R10

0x595cfd LEA	(,%R9,8),%RDX

0x595d05 XOR	%EAX,%EAX

0x595d07 VXORPD	%XMM0,%XMM0,%XMM0

0x595d0b SHR	$0x2,%R10

0x595d0f SAL	$0x5,%R10

0x595d13 LEA	-0x20(%R10),%R8

0x595d17 LEA	(%R12,%RDX,1),%RSI

0x595d1b ADD	%R14,%RDX

0x595d1e SHR	$0x5,%R8

0x595d22 INC	%R8

0x595d25 AND	$0x7,%R8D

0x595d29 JE	595e19

0x595d2f CMP	$0x1,%R8

0x595d33 JE	595df6

0x595d39 CMP	$0x2,%R8

0x595d3d JE	595ddc

0x595d43 CMP	$0x3,%R8

0x595d47 JE	595dc2

0x595d49 CMP	$0x4,%R8

0x595d4d JE	595da8

0x595d4f CMP	$0x5,%R8

0x595d53 JE	595d8e

0x595d55 CMP	$0x6,%R8

0x595d59 JE	595d74

0x595d5b VMOVDQU	(%RDX),%YMM7

0x595d5f KMOVB	%K0,%K3

0x595d63 MOV	$0x20,%EAX

0x595d68 VGATHERQPD	(%R15,%YMM7,8),%YMM3{%K3}

0x595d6f VFMADD231PD	(%RSI),%YMM3,%YMM0

0x595d74 VMOVDQU	(%RDX,%RAX,1),%YMM14

0x595d79 KMOVB	%K0,%K4

0x595d7d VGATHERQPD	(%R15,%YMM14,8),%YMM15{%K4}

0x595d84 VFMADD231PD	(%RSI,%RAX,1),%YMM15,%YMM0

0x595d8a ADD	$0x20,%RAX

0x595d8e VMOVDQU	(%RDX,%RAX,1),%YMM13

0x595d93 KMOVB	%K0,%K5

0x595d97 VGATHERQPD	(%R15,%YMM13,8),%YMM6{%K5}

0x595d9e VFMADD231PD	(%RSI,%RAX,1),%YMM6,%YMM0

0x595da4 ADD	$0x20,%RAX

0x595da8 VMOVDQU	(%RDX,%RAX,1),%YMM12

0x595dad KMOVB	%K0,%K6

0x595db1 VGATHERQPD	(%R15,%YMM12,8),%YMM11{%K6}

0x595db8 VFMADD231PD	(%RSI,%RAX,1),%YMM11,%YMM0

0x595dbe ADD	$0x20,%RAX

0x595dc2 VMOVDQU	(%RDX,%RAX,1),%YMM1

0x595dc7 KMOVB	%K0,%K7

0x595dcb VGATHERQPD	(%R15,%YMM1,8),%YMM4{%K7}

0x595dd2 VFMADD231PD	(%RSI,%RAX,1),%YMM4,%YMM0

0x595dd8 ADD	$0x20,%RAX

0x595ddc VMOVDQU	(%RDX,%RAX,1),%YMM10

0x595de1 KMOVB	%K0,%K1

0x595de5 VGATHERQPD	(%R15,%YMM10,8),%YMM5{%K1}

0x595dec VFMADD231PD	(%RSI,%RAX,1),%YMM5,%YMM0

0x595df2 ADD	$0x20,%RAX

0x595df6 VMOVDQU	(%RDX,%RAX,1),%YMM9

0x595dfb KMOVB	%K0,%K2

0x595dff VGATHERQPD	(%R15,%YMM9,8),%YMM8{%K2}

0x595e06 VFMADD231PD	(%RSI,%RAX,1),%YMM8,%YMM0

0x595e0c ADD	$0x20,%RAX

0x595e10 CMP	%RAX,%R10

0x595e13 JE	595efe

  (3101) 0x595e19 VMOVDQU	(%RDX,%RAX,1),%YMM7

  (3101) 0x595e1e VMOVDQU	0x20(%RDX,%RAX,1),%YMM14

  (3101) 0x595e24 KMOVB	%K0,%K3

  (3101) 0x595e28 KMOVB	%K0,%K4

  (3101) 0x595e2c VMOVDQU	0x40(%RDX,%RAX,1),%YMM13

  (3101) 0x595e32 VMOVDQU	0x60(%RDX,%RAX,1),%YMM12

  (3101) 0x595e38 KMOVB	%K0,%K5

  (3101) 0x595e3c VMOVDQU	0x80(%RDX,%RAX,1),%YMM11

  (3101) 0x595e45 VMOVDQU	0xa0(%RDX,%RAX,1),%YMM4

  (3101) 0x595e4e KMOVB	%K0,%K6

  (3101) 0x595e52 VMOVDQU	0xc0(%RDX,%RAX,1),%YMM5

  (3101) 0x595e5b VMOVDQU	0xe0(%RDX,%RAX,1),%YMM8

  (3101) 0x595e64 KMOVB	%K0,%K7

  (3101) 0x595e68 KMOVB	%K0,%K1

  (3101) 0x595e6c KMOVB	%K0,%K2

  (3101) 0x595e70 VGATHERQPD	(%R15,%YMM7,8),%YMM3{%K3}

  (3101) 0x595e77 KMOVB	%K0,%K3

  (3101) 0x595e7b VFMADD231PD	(%RSI,%RAX,1),%YMM3,%YMM0

  (3101) 0x595e81 VGATHERQPD	(%R15,%YMM14,8),%YMM15{%K4}

  (3101) 0x595e88 VGATHERQPD	(%R15,%YMM13,8),%YMM6{%K5}

  (3101) 0x595e8f VFMADD231PD	0x20(%RSI,%RAX,1),%YMM15,%YMM0

  (3101) 0x595e96 VFMADD132PD	0x40(%RSI,%RAX,1),%YMM0,%YMM6

  (3101) 0x595e9d VGATHERQPD	(%R15,%YMM12,8),%YMM0{%K6}

  (3101) 0x595ea4 VGATHERQPD	(%R15,%YMM11,8),%YMM1{%K7}

  (3101) 0x595eab VFMADD132PD	0x60(%RSI,%RAX,1),%YMM6,%YMM0

  (3101) 0x595eb2 VGATHERQPD	(%R15,%YMM4,8),%YMM10{%K1}

  (3101) 0x595eb9 VFMADD132PD	0x80(%RSI,%RAX,1),%YMM0,%YMM1

  (3101) 0x595ec3 VGATHERQPD	(%R15,%YMM5,8),%YMM9{%K2}

  (3101) 0x595eca VFMADD132PD	0xa0(%RSI,%RAX,1),%YMM1,%YMM10

  (3101) 0x595ed4 VGATHERQPD	(%R15,%YMM8,8),%YMM0{%K3}

  (3101) 0x595edb VFMADD132PD	0xc0(%RSI,%RAX,1),%YMM10,%YMM9

  (3101) 0x595ee5 VFMADD132PD	0xe0(%RSI,%RAX,1),%YMM9,%YMM0

  (3101) 0x595eef ADD	$0x100,%RAX

  (3101) 0x595ef5 CMP	%RAX,%R10

  (3101) 0x595ef8 JNE	595e19

0x595efe VEXTRACTF64X2	$0x1,%YMM0,%XMM7

0x595f05 VADDPD	%XMM0,%XMM7,%XMM3

0x595f09 MOV	%R11,%RDX

0x595f0c AND	$-0x4,%RDX

0x595f10 ADD	%RDX,%R9

0x595f13 AND	$0x3,%R11D

0x595f17 VUNPCKHPD	%XMM3,%XMM3,%XMM14

0x595f1b VADDPD	%XMM3,%XMM14,%XMM8

0x595f1f JE	595f6f

0x595f21 LEA	(,%R9,8),%R11

0x595f29 LEA	0x1(%R9),%R10

0x595f2d MOV	(%R14,%R11,1),%RSI

0x595f31 VMOVSD	(%R12,%R11,1),%XMM15

0x595f37 VFMADD231SD	(%R15,%RSI,8),%XMM15,%XMM8

0x595f3d CMP	%R13,%R10

0x595f40 JGE	595f6f

0x595f42 MOV	0x8(%R14,%R11,1),%R8

0x595f47 ADD	$0x2,%R9

0x595f4b VMOVSD	(%R15,%R8,8),%XMM13

0x595f51 VFMADD231SD	0x8(%R12,%R11,1),%XMM13,%XMM8

0x595f58 CMP	%R13,%R9

0x595f5b JGE	595f6f

0x595f5d MOV	0x10(%R14,%R11,1),%R9

0x595f62 VMOVSD	(%R15,%R9,8),%XMM6

0x595f68 VFMADD231SD	0x10(%R12,%R11,1),%XMM6,%XMM8

0x595f6f VMOVQ	%XMM2,%R13

0x595f74 ADD	$0x8,%RCX

0x595f78 ADD	%R13,%RDI

0x595f7b VADDSD	(%RDI),%XMM8,%XMM12

0x595f7f VMOVSD	%XMM12,(%RDI)

0x595f83 CMP	%RCX,0x10(%RSP)

0x595f88 JE	5955db

0x595f8e MOV	(%RCX),%RDI

0x595f91 JMP	595ccc

0x595f96 VXORPD	%XMM8,%XMM8,%XMM8

0x595f9b JMP	595f6f

0x595f9d VXORPD	%XMM8,%XMM8,%XMM8

0x595fa2 JMP	595f21

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 183 - 196

--------------------------------------------------------------------------------

183:             m = A_rownnz[i];

[...]

191:             if ( num_vectors==1 )

192:             {

193:                tempx = 0;

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

Coverage (%)	Name	Source Location	Module
►96.98+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.84+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:231	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_BoomerAMGCycle	par_cycle.c:429	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►1.03+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:231	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_PCGSolve	pcg.c:496	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.57
CQA speedup if fully vectorized	3.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source	csr_matvec.c:183-183,csr_matvec.c:191-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.88
CQA cycles if no scalar integer	26.75
CQA cycles if FP arith vectorized	21.56
CQA cycles if fully vectorized	10.63
Front-end cycles	33.88
P0 cycles	9.33
P1 cycles	9.33
P2 cycles	9.33
P3 cycles	9.33
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	14.25
P7 cycles	14.25
P8 cycles	14.25
P9 cycles	14.25
P10 cycles	14.25
P11 cycles	14.25
P12 cycles	14.25
P13 cycles	14.25
P14 cycles	22.00
P15 cycles	22.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	110.00
Nb uops	271.00
Nb loads	35.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	1.98
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	31.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	784.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	55.10
Vectorization ratio load	72.41
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	70.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	45.83
Vector-efficiency ratio all	30.10
Vector-efficiency ratio load	39.66
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	38.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.52

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.57
CQA speedup if fully vectorized	3.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source	csr_matvec.c:183-183,csr_matvec.c:191-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.88
CQA cycles if no scalar integer	26.75
CQA cycles if FP arith vectorized	21.56
CQA cycles if fully vectorized	10.63
Front-end cycles	33.88
P0 cycles	9.33
P1 cycles	9.33
P2 cycles	9.33
P3 cycles	9.33
P4 cycles	9.33
P5 cycles	9.33
P6 cycles	14.25
P7 cycles	14.25
P8 cycles	14.25
P9 cycles	14.25
P10 cycles	14.25
P11 cycles	14.25
P12 cycles	14.25
P13 cycles	14.25
P14 cycles	22.00
P15 cycles	22.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	110.00
Nb uops	271.00
Nb loads	35.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	1.98
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	31.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	784.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	55.10
Vectorization ratio load	72.41
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	70.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	45.83
Vector-efficiency ratio all	30.10
Vector-efficiency ratio load	39.66
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	38.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.52

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source file and lines	csr_matvec.c:183-196
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:183,191-196.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 33.88 to 26.75 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions).

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 31 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF64X2: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 67 FP arithmetical operations:

36: addition or subtraction (31 inside FMA instructions)
31: multiply (all inside FMA instructions)

The binary loop is loading 784 bytes (98 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	271
loop length	502
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	15
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.88 cycles
front end	33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.33	9.33	9.33	9.33	9.33	9.33	14.25	14.25	14.25	14.25	14.25	14.25	14.25	14.25	22.00	22.00
cycles	9.33	9.33	9.33	9.33	9.33	9.33	14.25	14.25	14.25	14.25	14.25	14.25	14.25	14.25	22.00	22.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.88
Dispatch	22.00
Overall L1	33.88

Vectorization ratios

INT

all	35%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	68%
load	66%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	70%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	91%

INT+FP

all	55%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	70%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	25%
load	45%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	33%
load	37%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	38%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	30%
load	39%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	38%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.88 cycles. At this rate:

9% of peak load performance is reached (23.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 33.88 to 22.00 cycles (1.54x speedup).

ASM code

In the binary file, the address of the loop is: 595ccc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA (,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDI,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX,%RDI,1),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R9,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595f96 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R11),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595f9d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdfd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R9,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%R10),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RDX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 595e19 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc79>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595df6 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc56>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595ddc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595dc2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595da8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc08>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595d8e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xbee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595d74 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xbd4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDX),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R15,%YMM7,8),%YMM3{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI),%YMM3,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQU (%RDX,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM14,8),%YMM15{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM15,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM13,8),%YMM6{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM6,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM12,8),%YMM11{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM11,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM1,8),%YMM4{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM4,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM10,8),%YMM5{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM5,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM9,8),%YMM8{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM8,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595efe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xd5e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM0,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VUNPCKHPD %XMM3,%XMM3,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM3,%XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%R9,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R9),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R14,%R11,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R12,%R11,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD (%R15,%RSI,8),%XMM15,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14,%R11,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R15,%R8,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x8(%R12,%R11,1),%XMM13,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%R14,%R11,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R15,%R9,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x10(%R12,%R11,1),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RDI),%XMM8,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5955db <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 595ccc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xb2c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 595f21 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xd81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source file and lines	csr_matvec.c:183-196
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:183,191-196.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions).

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 31 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF64X2: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:195

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 67 FP arithmetical operations:

36: addition or subtraction (31 inside FMA instructions)
31: multiply (all inside FMA instructions)

The binary loop is loading 784 bytes (98 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	271
loop length	502
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	15
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.88 cycles
front end	33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.33	9.33	9.33	9.33	9.33	9.33	14.25	14.25	14.25	14.25	14.25	14.25	14.25	14.25	22.00	22.00
cycles	9.33	9.33	9.33	9.33	9.33	9.33	14.25	14.25	14.25	14.25	14.25	14.25	14.25	14.25	22.00	22.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.88
Dispatch	22.00
Overall L1	33.88

Vectorization ratios

INT

all	35%
load	87%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	68%
load	66%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	70%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	91%

INT+FP

all	55%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	70%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	25%
load	45%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	33%
load	37%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	38%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	30%
load	39%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	38%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.88 cycles. At this rate:

9% of peak load performance is reached (23.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 595ccc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA (,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDI,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX,%RDI,1),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R9,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595f96 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R11),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595f9d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdfd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R9,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%R10),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RDX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 595e19 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc79>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595df6 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc56>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595ddc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595dc2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595da8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xc08>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595d8e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xbee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595d74 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xbd4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDX),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R15,%YMM7,8),%YMM3{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI),%YMM3,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQU (%RDX,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM14,8),%YMM15{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM15,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM13,8),%YMM6{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM6,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM12,8),%YMM11{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM11,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM1,8),%YMM4{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM4,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM10,8),%YMM5{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM5,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDX,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM9,8),%YMM8{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD231PD (%RSI,%RAX,1),%YMM8,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595efe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xd5e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM0,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VUNPCKHPD %XMM3,%XMM3,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM3,%XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%R9,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R9),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R14,%R11,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R12,%R11,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD (%R15,%RSI,8),%XMM15,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R14,%R11,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%R15,%R8,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x8(%R12,%R11,1),%XMM13,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%R14,%R11,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R15,%R9,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x10(%R12,%R11,1),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RDI),%XMM8,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RCX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5955db <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 595ccc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xb2c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 595f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xdcf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 595f21 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xd81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code