OV - exec - Loop 2826

	Loop Id: 2826	Module: exec	Source: IJMatrix_parcsr.c:306-307	Coverage: 0.04%

0x576db4 VMOVDQU	(%RSI,%R12,1),%YMM15    [4]

0x576dba VMOVDQU	%YMM15,(%R8,%R12,1)    [1]

0x576dc0 VMOVDQU	(%R9,%R12,1),%YMM3    [2]

0x576dc6 VMOVDQU	%YMM3,(%RDI,%R12,1)    [3]

0x576dcc VMOVDQU	0x20(%RSI,%R12,1),%YMM0    [4]

0x576dd3 VMOVDQU	%YMM0,0x20(%R8,%R12,1)    [1]

0x576dda VMOVDQU	0x20(%R9,%R12,1),%YMM1    [2]

0x576de1 VMOVDQU	%YMM1,0x20(%RDI,%R12,1)    [3]

0x576de8 VMOVDQU	0x40(%RSI,%R12,1),%YMM2    [4]

0x576def VMOVDQU	%YMM2,0x40(%R8,%R12,1)    [1]

0x576df6 VMOVDQU	0x40(%R9,%R12,1),%YMM4    [2]

0x576dfd VMOVDQU	%YMM4,0x40(%RDI,%R12,1)    [3]

0x576e04 VMOVDQU	0x60(%RSI,%R12,1),%YMM5    [4]

0x576e0b VMOVDQU	%YMM5,0x60(%R8,%R12,1)    [1]

0x576e12 VMOVDQU	0x60(%R9,%R12,1),%YMM6    [2]

0x576e19 VMOVDQU	%YMM6,0x60(%RDI,%R12,1)    [3]

0x576e20 VMOVDQU	0x80(%RSI,%R12,1),%YMM7    [4]

0x576e2a VMOVDQU	%YMM7,0x80(%R8,%R12,1)    [1]

0x576e34 VMOVDQU	0x80(%R9,%R12,1),%YMM8    [2]

0x576e3e VMOVDQU	%YMM8,0x80(%RDI,%R12,1)    [3]

0x576e48 VMOVDQU	0xa0(%RSI,%R12,1),%YMM9    [4]

0x576e52 VMOVDQU	%YMM9,0xa0(%R8,%R12,1)    [1]

0x576e5c VMOVDQU	0xa0(%R9,%R12,1),%YMM10    [2]

0x576e66 VMOVDQU	%YMM10,0xa0(%RDI,%R12,1)    [3]

0x576e70 VMOVDQU	0xc0(%RSI,%R12,1),%YMM11    [4]

0x576e7a VMOVDQU	%YMM11,0xc0(%R8,%R12,1)    [1]

0x576e84 VMOVDQU	0xc0(%R9,%R12,1),%YMM12    [2]

0x576e8e VMOVDQU	%YMM12,0xc0(%RDI,%R12,1)    [3]

0x576e98 VMOVDQU	0xe0(%RSI,%R12,1),%YMM13    [4]

0x576ea2 VMOVDQU	%YMM13,0xe0(%R8,%R12,1)    [1]

0x576eac VMOVDQU	0xe0(%R9,%R12,1),%YMM14    [2]

0x576eb6 VMOVDQU	%YMM14,0xe0(%RDI,%R12,1)    [3]

0x576ec0 ADD	$0x100,%R12

0x576ec7 CMP	%R12,%R13

0x576eca JNE	576db4

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 306 - 307

--------------------------------------------------------------------------------

306: 	    indx_diag[i] = diag_i[i];

307: 	    indx_offd[i] = offd_i[i];

Coverage (%)	Name	Source Location	Module
►97.09+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.91+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_IJMatrixInitializeParCSR	IJMatrix_parcsr.c:302	exec
○	HYPRE_IJMatrixInitialize	HYPRE_IJMatrix.c:292	exec
○	BuildIJLaplacian27pt	amg.c:2262	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	P6, P7, P8, P9, P14, P15,
Function	hypre_IJMatrixInitializeParCSR._omp_fn.0
Source	IJMatrix_parcsr.c:306-307
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	4.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	P6, P7, P8, P9, P14, P15,
Function	hypre_IJMatrixInitializeParCSR._omp_fn.0
Source	IJMatrix_parcsr.c:306-307
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	4.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixInitializeParCSR._omp_fn.0
Source file and lines	IJMatrix_parcsr.c:306-307
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:306-307.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 512 bytes.

General properties

nb instructions	35
nb uops	34
loop length	284
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

25% of peak load performance is reached (64.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (64.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 576db4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU (%RSI,%R12,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM15,(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU (%R9,%R12,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM3,(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x20(%RSI,%R12,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM0,0x20(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x20(%R9,%R12,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM1,0x20(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x40(%RSI,%R12,1),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM2,0x40(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x40(%R9,%R12,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM4,0x40(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x60(%RSI,%R12,1),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM5,0x60(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x60(%R9,%R12,1),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM6,0x60(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x80(%RSI,%R12,1),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM7,0x80(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x80(%R9,%R12,1),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM8,0x80(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xa0(%RSI,%R12,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM9,0xa0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xa0(%R9,%R12,1),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM10,0xa0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xc0(%RSI,%R12,1),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM11,0xc0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xc0(%R9,%R12,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM12,0xc0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xe0(%RSI,%R12,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM13,0xe0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xe0(%R9,%R12,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM14,0xe0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x100,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 576db4 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_IJMatrixInitializeParCSR._omp_fn.0
Source file and lines	IJMatrix_parcsr.c:306-307
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 512 bytes.

General properties

nb instructions	35
nb uops	34
loop length	284
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

25% of peak load performance is reached (64.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (64.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 576db4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU (%RSI,%R12,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM15,(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU (%R9,%R12,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM3,(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x20(%RSI,%R12,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM0,0x20(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x20(%R9,%R12,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM1,0x20(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x40(%RSI,%R12,1),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM2,0x40(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x40(%R9,%R12,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM4,0x40(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x60(%RSI,%R12,1),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM5,0x60(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x60(%R9,%R12,1),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM6,0x60(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x80(%RSI,%R12,1),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM7,0x80(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x80(%R9,%R12,1),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM8,0x80(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xa0(%RSI,%R12,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM9,0xa0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xa0(%R9,%R12,1),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM10,0xa0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xc0(%RSI,%R12,1),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM11,0xc0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xc0(%R9,%R12,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM12,0xc0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xe0(%RSI,%R12,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM13,0xe0(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0xe0(%R9,%R12,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU %YMM14,0xe0(%RDI,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x100,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 576db4 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x234>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code