OV - exec - Loop 2488

	Loop Id: 2488	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.02%

0x5538c5 VMOVQ	%XMM7,%RDX

0x5538ca MOV	%RBX,-0x70(%RBP)

0x5538ce TEST	%RDX,%RDX

0x5538d1 JNE	553a4e

0x5538db MOV	-0x80(%RBP),%R12

0x5538df MOV	-0x78(%RBP),%R8

0x5538e3 MOV	(%R12,%R8,8),%R9

0x5538e7 CMP	0x8(%R12,%R8,8),%R9

0x5538ec JGE	5539e8

0x5538f2 MOV	-0xe8(%RBP),%R12

0x5538f9 MOV	-0x70(%RBP),%RAX

0x5538fd VMOVDQA	%XMM11,%XMM2

0x553901 VMOVQ	%XMM12,%R10

0x553906 VMOVQ	%XMM13,%R13

0x55390b VMOVQ	%XMM14,%R11

0x553910 MOV	%R15,-0xa8(%RBP)

0x553917 MOV	%R9,-0x50(%RBP)

0x55391b NOPL	(%RAX,%RAX,1)

  (2492) 0x553920 MOV	-0x50(%RBP),%RCX

  (2492) 0x553924 MOV	-0x98(%RBP),%RDX

  (2492) 0x55392b MOV	-0x90(%RBP),%R15

  (2492) 0x553932 MOV	-0xa0(%RBP),%R14

  (2492) 0x553939 MOV	(%RDX,%RCX,8),%RSI

  (2492) 0x55393d VMOVSD	(%R14,%RCX,8),%XMM8

  (2492) 0x553943 MOV	%RAX,%RCX

  (2492) 0x553946 LEA	(,%RSI,8),%R8

  (2492) 0x55394e LEA	0x8(%R8),%R9

  (2492) 0x553952 MOV	(%R15,%R8,1),%RDX

  (2492) 0x553956 MOV	%R9,-0x70(%RBP)

  (2492) 0x55395a LEA	0x8(%R15,%R8,1),%R9

  (2492) 0x55395f MOV	(%R9),%R14

  (2492) 0x553962 MOV	%R14,%RSI

  (2492) 0x553965 CMP	%R14,%RDX

  (2492) 0x553968 JGE	5539b4

  (2492) 0x55396a NOPW	%CS:(%RAX,%RAX,1)

  (2492) 0x553975 NOPW	%CS:(%RAX,%RAX,1)

    (2494) 0x553980 MOV	(%R13,%RDX,8),%R15

    (2494) 0x553985 VMULSD	(%R11,%RDX,8),%XMM8,%XMM1

    (2494) 0x55398b LEA	(%RDI,%R15,8),%R14

    (2494) 0x55398f MOV	(%R14),%RAX

    (2494) 0x553992 CMP	%RAX,%RBX

    (2494) 0x553995 JG	553c30

    (2494) 0x55399b LEA	(%R10,%RAX,8),%R15

    (2494) 0x55399f INC	%RDX

    (2494) 0x5539a2 VADDSD	(%R15),%XMM1,%XMM0

    (2494) 0x5539a7 VMOVSD	%XMM0,(%R15)

    (2494) 0x5539ac CMP	%RSI,%RDX

    (2494) 0x5539af JL	553980

  (2492) 0x5539b1 MOV	%RCX,%RAX

  (2492) 0x5539b4 CMPQ	$0,-0x88(%RBP)

  (2492) 0x5539bc JNE	553c70

  (2492) 0x5539c2 MOV	-0x80(%RBP),%R9

  (2492) 0x5539c6 MOV	-0x78(%RBP),%RDX

  (2492) 0x5539ca INCQ	-0x50(%RBP)

  (2492) 0x5539ce MOV	-0x50(%RBP),%RCX

  (2492) 0x5539d2 CMP	%RCX,0x8(%R9,%RDX,8)

  (2492) 0x5539d7 JG	553920

0x5539dd MOV	-0xa8(%RBP),%R15

0x5539e4 MOV	%RAX,-0x70(%RBP)

0x5539e8 INCQ	-0x78(%RBP)

0x5539ec MOV	-0x78(%RBP),%RBX

0x5539f0 CMP	%RBX,-0xf8(%RBP)

0x5539f7 JE	553db9

0x5539fd CMPQ	$0,-0xf0(%RBP)

0x553a05 MOV	-0x70(%RBP),%RBX

0x553a09 MOV	%R15,-0x38(%RBP)

0x553a0d JE	5538c5

0x553a4e MOV	-0xb8(%RBP),%R9

0x553a55 MOV	-0x78(%RBP),%RSI

0x553a59 MOV	(%R9,%RSI,8),%RAX

0x553a5d CMP	0x8(%R9,%RSI,8),%RAX

0x553a62 JGE	5538d7

0x553a68 MOV	-0x38(%RBP),%RCX

0x553a6c MOV	-0x100(%RBP),%R15

0x553a73 MOV	-0x110(%RBP),%R8

0x553a7a MOV	-0x108(%RBP),%R14

0x553a81 VMOVQ	%XMM15,%R12

0x553a86 VMOVDQA	%XMM11,%XMM8

0x553a8b MOV	%RBX,%R10

0x553a8e MOV	%RAX,-0x50(%RBP)

0x553a92 VMOVQ	%XMM12,%R9

0x553a97 MOV	%RCX,-0xb0(%RBP)

0x553a9e XCHG	%AX,%AX

  (2487) 0x553aa0 MOV	-0x50(%RBP),%R13

  (2487) 0x553aa4 MOV	-0xd8(%RBP),%R11

  (2487) 0x553aab MOV	-0xe0(%RBP),%RBX

  (2487) 0x553ab2 MOV	(%R11,%R13,8),%RDX

  (2487) 0x553ab6 VMOVSD	(%RBX,%R13,8),%XMM1

  (2487) 0x553abc MOV	-0xc0(%RBP),%RBX

  (2487) 0x553ac3 MOV	%RDX,-0xa8(%RBP)

  (2487) 0x553aca SAL	$0x3,%RDX

  (2487) 0x553ace LEA	0x8(%RBX,%RDX,1),%R13

  (2487) 0x553ad3 MOV	(%RBX,%RDX,1),%RAX

  (2487) 0x553ad7 VMOVQ	%RDX,%XMM0

  (2487) 0x553adc LEA	0x8(%RDX),%RSI

  (2487) 0x553ae0 MOV	(%R13),%RDX

  (2487) 0x553ae4 VMOVQ	%R13,%XMM4

  (2487) 0x553ae9 CMP	%RDX,%RAX

  (2487) 0x553aec JGE	553b8d

  (2487) 0x553af2 MOV	%RSI,-0xa8(%RBP)

  (2487) 0x553af9 MOV	-0xb0(%RBP),%RSI

  (2487) 0x553b00 MOV	%RDI,%R11

  (2487) 0x553b03 MOV	%RDX,%RDI

  (2487) 0x553b06 NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553b11 NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553b1c NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553b27 NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553b32 NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553b3d NOPL	(%RAX)

    (2490) 0x553b40 MOV	(%R12,%RAX,8),%R13

    (2490) 0x553b44 MOV	-0x40(%RBP),%RBX

    (2490) 0x553b48 VMULSD	(%R15,%RAX,8),%XMM1,%XMM6

    (2490) 0x553b4e LEA	(%RBX,%R13,1),%RCX

    (2490) 0x553b52 LEA	(%R11,%RCX,8),%RDX

    (2490) 0x553b56 MOV	(%RDX),%RCX

    (2490) 0x553b59 CMP	%RCX,-0x38(%RBP)

    (2490) 0x553b5d JG	553d80

    (2490) 0x553b63 MOV	-0x48(%RBP),%R13

    (2490) 0x553b67 INC	%RAX

    (2490) 0x553b6a LEA	(%R13,%RCX,8),%RBX

    (2490) 0x553b6f VADDSD	(%RBX),%XMM6,%XMM3

    (2490) 0x553b73 VMOVSD	%XMM3,(%RBX)

    (2490) 0x553b77 CMP	%RDI,%RAX

    (2490) 0x553b7a JL	553b40

  (2487) 0x553b7c MOV	%RSI,-0xb0(%RBP)

  (2487) 0x553b83 MOV	-0xa8(%RBP),%RSI

  (2487) 0x553b8a MOV	%R11,%RDI

  (2487) 0x553b8d MOV	-0xc8(%RBP),%R11

  (2487) 0x553b94 VMOVQ	%XMM0,%RAX

  (2487) 0x553b99 LEA	(%R11,%RSI,1),%RBX

  (2487) 0x553b9d MOV	(%R11,%RAX,1),%RAX

  (2487) 0x553ba1 MOV	(%RBX),%RDX

  (2487) 0x553ba4 CMP	%RDX,%RAX

  (2487) 0x553ba7 JGE	553bf6

  (2487) 0x553ba9 MOV	-0x70(%RBP),%RCX

  (2487) 0x553bad MOV	%RDI,%R11

  (2487) 0x553bb0 MOV	%RDX,%RDI

  (2487) 0x553bb3 NOPW	%CS:(%RAX,%RAX,1)

  (2487) 0x553bbe XCHG	%AX,%AX

    (2489) 0x553bc0 MOV	(%R14,%RAX,8),%RSI

    (2489) 0x553bc4 VMULSD	(%R8,%RAX,8),%XMM1,%XMM9

    (2489) 0x553bca LEA	(%R11,%RSI,8),%R13

    (2489) 0x553bce MOV	(%R13),%RDX

    (2489) 0x553bd2 CMP	%RDX,%R10

    (2489) 0x553bd5 JG	553d40

    (2489) 0x553bdb LEA	(%R9,%RDX,8),%RSI

    (2489) 0x553bdf INC	%RAX

    (2489) 0x553be2 VADDSD	(%RSI),%XMM9,%XMM10

    (2489) 0x553be6 VMOVSD	%XMM10,(%RSI)

    (2489) 0x553bea CMP	%RDI,%RAX

    (2489) 0x553bed JL	553bc0

  (2487) 0x553bef MOV	%R11,%RDI

  (2487) 0x553bf2 MOV	%RCX,-0x70(%RBP)

  (2487) 0x553bf6 MOV	-0xb8(%RBP),%R11

  (2487) 0x553bfd MOV	-0x78(%RBP),%RBX

  (2487) 0x553c01 INCQ	-0x50(%RBP)

  (2487) 0x553c05 MOV	-0x50(%RBP),%RAX

  (2487) 0x553c09 CMP	%RAX,0x8(%R11,%RBX,8)

  (2487) 0x553c0e JG	553aa0

0x553c14 MOV	-0xb0(%RBP),%R15

0x553c1b VMOVQ	%R12,%XMM15

0x553c20 MOV	%R10,%RBX

0x553c23 JMP	5538db

    (2494) 0x553c30 MOV	%RCX,(%R14)

    (2494) 0x553c33 VMOVQ	%XMM2,%RSI

    (2494) 0x553c38 LEA	(,%RCX,8),%R14

    (2494) 0x553c40 INC	%RDX

    (2494) 0x553c43 VMOVSD	%XMM1,(%R10,%R14,1)

    (2494) 0x553c49 MOV	%R15,(%RSI,%R14,1)

    (2494) 0x553c4d MOV	(%R9),%RSI

    (2494) 0x553c50 INC	%RCX

    (2494) 0x553c53 CMP	%RDX,%RSI

    (2494) 0x553c56 JG	553980

  (2492) 0x553c5c JMP	5539b1

  (2492) 0x553c70 MOV	-0xd0(%RBP),%R9

  (2492) 0x553c77 MOV	(%R9,%R8,1),%RDX

  (2492) 0x553c7b MOV	-0x70(%RBP),%R8

  (2492) 0x553c7f ADD	%R9,%R8

  (2492) 0x553c82 MOV	(%R8),%R15

  (2492) 0x553c85 CMP	%R15,%RDX

  (2492) 0x553c88 JGE	5539c2

  (2492) 0x553c8e MOV	-0xa8(%RBP),%RCX

  (2492) 0x553c95 MOV	%RAX,-0x70(%RBP)

  (2492) 0x553c99 MOV	%R8,%RAX

  (2492) 0x553c9c NOPL	(%RAX)

    (2493) 0x553ca0 MOV	(%R12,%RDX,8),%R14

    (2493) 0x553ca4 MOV	-0x60(%RBP),%RSI

    (2493) 0x553ca8 MOV	-0x40(%RBP),%R8

    (2493) 0x553cac MOV	(%RSI,%R14,8),%R9

    (2493) 0x553cb0 MOV	-0x68(%RBP),%RSI

    (2493) 0x553cb4 LEA	(%R8,%R9,1),%R14

    (2493) 0x553cb8 VMULSD	(%RSI,%RDX,8),%XMM8,%XMM4

    (2493) 0x553cbd LEA	(%RDI,%R14,8),%R14

    (2493) 0x553cc1 MOV	(%R14),%R8

    (2493) 0x553cc4 CMP	%R8,-0x38(%RBP)

    (2493) 0x553cc8 JG	553d00

    (2493) 0x553cca MOV	-0x48(%RBP),%R9

    (2493) 0x553cce INC	%RDX

    (2493) 0x553cd1 LEA	(%R9,%R8,8),%R14

    (2493) 0x553cd5 VADDSD	(%R14),%XMM4,%XMM6

    (2493) 0x553cda VMOVSD	%XMM6,(%R14)

    (2493) 0x553cdf CMP	%R15,%RDX

    (2493) 0x553ce2 JL	553ca0

  (2492) 0x553ce4 MOV	-0x70(%RBP),%RAX

  (2492) 0x553ce8 MOV	%RCX,-0xa8(%RBP)

  (2492) 0x553cef JMP	5539c2

    (2493) 0x553d00 MOV	-0x48(%RBP),%R8

    (2493) 0x553d04 MOV	-0x58(%RBP),%RSI

    (2493) 0x553d08 LEA	(,%RCX,8),%R15

    (2493) 0x553d10 MOV	%RCX,(%R14)

    (2493) 0x553d13 INC	%RDX

    (2493) 0x553d16 INC	%RCX

    (2493) 0x553d19 VMOVSD	%XMM4,(%R8,%R15,1)

    (2493) 0x553d1f MOV	%R9,(%RSI,%R15,1)

    (2493) 0x553d23 MOV	(%RAX),%R15

    (2493) 0x553d26 CMP	%RDX,%R15

    (2493) 0x553d29 JG	553ca0

  (2492) 0x553d2f MOV	-0x70(%RBP),%RAX

  (2492) 0x553d33 MOV	%RCX,-0xa8(%RBP)

  (2492) 0x553d3a JMP	5539c2

    (2489) 0x553d40 MOV	%RCX,(%R13)

    (2489) 0x553d44 VMOVQ	%XMM8,%RDI

    (2489) 0x553d49 LEA	(,%RCX,8),%R13

    (2489) 0x553d51 INC	%RAX

    (2489) 0x553d54 VMOVSD	%XMM9,(%R9,%R13,1)

    (2489) 0x553d5a MOV	%RSI,(%RDI,%R13,1)

    (2489) 0x553d5e MOV	(%RBX),%RDI

    (2489) 0x553d61 INC	%RCX

    (2489) 0x553d64 CMP	%RAX,%RDI

    (2489) 0x553d67 JG	553bc0

  (2487) 0x553d6d JMP	553bef

    (2490) 0x553d80 MOV	-0x48(%RBP),%RDI

    (2490) 0x553d84 MOV	-0x58(%RBP),%RCX

    (2490) 0x553d88 MOV	%RSI,(%RDX)

    (2490) 0x553d8b LEA	(,%RSI,8),%RDX

    (2490) 0x553d93 INC	%RAX

    (2490) 0x553d96 INC	%RSI

    (2490) 0x553d99 VMOVSD	%XMM6,(%RDI,%RDX,1)

    (2490) 0x553d9e MOV	%R13,(%RCX,%RDX,1)

    (2490) 0x553da2 VMOVQ	%XMM4,%R13

    (2490) 0x553da7 MOV	(%R13),%RDI

    (2490) 0x553dab CMP	%RAX,%RDI

    (2490) 0x553dae JG	553b40

  (2487) 0x553db4 JMP	553b7c

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►97.17+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.83+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_ParMatmul	par_csr_matop.c:998	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.88
Front-end cycles	5.75
P0 cycles	2.17
P1 cycles	2.17
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	46.00
Nb loads	22.00
Nb stores	8.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.14
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	13.33
Vector-efficiency ratio all	13.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.17

Metric	Value
CQA speedup if no scalar integer	2.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.88
Front-end cycles	5.75
P0 cycles	2.17
P1 cycles	2.17
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	46.00
Nb loads	22.00
Nb stores	8.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.14
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	13.33
Vector-efficiency ratio all	13.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 3.00 cycles (2.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 0.87 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.75 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	48
nb uops	46
loop length	243
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	7.00
Overall L1	7.00

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5538db

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 553a4e <hypre_ParMatmul._omp_fn.3+0x39e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R12,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x8(%R12,%R8,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 5539e8 <hypre_ParMatmul._omp_fn.3+0x338>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xe8(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVDQA %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM12,%R10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xa8(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
INCQ -0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RBX,-0xf8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 553db9 <hypre_ParMatmul._omp_fn.3+0x709>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JE 5538c5 <hypre_ParMatmul._omp_fn.3+0x215>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R9,%RSI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x8(%R9,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JGE 5538d7 <hypre_ParMatmul._omp_fn.3+0x227>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x100(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x110(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x108(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %XMM15,%R12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM12,%R9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %R12,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 5538db <hypre_ParMatmul._omp_fn.3+0x22b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 3.00 cycles (2.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.75 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	48
nb uops	46
loop length	243
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00
cycles	2.17	2.17	2.17	2.17	2.17	2.17	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	7.00
Overall L1	7.00

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5538db

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 553a4e <hypre_ParMatmul._omp_fn.3+0x39e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R12,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x8(%R12,%R8,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 5539e8 <hypre_ParMatmul._omp_fn.3+0x338>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xe8(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVDQA %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM12,%R10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xa8(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
INCQ -0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
CMP %RBX,-0xf8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 553db9 <hypre_ParMatmul._omp_fn.3+0x709>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JE 5538c5 <hypre_ParMatmul._omp_fn.3+0x215>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R9,%RSI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x8(%R9,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JGE 5538d7 <hypre_ParMatmul._omp_fn.3+0x227>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x100(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x110(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x108(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %XMM15,%R12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM12,%R9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ %R12,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 5538db <hypre_ParMatmul._omp_fn.3+0x22b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code