OV - exec - Loop 2134

	Loop Id: 2134	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 47.94%

0x5277e0 INC	%RDX

0x5277e3 CMP	%RDX,%RAX

0x5277e6 JE	527d65

0x5277ec MOV	(%R12,%RDX,8),%R8

0x5277f0 LEA	(,%R8,8),%RCX

0x5277f8 LEA	(%R11,%RCX,1),%RSI

0x5277fc VCOMISD	(%RSI),%XMM3

0x527800 JE	5277e0

0x527802 MOV	0x8(%R12,%RDX,8),%R14

0x527807 VMOVQ	%XMM11,%RDI

0x52780c VMOVSD	(%RDI,%RDX,8),%XMM0

0x527811 CMP	%R14,%R8

0x527814 JGE	527a90

0x52781a MOV	%R14,%R13

0x52781d SUB	%R8,%R13

0x527820 LEA	-0x1(%R13),%R15

0x527824 CMP	$0x2,%R15

0x527828 JBE	527a44

0x52782e MOV	%R13,%R15

0x527831 VMOVQ	%XMM4,%RBX

0x527836 VXORPD	%XMM1,%XMM1,%XMM1

0x52783a SHR	$0x2,%R15

0x52783e SAL	$0x5,%R15

0x527842 LEA	(%RBX,%RCX,1),%RDI

0x527846 LEA	-0x20(%R15),%RBX

0x52784a XOR	%ECX,%ECX

0x52784c SHR	$0x5,%RBX

0x527850 INC	%RBX

0x527853 AND	$0x7,%EBX

0x527856 JE	527931

0x52785c CMP	$0x1,%RBX

0x527860 JE	52790e

0x527866 CMP	$0x2,%RBX

0x52786a JE	5278f4

0x527870 CMP	$0x3,%RBX

0x527874 JE	5278da

0x527876 CMP	$0x4,%RBX

0x52787a JE	5278c0

0x52787c CMP	$0x5,%RBX

0x527880 JE	5278a6

0x527882 CMP	$0x6,%RBX

0x527886 JNE	527d90

0x52788c VMOVDQU	(%RDI,%RCX,1),%YMM13

0x527891 KMOVB	%K1,%K7

0x527895 VGATHERQPD	(%R9,%YMM13,8),%YMM14{%K7}

0x52789c VFNMADD231PD	(%RSI,%RCX,1),%YMM14,%YMM1

0x5278a2 ADD	$0x20,%RCX

0x5278a6 VMOVDQU	(%RDI,%RCX,1),%YMM15

0x5278ab KMOVB	%K1,%K5

0x5278af VGATHERQPD	(%R9,%YMM15,8),%YMM12{%K5}

0x5278b6 VFNMADD231PD	(%RSI,%RCX,1),%YMM12,%YMM1

0x5278bc ADD	$0x20,%RCX

0x5278c0 VMOVDQU	(%RDI,%RCX,1),%YMM13

0x5278c5 KMOVB	%K1,%K2

0x5278c9 VGATHERQPD	(%R9,%YMM13,8),%YMM2{%K2}

0x5278d0 VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

0x5278d6 ADD	$0x20,%RCX

0x5278da VMOVDQU	(%RDI,%RCX,1),%YMM14

0x5278df KMOVB	%K1,%K4

0x5278e3 VGATHERQPD	(%R9,%YMM14,8),%YMM15{%K4}

0x5278ea VFNMADD231PD	(%RSI,%RCX,1),%YMM15,%YMM1

0x5278f0 ADD	$0x20,%RCX

0x5278f4 VMOVDQU	(%RDI,%RCX,1),%YMM12

0x5278f9 KMOVB	%K1,%K6

0x5278fd VGATHERQPD	(%R9,%YMM12,8),%YMM13{%K6}

0x527904 VFNMADD231PD	(%RSI,%RCX,1),%YMM13,%YMM1

0x52790a ADD	$0x20,%RCX

0x52790e VMOVDQU	(%RDI,%RCX,1),%YMM14

0x527913 KMOVB	%K1,%K3

0x527917 VGATHERQPD	(%R9,%YMM14,8),%YMM2{%K3}

0x52791e VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

0x527924 ADD	$0x20,%RCX

0x527928 CMP	%R15,%RCX

0x52792b JE	527a17

  (2136) 0x527931 VMOVDQU	(%RDI,%RCX,1),%YMM15

  (2136) 0x527936 VMOVDQU	0x20(%RDI,%RCX,1),%YMM12

  (2136) 0x52793c KMOVB	%K1,%K7

  (2136) 0x527940 KMOVB	%K1,%K5

  (2136) 0x527944 VMOVDQU	0x40(%RDI,%RCX,1),%YMM14

  (2136) 0x52794a KMOVB	%K1,%K2

  (2136) 0x52794e KMOVB	%K1,%K4

  (2136) 0x527952 KMOVB	%K1,%K6

  (2136) 0x527956 KMOVB	%K1,%K3

  (2136) 0x52795a VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K7}

  (2136) 0x527961 VMOVDQU	0x60(%RDI,%RCX,1),%YMM15

  (2136) 0x527967 VFNMADD132PD	(%RSI,%RCX,1),%YMM1,%YMM13

  (2136) 0x52796d KMOVB	%K1,%K7

  (2136) 0x527971 VGATHERQPD	(%R9,%YMM12,8),%YMM1{%K5}

  (2136) 0x527978 VMOVDQU	0x80(%RDI,%RCX,1),%YMM12

  (2136) 0x527981 VFNMADD132PD	0x20(%RSI,%RCX,1),%YMM13,%YMM1

  (2136) 0x527988 VGATHERQPD	(%R9,%YMM14,8),%YMM2{%K2}

  (2136) 0x52798f VFNMADD132PD	0x40(%RSI,%RCX,1),%YMM1,%YMM2

  (2136) 0x527996 KMOVB	%K1,%K5

  (2136) 0x52799a VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K4}

  (2136) 0x5279a1 VMOVDQU	0xc0(%RDI,%RCX,1),%YMM15

  (2136) 0x5279aa VFNMADD132PD	0x60(%RSI,%RCX,1),%YMM2,%YMM13

  (2136) 0x5279b1 VMOVDQU	0xa0(%RDI,%RCX,1),%YMM2

  (2136) 0x5279ba VGATHERQPD	(%R9,%YMM12,8),%YMM14{%K6}

  (2136) 0x5279c1 VMOVDQU	0xe0(%RDI,%RCX,1),%YMM12

  (2136) 0x5279ca VFNMADD132PD	0x80(%RSI,%RCX,1),%YMM13,%YMM14

  (2136) 0x5279d4 VGATHERQPD	(%R9,%YMM2,8),%YMM1{%K3}

  (2136) 0x5279db VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K7}

  (2136) 0x5279e2 VFNMADD132PD	0xa0(%RSI,%RCX,1),%YMM14,%YMM1

  (2136) 0x5279ec VFNMADD132PD	0xc0(%RSI,%RCX,1),%YMM1,%YMM13

  (2136) 0x5279f6 VGATHERQPD	(%R9,%YMM12,8),%YMM1{%K5}

  (2136) 0x5279fd VFNMADD132PD	0xe0(%RSI,%RCX,1),%YMM13,%YMM1

  (2136) 0x527a07 ADD	$0x100,%RCX

  (2136) 0x527a0e CMP	%R15,%RCX

  (2136) 0x527a11 JNE	527931

0x527a17 VEXTRACTF64X2	$0x1,%YMM1,%XMM14

0x527a1e VADDPD	%XMM1,%XMM14,%XMM2

0x527a22 VUNPCKHPD	%XMM2,%XMM2,%XMM15

0x527a26 VADDPD	%XMM2,%XMM15,%XMM13

0x527a2a VADDSD	%XMM13,%XMM0,%XMM0

0x527a2f TEST	$0x3,%R13B

0x527a33 JE	527a90

0x527a35 AND	$-0x4,%R13

0x527a39 ADD	%R13,%R8

0x527a3c LEA	(,%R8,8),%RCX

0x527a44 VMOVQ	%XMM4,%R13

0x527a49 LEA	0x1(%R8),%RDI

0x527a4d MOV	(%R13,%RCX,1),%RSI

0x527a52 VMOVSD	(%R9,%RSI,8),%XMM12

0x527a58 VFNMADD231SD	(%R11,%RCX,1),%XMM12,%XMM0

0x527a5e CMP	%R14,%RDI

0x527a61 JGE	527a90

0x527a63 MOV	0x8(%R13,%RCX,1),%R15

0x527a68 ADD	$0x2,%R8

0x527a6c VMOVSD	0x8(%R11,%RCX,1),%XMM1

0x527a73 VFNMADD231SD	(%R9,%R15,8),%XMM1,%XMM0

0x527a79 CMP	%R8,%R14

0x527a7c JLE	527a90

0x527a7e MOV	0x10(%R13,%RCX,1),%R14

0x527a83 VMOVSD	(%R9,%R14,8),%XMM14

0x527a89 VFNMADD231SD	0x10(%R11,%RCX,1),%XMM14,%XMM0

0x527a90 VMOVQ	%XMM7,%RCX

0x527a95 MOV	(%RCX,%RDX,8),%RBX

0x527a99 MOV	0x8(%RCX,%RDX,8),%R14

0x527a9e CMP	%R14,%RBX

0x527aa1 JGE	527d38

0x527aa7 MOV	%R14,%R13

0x527aaa SUB	%RBX,%R13

0x527aad LEA	-0x1(%R13),%RSI

0x527ab1 CMP	$0x2,%RSI

0x527ab5 JBE	527cdb

0x527abb LEA	(,%RBX,8),%RSI

0x527ac3 VMOVQ	%XMM5,%R15

0x527ac8 VMOVQ	%XMM6,%RDI

0x527acd XOR	%ECX,%ECX

0x527acf ADD	%RSI,%RDI

0x527ad2 ADD	%R15,%RSI

0x527ad5 MOV	%R13,%R15

0x527ad8 VXORPD	%XMM1,%XMM1,%XMM1

0x527adc SHR	$0x2,%R15

0x527ae0 SAL	$0x5,%R15

0x527ae4 LEA	-0x20(%R15),%R8

0x527ae8 SHR	$0x5,%R8

0x527aec INC	%R8

0x527aef AND	$0x7,%R8D

0x527af3 JE	527bce

0x527af9 CMP	$0x1,%R8

0x527afd JE	527bab

0x527b03 CMP	$0x2,%R8

0x527b07 JE	527b91

0x527b0d CMP	$0x3,%R8

0x527b11 JE	527b77

0x527b13 CMP	$0x4,%R8

0x527b17 JE	527b5d

0x527b19 CMP	$0x5,%R8

0x527b1d JE	527b43

0x527b1f CMP	$0x6,%R8

0x527b23 JNE	527db0

0x527b29 VMOVDQU	(%RDI,%RCX,1),%YMM13

0x527b2e KMOVB	%K1,%K4

0x527b32 VGATHERQPD	(%R10,%YMM13,8),%YMM12{%K4}

0x527b39 VFNMADD231PD	(%RSI,%RCX,1),%YMM12,%YMM1

0x527b3f ADD	$0x20,%RCX

0x527b43 VMOVDQU	(%RDI,%RCX,1),%YMM14

0x527b48 KMOVB	%K1,%K6

0x527b4c VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K6}

0x527b53 VFNMADD231PD	(%RSI,%RCX,1),%YMM15,%YMM1

0x527b59 ADD	$0x20,%RCX

0x527b5d VMOVDQU	(%RDI,%RCX,1),%YMM13

0x527b62 KMOVB	%K1,%K3

0x527b66 VGATHERQPD	(%R10,%YMM13,8),%YMM2{%K3}

0x527b6d VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

0x527b73 ADD	$0x20,%RCX

0x527b77 VMOVDQU	(%RDI,%RCX,1),%YMM12

0x527b7c KMOVB	%K1,%K7

0x527b80 VGATHERQPD	(%R10,%YMM12,8),%YMM14{%K7}

0x527b87 VFNMADD231PD	(%RSI,%RCX,1),%YMM14,%YMM1

0x527b8d ADD	$0x20,%RCX

0x527b91 VMOVDQU	(%RDI,%RCX,1),%YMM15

0x527b96 KMOVB	%K1,%K5

0x527b9a VGATHERQPD	(%R10,%YMM15,8),%YMM13{%K5}

0x527ba1 VFNMADD231PD	(%RSI,%RCX,1),%YMM13,%YMM1

0x527ba7 ADD	$0x20,%RCX

0x527bab VMOVDQU	(%RDI,%RCX,1),%YMM12

0x527bb0 KMOVB	%K1,%K2

0x527bb4 VGATHERQPD	(%R10,%YMM12,8),%YMM2{%K2}

0x527bbb VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

0x527bc1 ADD	$0x20,%RCX

0x527bc5 CMP	%RCX,%R15

0x527bc8 JE	527cb4

  (2135) 0x527bce VMOVDQU	(%RDI,%RCX,1),%YMM14

  (2135) 0x527bd3 VMOVDQU	0x20(%RDI,%RCX,1),%YMM13

  (2135) 0x527bd9 KMOVB	%K1,%K4

  (2135) 0x527bdd KMOVB	%K1,%K6

  (2135) 0x527be1 VMOVDQU	0x40(%RDI,%RCX,1),%YMM12

  (2135) 0x527be7 KMOVB	%K1,%K3

  (2135) 0x527beb KMOVB	%K1,%K7

  (2135) 0x527bef KMOVB	%K1,%K5

  (2135) 0x527bf3 KMOVB	%K1,%K2

  (2135) 0x527bf7 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K4}

  (2135) 0x527bfe VMOVDQU	0x60(%RDI,%RCX,1),%YMM14

  (2135) 0x527c04 VFNMADD132PD	(%RSI,%RCX,1),%YMM1,%YMM15

  (2135) 0x527c0a KMOVB	%K1,%K4

  (2135) 0x527c0e VGATHERQPD	(%R10,%YMM13,8),%YMM1{%K6}

  (2135) 0x527c15 VMOVDQU	0x80(%RDI,%RCX,1),%YMM13

  (2135) 0x527c1e VFNMADD132PD	0x20(%RSI,%RCX,1),%YMM15,%YMM1

  (2135) 0x527c25 VGATHERQPD	(%R10,%YMM12,8),%YMM2{%K3}

  (2135) 0x527c2c VMOVDQU	0xa0(%RDI,%RCX,1),%YMM12

  (2135) 0x527c35 VFNMADD132PD	0x40(%RSI,%RCX,1),%YMM1,%YMM2

  (2135) 0x527c3c KMOVB	%K1,%K6

  (2135) 0x527c40 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K7}

  (2135) 0x527c47 VMOVDQU	0xc0(%RDI,%RCX,1),%YMM14

  (2135) 0x527c50 VFNMADD132PD	0x60(%RSI,%RCX,1),%YMM2,%YMM15

  (2135) 0x527c57 VGATHERQPD	(%R10,%YMM13,8),%YMM2{%K5}

  (2135) 0x527c5e VMOVDQU	0xe0(%RDI,%RCX,1),%YMM13

  (2135) 0x527c67 VFNMADD132PD	0x80(%RSI,%RCX,1),%YMM15,%YMM2

  (2135) 0x527c71 VGATHERQPD	(%R10,%YMM12,8),%YMM1{%K2}

  (2135) 0x527c78 VFNMADD132PD	0xa0(%RSI,%RCX,1),%YMM2,%YMM1

  (2135) 0x527c82 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K4}

  (2135) 0x527c89 VFNMADD132PD	0xc0(%RSI,%RCX,1),%YMM1,%YMM15

  (2135) 0x527c93 VGATHERQPD	(%R10,%YMM13,8),%YMM1{%K6}

  (2135) 0x527c9a VFNMADD132PD	0xe0(%RSI,%RCX,1),%YMM15,%YMM1

  (2135) 0x527ca4 ADD	$0x100,%RCX

  (2135) 0x527cab CMP	%RCX,%R15

  (2135) 0x527cae JNE	527bce

0x527cb4 VEXTRACTF64X2	$0x1,%YMM1,%XMM2

0x527cbb VADDPD	%XMM1,%XMM2,%XMM12

0x527cbf VUNPCKHPD	%XMM12,%XMM12,%XMM14

0x527cc4 VADDPD	%XMM12,%XMM14,%XMM15

0x527cc9 VADDSD	%XMM15,%XMM0,%XMM0

0x527cce TEST	$0x3,%R13B

0x527cd2 JE	527d38

0x527cd4 AND	$-0x4,%R13

0x527cd8 ADD	%R13,%RBX

0x527cdb LEA	(,%RBX,8),%R13

0x527ce3 VMOVQ	%XMM6,%RSI

0x527ce8 VMOVQ	%XMM5,%RDI

0x527ced LEA	0x1(%RBX),%R8

0x527cf1 MOV	(%RSI,%R13,1),%R15

0x527cf5 VMOVSD	(%RDI,%R13,1),%XMM13

0x527cfb VFNMADD231SD	(%R10,%R15,8),%XMM13,%XMM0

0x527d01 CMP	%R14,%R8

0x527d04 JGE	527d38

0x527d06 MOV	0x8(%RSI,%R13,1),%RSI

0x527d0b ADD	$0x2,%RBX

0x527d0f VMOVSD	0x8(%RDI,%R13,1),%XMM1

0x527d16 VMOVQ	%XMM6,%RCX

0x527d1b VFNMADD231SD	(%R10,%RSI,8),%XMM1,%XMM0

0x527d21 CMP	%R14,%RBX

0x527d24 JGE	527d38

0x527d26 MOV	0x10(%RCX,%R13,1),%R14

0x527d2b VMOVSD	(%R10,%R14,8),%XMM2

0x527d31 VFNMADD231SD	0x10(%RDI,%R13,1),%XMM2,%XMM0

0x527d38 VMOVQ	%XMM8,%R8

0x527d3d VMOVQ	%XMM9,%R13

0x527d42 VMULSD	%XMM0,%XMM10,%XMM0

0x527d46 VDIVSD	(%R13,%RDX,8),%XMM0,%XMM12

0x527d4d VADDSD	(%R8,%RDX,8),%XMM12,%XMM14

0x527d53 VMOVSD	%XMM14,(%R8,%RDX,8)

0x527d59 INC	%RDX

0x527d5c CMP	%RDX,%RAX

0x527d5f JNE	5277ec

0x527d90 VMOVDQU	(%RDI),%YMM12

0x527d94 KMOVB	%K1,%K3

0x527d98 MOV	$0x20,%ECX

0x527d9d VGATHERQPD	(%R9,%YMM12,8),%YMM2{%K3}

0x527da4 VFNMADD231PD	(%RSI),%YMM2,%YMM1

0x527da9 JMP	52788c

0x527db0 VMOVDQU	(%RDI),%YMM15

0x527db4 KMOVB	%K1,%K2

0x527db8 MOV	$0x20,%ECX

0x527dbd VGATHERQPD	(%R10,%YMM15,8),%YMM2{%K2}

0x527dc4 VFNMADD231PD	(%RSI),%YMM2,%YMM1

0x527dc9 JMP	527b29

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
►96.67+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.91+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.24
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	3.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	67.63
CQA cycles if no scalar integer	54.75
CQA cycles if FP arith vectorized	43.69
CQA cycles if fully vectorized	21.81
Front-end cycles	67.63
P0 cycles	17.50
P1 cycles	17.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	27.75
P7 cycles	27.75
P8 cycles	27.75
P9 cycles	27.75
P10 cycles	29.50
P11 cycles	29.50
P12 cycles	29.50
P13 cycles	29.50
P14 cycles	48.50
P15 cycles	48.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	218.00
Nb uops	541.00
Nb loads	68.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	62.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.07
Bytes prefetched	0.00
Bytes loaded	1552.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	47.17
Vectorization ratio load	72.41
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	57.14
Vectorization ratio fma	70.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	32.73
Vector-efficiency ratio all	28.30
Vector-efficiency ratio load	39.66
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	19.64
Vector-efficiency ratio fma	38.75
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	22.95

Metric	Value
CQA speedup if no scalar integer	1.24
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	3.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	67.63
CQA cycles if no scalar integer	54.75
CQA cycles if FP arith vectorized	43.69
CQA cycles if fully vectorized	21.81
Front-end cycles	67.63
P0 cycles	17.50
P1 cycles	17.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	27.75
P7 cycles	27.75
P8 cycles	27.75
P9 cycles	27.75
P10 cycles	29.50
P11 cycles	29.50
P12 cycles	29.50
P13 cycles	29.50
P14 cycles	48.50
P15 cycles	48.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	218.00
Nb uops	541.00
Nb loads	68.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	62.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.07
Bytes prefetched	0.00
Bytes loaded	1552.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	47.17
Vectorization ratio load	72.41
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	57.14
Vectorization ratio fma	70.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	32.73
Vector-efficiency ratio all	28.30
Vector-efficiency ratio load	39.66
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	19.64
Vector-efficiency ratio fma	38.75
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	22.95

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4097 paths individually, rerun with max-paths=4097
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4097 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.63 to 54.75 cycles (1.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions).

Details

47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
57% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
70% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 62 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3669
VGATHERQPD: 14 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF64X2: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 14 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 14 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 137 FP arithmetical operations:

73: addition or subtraction (62 inside FMA instructions)
63: multiply (62 inside FMA instructions)
1: divide

The binary loop is loading 1552 bytes (194 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	218
nb uops	541
loop length	1013
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	6
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.63 cycles
front end	67.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	17.50	17.50	17.50	17.50	17.50	17.50	27.75	27.75	27.75	27.75	29.50	29.50	29.50	29.50	48.50	48.50
cycles	17.50	17.50	17.50	17.50	17.50	17.50	27.75	27.75	27.75	27.75	29.50	29.50	29.50	29.50	48.50	48.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	67.63
Dispatch	48.50
DIV/SQRT	4.00
Overall L1	67.63

Vectorization ratios

INT

all	29%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	63%
store	0%
mul	0%
add-sub	57%
fma	70%
div/sqrt	0%
other	85%

INT+FP

all	47%
load	72%
store	0%
mul	0%
add-sub	57%
fma	70%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	23%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	32%
load	36%
store	12%
mul	12%
add-sub	19%
fma	38%
div/sqrt	12%
other	39%

INT+FP

all	28%
load	39%
store	12%
mul	12%
add-sub	19%
fma	38%
div/sqrt	12%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.63 cycles. At this rate:

8% of peak load performance is reached (22.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 67.63 to 48.50 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 5277ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527d65 <hypre_ParCSRRelaxThreads._omp_fn.1+0x625>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RCX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VCOMISD (%RSI),%XMM3	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 5277e0 <hypre_ParCSRRelaxThreads._omp_fn.1+0xa0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R12,%RDX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R13),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 527a44 <hypre_ParCSRRelaxThreads._omp_fn.1+0x304>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM4,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RCX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%R15),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x5,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527931 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 52790e <hypre_ParCSRRelaxThreads._omp_fn.1+0x1ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278f4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278da <hypre_ParCSRRelaxThreads._omp_fn.1+0x19a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278c0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278a6 <hypre_ParCSRRelaxThreads._omp_fn.1+0x166>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 527d90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x650>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM13,8),%YMM14{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM15,8),%YMM12{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM12,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM13,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM14,8),%YMM15{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM12,8),%YMM13{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM14,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527a17 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM2,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM2,%XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
TEST $0x3,%R13B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R13,%RCX,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%RSI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R11,%RCX,1),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R13,%RCX,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%R11,%RCX,1),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R9,%R15,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%R13,%RCX,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%R14,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD 0x10(%R11,%RCX,1),%XMM14,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RCX,%RDX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R13),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 527cdb <hypre_ParCSRRelaxThreads._omp_fn.1+0x59b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM5,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%R15),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527bce <hypre_ParCSRRelaxThreads._omp_fn.1+0x48e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527bab <hypre_ParCSRRelaxThreads._omp_fn.1+0x46b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b91 <hypre_ParCSRRelaxThreads._omp_fn.1+0x451>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b77 <hypre_ParCSRRelaxThreads._omp_fn.1+0x437>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b5d <hypre_ParCSRRelaxThreads._omp_fn.1+0x41d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b43 <hypre_ParCSRRelaxThreads._omp_fn.1+0x403>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 527db0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x670>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM13,8),%YMM12{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM12,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM14,8),%YMM15{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM13,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM12,8),%YMM14{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM15,8),%YMM13{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM12,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527cb4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x574>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM12,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
TEST $0x3,%R13B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%RBX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM5,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RSI,%R13,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%R13,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R10,%R15,8),%XMM13,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RSI,%R13,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RDI,%R13,1),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD231SD (%R10,%RSI,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RCX,%R13,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R10,%R14,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD 0x10(%RDI,%R13,1),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD (%R13,%RDX,8),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD (%R8,%RDX,8),%XMM12,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM14,(%R8,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5277ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R9,%YMM12,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JMP 52788c <hypre_ParCSRRelaxThreads._omp_fn.1+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQU (%RDI),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R10,%YMM15,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JMP 527b29 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4097 paths individually, rerun with max-paths=4097
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions).

Details

47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
57% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
70% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 62 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3669
VGATHERQPD: 14 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF64X2: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 14 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3675
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3680

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 137 FP arithmetical operations:

73: addition or subtraction (62 inside FMA instructions)
63: multiply (62 inside FMA instructions)
1: divide

The binary loop is loading 1552 bytes (194 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	218
nb uops	541
loop length	1013
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	6
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.63 cycles
front end	67.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	17.50	17.50	17.50	17.50	17.50	17.50	27.75	27.75	27.75	27.75	29.50	29.50	29.50	29.50	48.50	48.50
cycles	17.50	17.50	17.50	17.50	17.50	17.50	27.75	27.75	27.75	27.75	29.50	29.50	29.50	29.50	48.50	48.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	67.63
Dispatch	48.50
DIV/SQRT	4.00
Overall L1	67.63

Vectorization ratios

INT

all	29%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	63%
store	0%
mul	0%
add-sub	57%
fma	70%
div/sqrt	0%
other	85%

INT+FP

all	47%
load	72%
store	0%
mul	0%
add-sub	57%
fma	70%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	23%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	32%
load	36%
store	12%
mul	12%
add-sub	19%
fma	38%
div/sqrt	12%
other	39%

INT+FP

all	28%
load	39%
store	12%
mul	12%
add-sub	19%
fma	38%
div/sqrt	12%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.63 cycles. At this rate:

8% of peak load performance is reached (22.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5277ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527d65 <hypre_ParCSRRelaxThreads._omp_fn.1+0x625>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RCX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VCOMISD (%RSI),%XMM3	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 5277e0 <hypre_ParCSRRelaxThreads._omp_fn.1+0xa0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R12,%RDX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R13),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 527a44 <hypre_ParCSRRelaxThreads._omp_fn.1+0x304>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM4,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RCX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%R15),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x5,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527931 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 52790e <hypre_ParCSRRelaxThreads._omp_fn.1+0x1ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278f4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278da <hypre_ParCSRRelaxThreads._omp_fn.1+0x19a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278c0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5278a6 <hypre_ParCSRRelaxThreads._omp_fn.1+0x166>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 527d90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x650>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM13,8),%YMM14{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM15,8),%YMM12{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM12,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM13,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM14,8),%YMM15{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM12,8),%YMM13{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R9,%YMM14,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527a17 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM2,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM2,%XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
TEST $0x3,%R13B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R13,%RCX,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%RSI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R11,%RCX,1),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R13,%RCX,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%R11,%RCX,1),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R9,%R15,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 527a90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%R13,%RCX,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%R14,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD 0x10(%R11,%RCX,1),%XMM14,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RCX,%RDX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R13),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 527cdb <hypre_ParCSRRelaxThreads._omp_fn.1+0x59b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM5,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SHR $0x2,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%R15),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527bce <hypre_ParCSRRelaxThreads._omp_fn.1+0x48e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527bab <hypre_ParCSRRelaxThreads._omp_fn.1+0x46b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b91 <hypre_ParCSRRelaxThreads._omp_fn.1+0x451>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b77 <hypre_ParCSRRelaxThreads._omp_fn.1+0x437>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b5d <hypre_ParCSRRelaxThreads._omp_fn.1+0x41d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527b43 <hypre_ParCSRRelaxThreads._omp_fn.1+0x403>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 527db0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x670>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM13,8),%YMM12{%K4}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM12,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM14,8),%YMM15{%K6}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM15,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM13,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM12,8),%YMM14{%K7}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM14,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM15,8),%YMM13{%K5}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU (%RDI,%RCX,1),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R10,%YMM12,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI,%RCX,1),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 527cb4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x574>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTF64X2 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM12,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
TEST $0x3,%R13B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%RBX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM5,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RSI,%R13,1),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%R13,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD (%R10,%R15,8),%XMM13,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RSI,%R13,1),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RDI,%R13,1),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFNMADD231SD (%R10,%RSI,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d38 <hypre_ParCSRRelaxThreads._omp_fn.1+0x5f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RCX,%R13,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R10,%R14,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFNMADD231SD 0x10(%RDI,%R13,1),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD (%R13,%RDX,8),%XMM0,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD (%R8,%RDX,8),%XMM12,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM14,(%R8,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5277ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQU (%RDI),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R9,%YMM12,8),%YMM2{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JMP 52788c <hypre_ParCSRRelaxThreads._omp_fn.1+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQU (%RDI),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VGATHERQPD (%R10,%YMM15,8),%YMM2{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFNMADD231PD (%RSI),%YMM2,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JMP 527b29 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code